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[Linux-mips-commits]CVS: linux/include/asm-mips64 bootinfo.h,1.4,1.5 cpu.h,1.3,1.4 mipsregs.h,1.6,1.7 pci.h,1.7,1.8 smp.h,1.4,1.5
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From: James S. <jsi...@us...> - 2001-11-26 17:21:34
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Update of /cvsroot/linux-mips/linux/include/asm-mips64
In directory usw-pr-cvs1:/tmp/cvs-serv18886
Modified Files:
bootinfo.h cpu.h mipsregs.h pci.h smp.h
Log Message:
Synced mips64 stuff to OSS tree.
Index: bootinfo.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips64/bootinfo.h,v
retrieving revision 1.4
retrieving revision 1.5
diff -u -d -r1.4 -r1.5
--- bootinfo.h 2001/11/19 17:35:09 1.4
+++ bootinfo.h 2001/11/26 17:21:32 1.5
@@ -178,11 +178,8 @@
char dummy[32];
};
-extern unsigned long mips_memory_upper;
-extern unsigned long mips_cputype;
extern unsigned long mips_machtype;
extern unsigned long mips_machgroup;
-extern unsigned long mips_tlb_entries;
/*
* A memory map that's built upon what was determined
Index: cpu.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips64/cpu.h,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- cpu.h 2001/11/21 22:11:00 1.3
+++ cpu.h 2001/11/26 17:21:32 1.4
@@ -90,13 +90,24 @@
#define PRID_REV_TX3927C 0x0042
#define PRID_REV_TX39H3TEG 0x0050
+/*
+ * FPU implementation/revision register (CP1 control register 0).
+ *
+ * +---------------------------------+----------------+----------------+
+ * | 0 | Implementation | Revision |
+ * +---------------------------------+----------------+----------------+
+ * 31 16 15 8 7 0
+ */
+
+#define FPIR_IMP_NONE 0x0000
+
#ifndef _LANGUAGE_ASSEMBLY
/*
* Capability and feature descriptor structure for MIPS CPU
*/
struct mips_cpu {
unsigned int processor_id;
- unsigned int cputype; /* Old "mips_cputype" code */
+ unsigned int cputype;
int isa_level;
int options;
int tlbsize;
@@ -137,5 +148,6 @@
#define MIPS_CPU_VCE 0x00000400 /* virt. coherence conflict possible */
#define MIPS_CPU_CACHE_CDEX 0x00000800 /* Create_Dirty_Exclusive CACHE op */
#define MIPS_CPU_MCHECK 0x00001000 /* Machine check exception */
+#define MIPS_CPU_EJTAG 0x00002000 /* EJTAG exception */
#endif /* _ASM_CPU_H */
Index: mipsregs.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips64/mipsregs.h,v
retrieving revision 1.6
retrieving revision 1.7
diff -u -d -r1.6 -r1.7
--- mipsregs.h 2001/11/19 17:35:09 1.6
+++ mipsregs.h 2001/11/26 17:21:32 1.7
@@ -319,6 +319,19 @@
:"=r" (__res)); \
__res;})
+/*
+ * Macros to access the floating point coprocessor control registers
+ */
+#define read_32bit_cp1_register(source) \
+({ int __res; \
+ __asm__ __volatile__( \
+ ".set\tpush\n\t" \
+ ".set\treorder\n\t" \
+ "cfc1\t%0,"STR(source)"\n\t" \
+ ".set\tpop" \
+ : "=r" (__res)); \
+ __res;})
+
/* TLB operations. */
static inline void tlb_probe(void)
{
Index: pci.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips64/pci.h,v
retrieving revision 1.7
retrieving revision 1.8
diff -u -d -r1.7 -r1.8
--- pci.h 2001/11/12 18:38:46 1.7
+++ pci.h 2001/11/26 17:21:32 1.8
@@ -103,7 +103,7 @@
if (direction == PCI_DMA_NONE)
BUG();
-#ifndef CONFIG_COHERENT_IO
+#ifdef CONFIG_NONCOHERENT_IO
dma_cache_wback_inv((unsigned long)ptr, size);
#endif
return virt_to_bus(ptr);
@@ -140,7 +140,7 @@
BUG();
addr = (unsigned long) page_address(page) + offset;
-#ifndef CONFIG_COHERENT_IO
+#ifdef CONFIG_NONCOHERENT_IO
dma_cache_wback_inv(addr, size);
#endif
@@ -174,14 +174,16 @@
static inline int pci_map_sg(struct pci_dev *hwdev, struct scatterlist *sg,
int nents, int direction)
{
+#ifdef CONFIG_NONCOHERENT_IO
int i;
+#endif
if (direction == PCI_DMA_NONE)
BUG();
/* Make sure that gcc doesn't leave the empty loop body. */
for (i = 0; i < nents; i++, sg++) {
-#ifndef CONFIG_COHERENT_IO
+#ifdef CONFIG_NONCOHERENT_IO
dma_cache_wback_inv((unsigned long)sg->address, sg->length);
#endif
sg->address = (char *)(bus_to_baddr[hwdev->bus->number] | __pa(sg->address));
@@ -220,7 +222,7 @@
{
if (direction == PCI_DMA_NONE)
BUG();
-#ifndef CONFIG_COHERENT_IO
+#ifdef CONFIG_NONCOHERENT_IO
dma_cache_wback_inv((unsigned long)__va(dma_handle - bus_to_baddr[hwdev->bus->number]), size);
#endif
}
@@ -236,7 +238,7 @@
struct scatterlist *sg,
int nelems, int direction)
{
-#ifndef CONFIG_COHERENT_IO
+#ifdef CONFIG_NONCOHERENT_IO
int i;
#endif
@@ -244,7 +246,7 @@
BUG();
/* Make sure that gcc doesn't leave the empty loop body. */
-#ifndef CONFIG_COHERENT_IO
+#ifdef CONFIG_NONCOHERENT_IO
for (i = 0; i < nelems; i++, sg++)
dma_cache_wback_inv((unsigned long)sg->address, sg->length);
#endif
Index: smp.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips64/smp.h,v
retrieving revision 1.4
retrieving revision 1.5
diff -u -d -r1.4 -r1.5
--- smp.h 2001/11/06 00:30:47 1.4
+++ smp.h 2001/11/26 17:21:32 1.5
@@ -68,6 +68,16 @@
#error cpumask macros only defined for 128p kernels
#endif
+struct call_data_struct {
+ void (*func)(void *);
+ void *info;
+ atomic_t started;
+ atomic_t finished;
+ int wait;
+};
+
+extern struct call_data_struct *call_data;
+
extern cpumask_t cpu_online_map;
#endif /* __ASM_SMP_H */
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