From: James S. <jsi...@us...> - 2001-11-21 22:12:45
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Update of /cvsroot/linux-mips/linux/arch/mips/mm In directory usw-pr-cvs1:/tmp/cvs-serv7001 Modified Files: c-sb1.c Log Message: Remove SMP braindamage without replacement. Index: c-sb1.c =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips/mm/c-sb1.c,v retrieving revision 1.3 retrieving revision 1.4 diff -u -d -r1.3 -r1.4 --- c-sb1.c 2001/11/19 17:59:43 1.3 +++ c-sb1.c 2001/11/21 22:12:42 1.4 @@ -39,9 +39,6 @@ static unsigned int dcache_sets; static unsigned int tlb_entries; -/* Define this to be insanely conservative (e.g. flush everything, lots) */ -#undef SB1_TLB_CONSERVATIVE -#undef SB1_CACHE_CONSERVATIVE void pgd_init(unsigned long page) { unsigned long *p = (unsigned long *) page; @@ -72,7 +69,7 @@ * to flush it */ -static void _sb1_flush_cache_all(void) +static void sb1_flush_cache_all(void) { /* @@ -83,7 +80,7 @@ * $1 - moving cache index * $2 - set count */ - if (icache_sets) { + if (icache_sets) { if (dcache_sets) { __asm__ __volatile__ ( ".set push \n" @@ -96,10 +93,12 @@ " bnez %1, 1b \n" /* loop test */ " addu $1, $1, %0 \n" /* Next address */ ".set pop \n" - ::"r" (dcache_line_size), - "r" (dcache_sets * dcache_assoc), - "r" (KSEG0) - :"$1"); + : + : "r" (dcache_line_size), + "r" (dcache_sets * dcache_assoc), + "r" (KSEG0) + "i" (Index_Writeback_Inv_D)); + __asm__ __volatile__ ( ".set push \n" ".set noreorder \n" @@ -116,31 +115,20 @@ ".set noat \n" ".set mips4 \n" " move $1, %2 \n" /* Start at index 0 */ - "1: cache 0, 0($1) \n" /* Invalidate this index */ + "1: cache %3, 0($1) \n" /* Invalidate this index */ " addiu %1, %1, -1 \n" /* Decrement loop count */ " bnez %1, 1b \n" /* loop test */ " addu $1, $1, %0 \n" /* Next address */ ".set pop \n" - ::"r" (icache_line_size), - "r" (icache_sets * icache_assoc), - "r" (KSEG0) + : + : "r" (icache_line_size), + "r" (icache_sets * icache_assoc), + "r" (KSEG0), + "i" (Index_Invalidate_I) :"$1"); } } -#ifdef CONFIG_SMP -static void sb1_flush_cache_all_ipi(void *ignored) -{ - _sb1_flush_cache_all(); -} -#endif - -static void sb1_flush_cache_all(void) -{ - smp_call_function(sb1_flush_cache_all_ipi, 0, 1, 1); - _sb1_flush_cache_all(); -} - /* * When flushing a range in the icache, we have to first writeback * the dcache for the same range, so new ifetches will see any @@ -155,7 +143,7 @@ * */ -static void _sb1_flush_icache_range(unsigned long start, unsigned long end) +static void sb1_flush_icache_range(unsigned long start, unsigned long end) { if (icache_sets) { if (dcache_sets) { @@ -232,40 +220,6 @@ } } -/* XXXKW how should I pass these instead? */ -unsigned long flush_range_start; -unsigned long flush_range_end; - -#if defined(CONFIG_SMP) && !defined(SB1_CACHE_CONSERVATIVE) - -static void sb1_flush_icache_range_ipi(void *ignored) -{ - _sb1_flush_icache_range(flush_range_start, flush_range_end); -} -#endif - -static void sb1_flush_icache_range(unsigned long start, unsigned long end) -{ -#ifdef SB1_CACHE_CONSERVATIVE - sb1_flush_cache_all(); -#else - if (start == end) { - return; - } - start &= ~((long)(dcache_line_size - 1)); - end = (end - 1) & ~((long)(dcache_line_size - 1)); - - if ((end-start) >= (16*1024*1024)) { - sb1_flush_cache_all(); - } else { - _sb1_flush_icache_range(start, end); - flush_range_start = start; - flush_range_end = end; - smp_call_function(sb1_flush_icache_range_ipi, 0, 1, 1); - } -#endif -} - /* * If there's no context yet, or the page isn't executable, no icache flush * is needed @@ -279,11 +233,12 @@ } addr = (unsigned long)page_address(page); - /* XXXKW addr is a Kseg0 address, whereas hidden higher up the - call stack, we may really need to flush a Useg address. - Our Icache is virtually tagged, which means we have to be - super conservative. See comments in - _sb1_flush_icache_rage. */ + /* + * XXXKW addr is a Kseg0 address, whereas hidden higher up the call + * stack, we may really need to flush a Useg address. Our Icache is + * virtually tagged, which means we have to be super conservative. + * See comments in sb1_flush_icache_rage. + */ sb1_flush_icache_range(addr, addr + PAGE_SIZE); } |