[Linux-mips-commits]CVS: linux/include/asm-mips64 bootinfo.h,1.3,1.4 mipsregs.h,1.5,1.6 mmu_context.h,1.2,1.3 processor.h,1.6,1.7

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/include/asm-mips64
In directory usw-pr-cvs1:/tmp/cvs-serv23403

Modified Files:
	bootinfo.h mipsregs.h mmu_context.h processor.h 
Log Message:
Update from 32-bit versions. A few other synced to OSS tree.

Index: bootinfo.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips64/bootinfo.h,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- bootinfo.h	2001/10/27 17:28:55	1.3
+++ bootinfo.h	2001/11/19 17:35:09	1.4
@@ -134,13 +134,32 @@
 #define CPU_R5000A		25
 #define CPU_R4640		26
 #define CPU_NEVADA		27	/* RM5230, RM5260 */
-#define CPU_LAST		27
+#define CPU_RM7000		28
+#define CPU_R5432		29
+#define CPU_4KC			30
+#define CPU_5KC			31
+#define CPU_R4310		32
+#define CPU_SB1			33
+#define CPU_TX3912		34
+#define CPU_TX3922		35
+#define CPU_TX3927		36
+#define CPU_AU1000		37
+#define CPU_4KEC		38
+#define CPU_4KSC		39
+#define CPU_VR41XX		40
+#define CPU_R5500		41
+#define CPU_TX49XX		42
+#define CPU_TX39XX		43
+#define CPU_LAST		43
 
 #define CPU_NAMES { "unknown", "R2000", "R3000", "R3000A", "R3041", "R3051", \
         "R3052", "R3081", "R3081E", "R4000PC", "R4000SC", "R4000MC",         \
         "R4200", "R4400PC", "R4400SC", "R4400MC", "R4600", "R6000",          \
         "R6000A", "R8000", "R10000", "R4300", "R4650", "R4700", "R5000",     \
-        "R5000A", "R4640", "Nevada" }
+        "R5000A", "R4640", "Nevada", "RM7000", "R5432", "MIPS 4Kc",          \
+        "MIPS 5Kc", "R4310", "SiByte SB1", "TX3912", "TX3922", "TX3927",     \
+	"Au1000", "MIPS 4KEc", "MIPS 4KSc", "NEC Vr41xx", "R5500", "TX49xx", \
+	"TX39xx" }
 
 #define CL_SIZE      (80)
 

Index: mipsregs.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips64/mipsregs.h,v
retrieving revision 1.5
retrieving revision 1.6
diff -u -d -r1.5 -r1.6
--- mipsregs.h	2001/10/31 18:26:52	1.5
+++ mipsregs.h	2001/11/19 17:35:09	1.6
@@ -301,6 +301,24 @@
         ".set\tmips0"                                           \
         : : "r" (value))
 
+/* 
+ * This should be changed when we get a compiler that support the MIPS32 ISA. 
+ */
+#define read_mips32_cp0_config1()                               \
+({ int __res;                                                   \
+        __asm__ __volatile__(                                   \
+	".set\tnoreorder\n\t"                                   \
+	".set\tnoat\n\t"                                        \
+	"#.set\tmips64\n\t"					\
+	"#mfc0\t$1, $16, 1\n\t"					\
+	"#.set\tmips0\n\t"					\
+     	".word\t0x40018001\n\t"                                 \
+	"move\t%0,$1\n\t"                                       \
+	".set\tat\n\t"                                          \
+	".set\treorder"                                         \
+	:"=r" (__res));                                         \
+        __res;})
+
 /* TLB operations. */
 static inline void tlb_probe(void)
 {

Index: mmu_context.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips64/mmu_context.h,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -d -r1.2 -r1.3
--- mmu_context.h	2001/10/31 18:26:52	1.2
+++ mmu_context.h	2001/11/19 17:35:09	1.3
@@ -52,7 +52,7 @@
 #define ASID_FIRST_VERSION ((unsigned long)(~ASID_VERSION_MASK) + 1)
 
 static inline void
-get_new_cpu_mmu_context(struct mm_struct *mm, unsigned long cpu)
+get_new_mmu_context(struct mm_struct *mm, unsigned long cpu)
 {
 	unsigned long asid = ASID_CACHE(cpu);
 
@@ -92,7 +92,7 @@
 {
 	/* Check if our ASID is of an older version and thus invalid */
 	if ((CPU_CONTEXT(cpu, next) ^ ASID_CACHE(cpu)) & ASID_VERSION_MASK)
-		get_new_cpu_mmu_context(next, cpu);
+		get_new_mmu_context(next, cpu);
 
 	set_entryhi(CPU_CONTEXT(cpu, next));
 	TLBMISS_HANDLER_SETUP_PGD(next->pgd);
@@ -118,7 +118,7 @@
 activate_mm(struct mm_struct *prev, struct mm_struct *next)
 {
 	/* Unconditionally get a new ASID.  */
-	get_new_cpu_mmu_context(next, smp_processor_id());
+	get_new_mmu_context(next, smp_processor_id());
 
 	set_entryhi(CPU_CONTEXT(smp_processor_id(), next));
 	TLBMISS_HANDLER_SETUP_PGD(next->pgd);

Index: processor.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips64/processor.h,v
retrieving revision 1.6
retrieving revision 1.7
diff -u -d -r1.6 -r1.7
--- processor.h	2001/11/06 00:30:47	1.6
+++ processor.h	2001/11/19 17:35:09	1.7
@@ -157,11 +157,17 @@
 };
 
 /*
- * FIXME: no fpu emulator yet (but who cares anyway?)
+ * It would be nice to add some more fields for emulator statistics, but there
+ * are a number of fixed offsets in offset.h and elsewhere that would have to
+ * be recalculated by hand.  So the additional information will be private to
+ * the FPU emulator for now.  See asm-mips/fpu_emulator.h.
  */
+typedef u64 fpureg_t;
 struct mips_fpu_soft_struct {
-	long	dummy;
+	fpureg_t	regs[NUM_FPU_REGS];
+	unsigned int	sr;
 };
+
 
 union mips_fpu_union {
         struct mips_fpu_hard_struct hard;