[Linux-mips-commits]CVS: linux/arch/mips/mm tlb-r4k.c,1.2,1.3

[Pete P. <pp...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips/mm
In directory usw-pr-cvs1:/tmp/cvs-serv644/arch/mips/mm

Modified Files:
	tlb-r4k.c 
Log Message:
Quick rm7k bug fix. The rm7k config register uses bit 31 to report
secondary cache. Thus, the cpu is mistaken as a mips32 CPU.


Index: tlb-r4k.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/mm/tlb-r4k.c,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -d -r1.2 -r1.3
--- tlb-r4k.c	2001/10/23 23:51:03	1.2
+++ tlb-r4k.c	2001/11/11 00:10:32	1.3
@@ -337,6 +337,10 @@
 {
 	unsigned long config1;
 
+#ifdef CONFIG_CPU_RM7000
+	return;
+#endif
+
 	if (!(config & (1 << 31)))
 	        /* 
 		 * Not a MIPS32 complianant CPU.  Config 1 register not