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[Linux-mips-commits]CVS: linux/include/asm-mips/jmr3927 ds1742rtc.h,NONE,1.1 irq.h,NONE,1.1 jmr3927.h,NONE,1.1 pci.h,NONE,1.1 tx3927.h,NONE,1.1 txx927.h,NONE,1.1
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From: James S. <jsi...@us...> - 2001-11-10 03:54:11
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Update of /cvsroot/linux-mips/linux/include/asm-mips/jmr3927
In directory usw-pr-cvs1:/tmp/cvs-serv21221
Added Files:
ds1742rtc.h irq.h jmr3927.h pci.h tx3927.h txx927.h
Log Message:
Imported support for JMR-TX3927 by Alice Hennessy. Thank you.
--- NEW FILE: ds1742rtc.h ---
/* $Id: ds1742rtc.h,v 1.1 2001/11/10 03:54:08 jsimmons Exp $
*
* ds1742rtc.h - register definitions for the Real-Time-Clock / CMOS RAM
*
* Based on include/asm-mips/ds1643rtc.h.
*
* Copyright (C) 1999-2001 Toshiba Corporation
* It was written to be part of the Linux operating system.
*/
/* permission is hereby granted to copy, modify and redistribute this code
* in terms of the GNU Library General Public License, Version 2 or later,
* at your option.
*/
#ifndef _DS1742RTC_H
#define _DS1742RTC_H
#include <linux/rtc.h>
#include <asm/mc146818rtc.h> /* bad name... */
#define RTC_BRAM_SIZE 0x800
#define RTC_OFFSET 0x7f8
/**********************************************************************
* register summary
**********************************************************************/
#define RTC_CONTROL (RTC_OFFSET + 0)
#define RTC_CENTURY (RTC_OFFSET + 0)
#define RTC_SECONDS (RTC_OFFSET + 1)
#define RTC_MINUTES (RTC_OFFSET + 2)
#define RTC_HOURS (RTC_OFFSET + 3)
#define RTC_DAY (RTC_OFFSET + 4)
#define RTC_DATE (RTC_OFFSET + 5)
#define RTC_MONTH (RTC_OFFSET + 6)
#define RTC_YEAR (RTC_OFFSET + 7)
#define RTC_CENTURY_MASK 0x3f
#define RTC_SECONDS_MASK 0x7f
#define RTC_DAY_MASK 0x07
/*
* Bits in the Control/Century register
*/
#define RTC_WRITE 0x80
#define RTC_READ 0x40
/*
* Bits in the Seconds register
*/
#define RTC_STOP 0x80
/*
* Bits in the Day register
*/
#define RTC_BATT_FLAG 0x80
#define RTC_FREQ_TEST 0x40
/*
* Conversion between binary and BCD.
*/
#ifndef BCD_TO_BIN
#define BCD_TO_BIN(val) ((val)=((val)&15) + ((val)>>4)*10)
#endif
#ifndef BIN_TO_BCD
#define BIN_TO_BCD(val) ((val)=(((val)/10)<<4) + (val)%10)
#endif
#endif /* _DS1742RTC_H */
--- NEW FILE: irq.h ---
/*
* linux/include/asm-mips/tx3927/irq.h
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2001 Toshiba Corporation
*
* $Id: irq.h,v 1.1 2001/11/10 03:54:08 jsimmons Exp $
*/
#ifndef __ASM_MIPS_TX3927_IRQ_H
#define __ASM_MIPS_TX3927_IRQ_H
#ifndef _LANGUAGE_ASSEMBLY
#include <asm/irq.h>
struct tb_irq_space {
struct tb_irq_space* next;
int start_irqno;
int nr_irqs;
void (*mask_func)(int irq_nr, int space_id);
void (*unmask_func)(int irq_no, int space_id);
const char *name;
int space_id;
int can_share;
};
extern struct tb_irq_space* tb_irq_spaces;
static __inline__ void add_tb_irq_space(struct tb_irq_space* sp)
{
sp->next = tb_irq_spaces;
tb_irq_spaces = sp;
}
struct pt_regs;
extern void
toshibaboards_spurious(struct pt_regs *regs, int irq);
extern void
toshibaboards_irqdispatch(struct pt_regs *regs, int irq);
extern struct irqaction *
toshibaboards_get_irq_action(int irq);
extern int
toshibaboards_setup_irq(int irq, struct irqaction * new);
#ifdef CONFIG_TX_BRANCH_LIKELY_BUG_WORKAROUND
extern void tx_branch_likely_bug_fixup(struct pt_regs *regs);
#endif
extern int (*toshibaboards_gen_iack)(void);
#endif /* _LANGUAGE_ASSEMBLY */
#define NR_ISA_IRQS 16
#define TB_IRQ_IS_ISA(irq) \
(0 <= (irq) && (irq) < NR_ISA_IRQS)
#define TB_IRQ_TO_ISA_IRQ(irq) (irq)
#endif /* __ASM_MIPS_TX3927_IRQ_H */
--- NEW FILE: jmr3927.h ---
/* $Id: jmr3927.h,v 1.1 2001/11/10 03:54:08 jsimmons Exp $
*
* Defines for the TJSYS JMR-TX3927/JMI-3927IO2/JMY-1394IF.
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2000-2001 Toshiba Corporation
*/
#ifndef __ASM_MIPS_TX3927_JMR3927_H
#define __ASM_MIPS_TX3927_JMR3927_H
#include <asm/jmr3927/tx3927.h>
#include <asm/addrspace.h>
#include <asm/jmr3927/irq.h>
#ifndef _LANGUAGE_ASSEMBLY
#include <asm/system.h>
#endif
/* CS */
#define JMR3927_ROMCE0 0x1fc00000 /* 4M */
#define JMR3927_ROMCE1 0x1e000000 /* 4M */
#define JMR3927_ROMCE2 0x14000000 /* 16M */
#define JMR3927_ROMCE3 0x10000000 /* 64M */
#define JMR3927_ROMCE5 0x1d000000 /* 4M */
#define JMR3927_SDCS0 0x00000000 /* 32M */
#define JMR3927_SDCS1 0x02000000 /* 32M */
/* PCI Direct Mappings */
#define JMR3927_PCIMEM 0x08000000
#define JMR3927_PCIMEM_SIZE 0x08000000 /* 128M */
#define JMR3927_PCIIO 0x15000000
#define JMR3927_PCIIO_SIZE 0x01000000 /* 16M */
#define JMR3927_SDRAM_SIZE 0x02000000 /* 32M */
#define JMR3927_PORT_BASE KSEG1
/* select indirect initiator access per errata */
#define JMR3927_INIT_INDIRECT_PCI
#define PCI_ISTAT_IDICC 0x1000
#define PCI_IPCIBE_IBE_LONG 0
#define PCI_IPCIBE_ICMD_IOREAD 2
#define PCI_IPCIBE_ICMD_IOWRITE 3
#define PCI_IPCIBE_ICMD_MEMREAD 6
#define PCI_IPCIBE_ICMD_MEMWRITE 7
#define PCI_IPCIBE_ICMD_SHIFT 4
/* Address map (virtual address) */
#define JMR3927_ROM0_BASE (KSEG1 + JMR3927_ROMCE0)
#define JMR3927_ROM1_BASE (KSEG1 + JMR3927_ROMCE1)
#define JMR3927_IOC_BASE (KSEG1 + JMR3927_ROMCE2)
#define JMR3927_IOB_BASE (KSEG1 + JMR3927_ROMCE3)
#define JMR3927_ISAMEM_BASE (JMR3927_IOB_BASE)
#define JMR3927_ISAIO_BASE (JMR3927_IOB_BASE + 0x01000000)
#define JMR3927_ISAC_BASE (JMR3927_IOB_BASE + 0x02000000)
#define JMR3927_LCDVGA_REG_BASE (JMR3927_IOB_BASE + 0x03000000)
#define JMR3927_LCDVGA_MEM_BASE (JMR3927_IOB_BASE + 0x03800000)
#define JMR3927_JMY1394_BASE (KSEG1 + JMR3927_ROMCE5)
#define JMR3927_PREMIER3_BASE (JMR3927_JMY1394_BASE + 0x00100000)
#define JMR3927_PCIMEM_BASE (KSEG1 + JMR3927_PCIMEM)
#define JMR3927_PCIIO_BASE (KSEG1 + JMR3927_PCIIO)
#define JMR3927_IOC_REV_ADDR (JMR3927_IOC_BASE + 0x00000000)
#define JMR3927_IOC_NVRAMB_ADDR (JMR3927_IOC_BASE + 0x00010000)
#define JMR3927_IOC_LED_ADDR (JMR3927_IOC_BASE + 0x00020000)
#define JMR3927_IOC_DIPSW_ADDR (JMR3927_IOC_BASE + 0x00030000)
#define JMR3927_IOC_BREV_ADDR (JMR3927_IOC_BASE + 0x00040000)
#define JMR3927_IOC_DTR_ADDR (JMR3927_IOC_BASE + 0x00050000)
#define JMR3927_IOC_INTS1_ADDR (JMR3927_IOC_BASE + 0x00080000)
#define JMR3927_IOC_INTS2_ADDR (JMR3927_IOC_BASE + 0x00090000)
#define JMR3927_IOC_INTM_ADDR (JMR3927_IOC_BASE + 0x000a0000)
#define JMR3927_IOC_INTP_ADDR (JMR3927_IOC_BASE + 0x000b0000)
#define JMR3927_IOC_RESET_ADDR (JMR3927_IOC_BASE + 0x000f0000)
#define JMR3927_ISAC_REV_ADDR (JMR3927_ISAC_BASE + 0x00000000)
#define JMR3927_ISAC_EINTS_ADDR (JMR3927_ISAC_BASE + 0x00200000)
#define JMR3927_ISAC_EINTM_ADDR (JMR3927_ISAC_BASE + 0x00300000)
#define JMR3927_ISAC_NMI_ADDR (JMR3927_ISAC_BASE + 0x00400000)
#define JMR3927_ISAC_LED_ADDR (JMR3927_ISAC_BASE + 0x00500000)
#define JMR3927_ISAC_INTP_ADDR (JMR3927_ISAC_BASE + 0x00800000)
#define JMR3927_ISAC_INTS1_ADDR (JMR3927_ISAC_BASE + 0x00900000)
#define JMR3927_ISAC_INTS2_ADDR (JMR3927_ISAC_BASE + 0x00a00000)
#define JMR3927_ISAC_INTM_ADDR (JMR3927_ISAC_BASE + 0x00b00000)
/* Flash ROM */
#define JMR3927_FLASH_BASE (JMR3927_ROM0_BASE)
#define JMR3927_FLASH_SIZE 0x00400000
/* bits for IOC_REV/IOC_BREV/ISAC_REV (high byte) */
#define JMR3927_IDT_MASK 0xfc
#define JMR3927_REV_MASK 0x03
#define JMR3927_IOC_IDT 0xe0
#define JMR3927_ISAC_IDT 0x20
/* bits for IOC_INTS1/IOC_INTS2/IOC_INTM/IOC_INTP (high byte) */
#define JMR3927_IOC_INTB_PCIA 0
#define JMR3927_IOC_INTB_PCIB 1
#define JMR3927_IOC_INTB_PCIC 2
#define JMR3927_IOC_INTB_PCID 3
#define JMR3927_IOC_INTB_MODEM 4
#define JMR3927_IOC_INTB_INT6 5
#define JMR3927_IOC_INTB_INT7 6
#define JMR3927_IOC_INTB_SOFT 7
#define JMR3927_IOC_INTF_PCIA (1 << JMR3927_IOC_INTF_PCIA)
#define JMR3927_IOC_INTF_PCIB (1 << JMR3927_IOC_INTB_PCIB)
#define JMR3927_IOC_INTF_PCIC (1 << JMR3927_IOC_INTB_PCIC)
#define JMR3927_IOC_INTF_PCID (1 << JMR3927_IOC_INTB_PCID)
#define JMR3927_IOC_INTF_MODEM (1 << JMR3927_IOC_INTB_MODEM)
#define JMR3927_IOC_INTF_INT6 (1 << JMR3927_IOC_INTB_INT6)
#define JMR3927_IOC_INTF_INT7 (1 << JMR3927_IOC_INTB_INT7)
#define JMR3927_IOC_INTF_SOFT (1 << JMR3927_IOC_INTB_SOFT)
/* bits for IOC_RESET (high byte) */
#define JMR3927_IOC_RESET_CPU 1
#define JMR3927_IOC_RESET_PCI 2
/* bits for ISAC_EINTS/ISAC_EINTM (high byte) */
#define JMR3927_ISAC_EINTB_IOCHK 2
#define JMR3927_ISAC_EINTB_BWTH 4
#define JMR3927_ISAC_EINTF_IOCHK (1 << JMR3927_ISAC_EINTB_IOCHK)
#define JMR3927_ISAC_EINTF_BWTH (1 << JMR3927_ISAC_EINTB_BWTH)
/* bits for ISAC_LED (high byte) */
#define JMR3927_ISAC_LED_ISALED 0x01
#define JMR3927_ISAC_LED_USRLED 0x02
/* bits for ISAC_INTS/ISAC_INTM/ISAC_INTP (high byte) */
#define JMR3927_ISAC_INTB_IRQ5 0
#define JMR3927_ISAC_INTB_IRQKB 1
#define JMR3927_ISAC_INTB_IRQMOUSE 2
#define JMR3927_ISAC_INTB_IRQ4 3
#define JMR3927_ISAC_INTB_IRQ12 4
#define JMR3927_ISAC_INTB_IRQ3 5
#define JMR3927_ISAC_INTB_IRQ10 6
#define JMR3927_ISAC_INTB_ISAER 7
#define JMR3927_ISAC_INTF_IRQ5 (1 << JMR3927_ISAC_INTB_IRQ5)
#define JMR3927_ISAC_INTF_IRQKB (1 << JMR3927_ISAC_INTB_IRQKB)
#define JMR3927_ISAC_INTF_IRQMOUSE (1 << JMR3927_ISAC_INTB_IRQMOUSE)
#define JMR3927_ISAC_INTF_IRQ4 (1 << JMR3927_ISAC_INTB_IRQ4)
#define JMR3927_ISAC_INTF_IRQ12 (1 << JMR3927_ISAC_INTB_IRQ12)
#define JMR3927_ISAC_INTF_IRQ3 (1 << JMR3927_ISAC_INTB_IRQ3)
#define JMR3927_ISAC_INTF_IRQ10 (1 << JMR3927_ISAC_INTB_IRQ10)
#define JMR3927_ISAC_INTF_ISAER (1 << JMR3927_ISAC_INTB_ISAER)
#ifndef _LANGUAGE_ASSEMBLY
#if 0
#define jmr3927_ioc_reg_out(d, a) ((*(volatile unsigned short *)(a)) = (d) << 8)
#define jmr3927_ioc_reg_in(a) (((*(volatile unsigned short *)(a)) >> 8) & 0xff)
#else
#if defined(__BIG_ENDIAN)
#define jmr3927_ioc_reg_out(d, a) ((*(volatile unsigned char *)(a)) = (d))
#define jmr3927_ioc_reg_in(a) (*(volatile unsigned char *)(a))
#elif defined(__LITTLE_ENDIAN)
#define jmr3927_ioc_reg_out(d, a) ((*(volatile unsigned char *)((a)^1)) = (d))
#define jmr3927_ioc_reg_in(a) (*(volatile unsigned char *)((a)^1))
#else
#error "No Endian"
#endif
#endif
#define jmr3927_isac_reg_out(d, a) ((*(volatile unsigned char *)(a)) = (d))
#define jmr3927_isac_reg_in(a) (*(volatile unsigned char *)(a))
extern inline int jmr3927_have_isac(void)
{
unsigned char idt;
unsigned long flags;
unsigned long romcr3;
save_and_cli(flags);
romcr3 = tx3927_romcptr->cr[3];
tx3927_romcptr->cr[3] &= 0xffffefff; /* do not wait infinitely */
idt = jmr3927_isac_reg_in(JMR3927_ISAC_REV_ADDR) & JMR3927_IDT_MASK;
tx3927_romcptr->cr[3] = romcr3;
restore_flags(flags);
return idt == JMR3927_ISAC_IDT;
}
#define jmr3927_have_nvram() \
((jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR) & JMR3927_IDT_MASK) == JMR3927_IOC_IDT)
/* NVRAM macro */
#define jmr3927_nvram_in(ofs) \
jmr3927_ioc_reg_in(JMR3927_IOC_NVRAMB_ADDR + ((ofs) << 1))
#define jmr3927_nvram_out(d, ofs) \
jmr3927_ioc_reg_out(d, JMR3927_IOC_NVRAMB_ADDR + ((ofs) << 1))
/* LED macro */
#define jmr3927_led_set(n/*0-16*/) jmr3927_ioc_reg_out(~(n), JMR3927_IOC_LED_ADDR)
#define jmr3927_io_led_set(n/*0-3*/) jmr3927_isac_reg_out((n), JMR3927_ISAC_LED_ADDR)
#define jmr3927_led_and_set(n/*0-16*/) jmr3927_ioc_reg_out((~(n)) & jmr3927_ioc_reg_in(JMR3927_IOC_LED_ADDR), JMR3927_IOC_LED_ADDR)
/* DIPSW4 macro */
#define jmr3927_dipsw1() ((tx3927_pioptr->din & (1 << 11)) == 0)
#define jmr3927_dipsw2() ((tx3927_pioptr->din & (1 << 10)) == 0)
#define jmr3927_dipsw3() ((jmr3927_ioc_reg_in(JMR3927_IOC_DIPSW_ADDR) & 2) == 0)
#define jmr3927_dipsw4() ((jmr3927_ioc_reg_in(JMR3927_IOC_DIPSW_ADDR) & 1) == 0)
#define jmr3927_io_dipsw() (jmr3927_isac_reg_in(JMR3927_ISAC_LED_ADDR) >> 4)
#endif /* _LANGUAGE_ASSEMBLY */
/*
* UART defines for serial.h
*/
/* use Pre-scaler T0 (1/2) */
#define JMR3927_BASE_BAUD (JMR3927_IMCLK / 2 / 16)
#define UART0_ADDR 0xfffef300
#define UART1_ADDR 0xfffef400
#define UART0_INT JMR3927_IRQ_IRC_SIO0
#define UART1_INT JMR3927_IRQ_IRC_SIO1
#define UART0_FLAGS ASYNC_BOOT_AUTOCONF
#define UART1_FLAGS 0
/*
* IRQ mappings
*/
/* These are the virtual IRQ numbers, we divide all IRQ's into
* 'spaces', the 'space' determines where and how to enable/disable
* that particular IRQ on an JMR machine. Add new 'spaces' as new
* IRQ hardware is supported.
*/
#define JMR3927_NR_IRQ_IRC 16 /* On-Chip IRC */
#define JMR3927_NR_IRQ_IOC 8 /* PCI/MODEM/INT[6:7] */
#define JMR3927_NR_IRQ_ISAC 8 /* ISA */
#define JMR3927_IRQ_IRC NR_ISA_IRQS
#define JMR3927_IRQ_IOC (JMR3927_IRQ_IRC + JMR3927_NR_IRQ_IRC)
#define JMR3927_IRQ_ISAC (JMR3927_IRQ_IOC + JMR3927_NR_IRQ_IOC)
#define JMR3927_IRQ_END (JMR3927_IRQ_ISAC + JMR3927_NR_IRQ_ISAC)
#define JMR3927_IRQ_IS_IRC(irq) (JMR3927_IRQ_IRC <= (irq) && (irq) < JMR3927_IRQ_IOC)
#define JMR3927_IRQ_IS_IOC(irq) (JMR3927_IRQ_IOC <= (irq) && (irq) < JMR3927_IRQ_ISAC)
#define JMR3927_IRQ_IS_ISAC(irq) (JMR3927_IRQ_ISAC <= (irq) && (irq) < JMR3927_IRQ_END)
#define JMR3927_IRQ_IRC_INT0 (JMR3927_IRQ_IRC + TX3927_IR_INT0)
#define JMR3927_IRQ_IRC_INT1 (JMR3927_IRQ_IRC + TX3927_IR_INT1)
#define JMR3927_IRQ_IRC_INT2 (JMR3927_IRQ_IRC + TX3927_IR_INT2)
#define JMR3927_IRQ_IRC_INT3 (JMR3927_IRQ_IRC + TX3927_IR_INT3)
#define JMR3927_IRQ_IRC_INT4 (JMR3927_IRQ_IRC + TX3927_IR_INT4)
#define JMR3927_IRQ_IRC_INT5 (JMR3927_IRQ_IRC + TX3927_IR_INT5)
#define JMR3927_IRQ_IRC_SIO0 (JMR3927_IRQ_IRC + TX3927_IR_SIO0)
#define JMR3927_IRQ_IRC_SIO1 (JMR3927_IRQ_IRC + TX3927_IR_SIO1)
#define JMR3927_IRQ_IRC_SIO(ch) (JMR3927_IRQ_IRC + TX3927_IR_SIO(ch))
#define JMR3927_IRQ_IRC_DMA (JMR3927_IRQ_IRC + TX3927_IR_DMA)
#define JMR3927_IRQ_IRC_PIO (JMR3927_IRQ_IRC + TX3927_IR_PIO)
#define JMR3927_IRQ_IRC_PCI (JMR3927_IRQ_IRC + TX3927_IR_PCI)
#define JMR3927_IRQ_IRC_TMR0 (JMR3927_IRQ_IRC + TX3927_IR_TMR0)
#define JMR3927_IRQ_IRC_TMR1 (JMR3927_IRQ_IRC + TX3927_IR_TMR1)
#define JMR3927_IRQ_IRC_TMR2 (JMR3927_IRQ_IRC + TX3927_IR_TMR2)
#define JMR3927_IRQ_IOC_PCIA (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIA)
#define JMR3927_IRQ_IOC_PCIB (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIB)
#define JMR3927_IRQ_IOC_PCIC (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIC)
#define JMR3927_IRQ_IOC_PCID (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCID)
#define JMR3927_IRQ_IOC_MODEM (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_MODEM)
#define JMR3927_IRQ_IOC_INT6 (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_INT6)
#define JMR3927_IRQ_IOC_INT7 (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_INT7)
#define JMR3927_IRQ_IOC_SOFT (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_SOFT)
#define JMR3927_IRQ_ISAC_IRQ5 (JMR3927_IRQ_ISAC + JMR3927_ISAC_INTB_IRQ5)
#define JMR3927_IRQ_ISAC_IRQKB (JMR3927_IRQ_ISAC + JMR3927_ISAC_INTB_IRQKB)
#define JMR3927_IRQ_ISAC_IRQMOUSE (JMR3927_IRQ_ISAC + JMR3927_ISAC_INTB_IRQMOUSE)
#define JMR3927_IRQ_ISAC_IRQ4 (JMR3927_IRQ_ISAC + JMR3927_ISAC_INTB_IRQ4)
#define JMR3927_IRQ_ISAC_IRQ12 (JMR3927_IRQ_ISAC + JMR3927_ISAC_INTB_IRQ12)
#define JMR3927_IRQ_ISAC_IRQ3 (JMR3927_IRQ_ISAC + JMR3927_ISAC_INTB_IRQ3)
#define JMR3927_IRQ_ISAC_IRQ10 (JMR3927_IRQ_ISAC + JMR3927_ISAC_INTB_IRQ10)
#define JMR3927_IRQ_ISAC_ISAER (JMR3927_IRQ_ISAC + JMR3927_ISAC_INTB_ISAER)
#if 0 /* auto detect */
/* RTL8019AS 10M Ether (JMI-3927IO2:JPW2:1-2 Short) */
#define JMR3927_IRQ_ETHER1 JMR3927_IRQ_IRC_INT0
#endif
/* IOC (PCI, MODEM) */
#define JMR3927_IRQ_IOCINT JMR3927_IRQ_IRC_INT1
/* ISAC (ISA, PCMCIA, KEYBOARD, MOUSE) */
#define JMR3927_IRQ_ISACINT JMR3927_IRQ_IRC_INT2
/* TC35815 100M Ether (JMR-TX3912:JPW4:2-3 Short) */
#define JMR3927_IRQ_ETHER0 JMR3927_IRQ_IRC_INT3
/* Clock Tick (10ms) */
#define JMR3927_IRQ_TICK JMR3927_IRQ_IRC_TMR0
#define JMR3927_IRQ_IDE JMR3927_IRQ_ISAC_IRQ12
/* IEEE1394 (Note that this may conflicts with RTL8019AS 10M Ether...) */
#define JMR3927_IRQ_PREMIER3 JMR3927_IRQ_IRC_INT0
/* I/O Ports */
/* RTL8019AS 10M Ether */
#define JMR3927_ETHER1_PORT (JMR3927_ISAIO_BASE - JMR3927_PORT_BASE + 0x280)
#define JMR3927_KBD_PORT (JMR3927_ISAIO_BASE - JMR3927_PORT_BASE + 0x00800060)
#define JMR3927_IDE_PORT (JMR3927_ISAIO_BASE - JMR3927_PORT_BASE + 0x001001f0)
/* Clocks */
#define JMR3927_CORECLK 132710400 /* 132.7MHz */
#define JMR3927_GBUSCLK (JMR3927_CORECLK / 2) /* 66.35MHz */
#define JMR3927_IMCLK (JMR3927_CORECLK / 4) /* 33.17MHz */
#define jmr3927_tmrptr tx3927_tmrptr(0) /* TMR0 */
/*
* TX3927 Pin Configuration:
*
* PCFG bits Avail Dead
* SELSIO[1:0]:11 RXD[1:0], TXD[1:0] PIO[6:3]
* SELSIOC[0]:1 CTS[0], RTS[0] INT[5:4]
* SELSIOC[1]:0,SELDSF:0, GSDAO[0],GPCST[3] CTS[1], RTS[1],DSF,
* GDBGE* PIO[2:1]
* SELDMA[2]:1 DMAREQ[2],DMAACK[2] PIO[13:12]
* SELTMR[2:0]:000 TIMER[1:0]
* SELCS:0,SELDMA[1]:0 PIO[11;10] SDCS_CE[7:6],
* DMAREQ[1],DMAACK[1]
* SELDMA[0]:1 DMAREQ[0],DMAACK[0] PIO[9:8]
* SELDMA[3]:1 DMAREQ[3],DMAACK[3] PIO[15:14]
* SELDONE:1 DMADONE PIO[7]
*
* Usable pins are:
* RXD[1;0],TXD[1:0],CTS[0],RTS[0],
* DMAREQ[0,2,3],DMAACK[0,2,3],DMADONE,PIO[0,10,11]
* INT[3:0]
*/
#endif /* __ASM_MIPS_TX3927_JMR3927_H */
--- NEW FILE: pci.h ---
/***********************************************************************
*
* Copyright 2001 MontaVista Software Inc.
* Author: MontaVista Software, Inc.
* ahe...@mv...
*
* include/asm-mips/jmr3927/pci.h
* Based on include/asm-mips/ddb5xxx/pci.h
*
* This file essentially defines the interface between board
* specific PCI code and MIPS common PCI code. Should potentially put
* into include/asm/pci.h file.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*
***********************************************************************
*/
#ifndef __ASM_TX3927_PCI_H
#define __ASM_TX3927__PCI_H
#include <linux/ioport.h>
#include <linux/pci.h>
/*
* Each pci channel is a top-level PCI bus seem by CPU. A machine with
* multiple PCI channels may have multiple PCI host controllers or a
* single controller supporting multiple channels.
*/
struct pci_channel {
struct pci_ops *pci_ops;
struct resource *io_resource;
struct resource *mem_resource;
};
/*
* each board defines an array of pci_channels, that ends with all NULL entry
*/
extern struct pci_channel mips_pci_channels[];
/*
* board supplied pci irq fixup routine
*/
extern void pcibios_fixup_irqs(void);
#endif /* __ASM_TX3927_PCI_H */
--- NEW FILE: tx3927.h ---
/* $Id: tx3927.h,v 1.1 2001/11/10 03:54:08 jsimmons Exp $
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2000 Toshiba Corporation
*/
#ifndef __ASM_MIPS_TX3927_H
#define __ASM_MIPS_TX3927_H
#include <asm/jmr3927/txx927.h>
#define TX3927_SDRAMC_REG 0xfffe8000
#define TX3927_ROMC_REG 0xfffe9000
#define TX3927_DMA_REG 0xfffeb000
#define TX3927_IRC_REG 0xfffec000
#define TX3927_PCIC_REG 0xfffed000
#define TX3927_CCFG_REG 0xfffee000
#define TX3927_NR_TMR 3
#define TX3927_TMR_REG(ch) (0xfffef000 + (ch) * 0x100)
#define TX3927_NR_SIO 2
#define TX3927_SIO_REG(ch) (0xfffef300 + (ch) * 0x100)
#define TX3927_PIO_REG 0xfffef500
#ifndef _LANGUAGE_ASSEMBLY
struct tx3927_sdramc_reg {
volatile unsigned long cr[8];
volatile unsigned long tr[3];
volatile unsigned long cmd;
volatile unsigned long smrs[2];
};
struct tx3927_romc_reg {
volatile unsigned long cr[8];
};
struct tx3927_dma_reg {
struct tx3927_dma_ch_reg {
volatile unsigned long cha;
volatile unsigned long sar;
volatile unsigned long dar;
volatile unsigned long cntr;
volatile unsigned long sair;
volatile unsigned long dair;
volatile unsigned long ccr;
volatile unsigned long csr;
} ch[4];
volatile unsigned long dbr[8];
volatile unsigned long tdhr;
volatile unsigned long mcr;
volatile unsigned long unused0;
};
struct tx3927_irc_reg {
volatile unsigned long cer;
volatile unsigned long cr[2];
volatile unsigned long unused0;
volatile unsigned long ilr[8];
volatile unsigned long unused1[4];
volatile unsigned long imr;
volatile unsigned long unused2[7];
volatile unsigned long scr;
volatile unsigned long unused3[7];
volatile unsigned long ssr;
volatile unsigned long unused4[7];
volatile unsigned long csr;
};
#include <asm/byteorder.h>
#ifdef __BIG_ENDIAN
#define endian_def_s2(e1,e2) \
volatile unsigned short e1,e2
#define endian_def_sb2(e1,e2,e3) \
volatile unsigned short e1;volatile unsigned char e2,e3
#define endian_def_b2s(e1,e2,e3) \
volatile unsigned char e1,e2;volatile unsigned short e3
#define endian_def_b4(e1,e2,e3,e4) \
volatile unsigned char e1,e2,e3,e4
#else
#define endian_def_s2(e1,e2) \
volatile unsigned short e2,e1
#define endian_def_sb2(e1,e2,e3) \
volatile unsigned char e3,e2;volatile unsigned short e1
#define endian_def_b2s(e1,e2,e3) \
volatile unsigned short e3;volatile unsigned char e2,e1
#define endian_def_b4(e1,e2,e3,e4) \
volatile unsigned char e4,e3,e2,e1
#endif
struct tx3927_pcic_reg {
endian_def_s2(did, vid);
endian_def_s2(pcistat, pcicmd);
endian_def_b4(cc, scc, rpli, rid);
endian_def_b4(unused0, ht, mlt, cls);
volatile unsigned long ioba; /* +10 */
volatile unsigned long mba;
volatile unsigned long unused1[5];
endian_def_s2(svid, ssvid);
volatile unsigned long unused2; /* +30 */
endian_def_sb2(unused3, unused4, capptr);
volatile unsigned long unused5;
endian_def_b4(ml, mg, ip, il);
volatile unsigned long unused6; /* +40 */
volatile unsigned long istat;
volatile unsigned long iim;
volatile unsigned long rrt;
volatile unsigned long unused7[3]; /* +50 */
volatile unsigned long ipbmma;
volatile unsigned long ipbioma; /* +60 */
volatile unsigned long ilbmma;
volatile unsigned long ilbioma;
volatile unsigned long unused8[9];
volatile unsigned long tc; /* +90 */
volatile unsigned long tstat;
volatile unsigned long tim;
volatile unsigned long tccmd;
volatile unsigned long pcirrt; /* +a0 */
volatile unsigned long pcirrt_cmd;
volatile unsigned long pcirrdt;
volatile unsigned long unused9[3];
volatile unsigned long tlboap;
volatile unsigned long tlbiap;
volatile unsigned long tlbmma; /* +c0 */
volatile unsigned long tlbioma;
volatile unsigned long sc_msg;
volatile unsigned long sc_be;
volatile unsigned long tbl; /* +d0 */
volatile unsigned long unused10[3];
volatile unsigned long pwmng; /* +e0 */
volatile unsigned long pwmngs;
volatile unsigned long unused11[6];
volatile unsigned long req_trace; /* +100 */
volatile unsigned long pbapmc;
volatile unsigned long pbapms;
volatile unsigned long pbapmim;
volatile unsigned long bm; /* +110 */
volatile unsigned long cpcibrs;
volatile unsigned long cpcibgs;
volatile unsigned long pbacs;
volatile unsigned long iobas; /* +120 */
volatile unsigned long mbas;
volatile unsigned long lbc;
volatile unsigned long lbstat;
volatile unsigned long lbim; /* +130 */
volatile unsigned long pcistatim;
volatile unsigned long ica;
volatile unsigned long icd;
volatile unsigned long iiadp; /* +140 */
volatile unsigned long iscdp;
volatile unsigned long mmas;
volatile unsigned long iomas;
volatile unsigned long ipciaddr; /* +150 */
volatile unsigned long ipcidata;
volatile unsigned long ipcibe;
};
struct tx3927_ccfg_reg {
volatile unsigned long ccfg;
volatile unsigned long crir;
volatile unsigned long pcfg;
volatile unsigned long tear;
volatile unsigned long pdcr;
};
#endif /* _LANGUAGE_ASSEMBLY */
/*
* SDRAMC
*/
/*
* ROMC
*/
/*
* DMA
*/
/* bits for MCR */
#define TX3927_DMA_MCR_EIS(ch) (0x10000000<<(ch))
#define TX3927_DMA_MCR_DIS(ch) (0x01000000<<(ch))
#define TX3927_DMA_MCR_RSFIF 0x00000080
#define TX3927_DMA_MCR_FIFUM(ch) (0x00000008<<(ch))
#define TX3927_DMA_MCR_LE 0x00000004
#define TX3927_DMA_MCR_RPRT 0x00000002
#define TX3927_DMA_MCR_MSTEN 0x00000001
/* bits for CCRn */
#define TX3927_DMA_CCR_DBINH 0x04000000
#define TX3927_DMA_CCR_SBINH 0x02000000
#define TX3927_DMA_CCR_CHRST 0x01000000
#define TX3927_DMA_CCR_RVBYTE 0x00800000
#define TX3927_DMA_CCR_ACKPOL 0x00400000
#define TX3927_DMA_CCR_REQPL 0x00200000
#define TX3927_DMA_CCR_EGREQ 0x00100000
#define TX3927_DMA_CCR_CHDN 0x00080000
#define TX3927_DMA_CCR_DNCTL 0x00060000
#define TX3927_DMA_CCR_EXTRQ 0x00010000
#define TX3927_DMA_CCR_INTRQD 0x0000e000
#define TX3927_DMA_CCR_INTENE 0x00001000
#define TX3927_DMA_CCR_INTENC 0x00000800
#define TX3927_DMA_CCR_INTENT 0x00000400
#define TX3927_DMA_CCR_CHNEN 0x00000200
#define TX3927_DMA_CCR_XFACT 0x00000100
#define TX3927_DMA_CCR_SNOP 0x00000080
#define TX3927_DMA_CCR_DSTINC 0x00000040
#define TX3927_DMA_CCR_SRCINC 0x00000020
#define TX3927_DMA_CCR_XFSZ(order) (((order) << 2) & 0x0000001c)
#define TX3927_DMA_CCR_XFSZ_1W TX3927_DMA_CCR_XFSZ(2)
#define TX3927_DMA_CCR_XFSZ_4W TX3927_DMA_CCR_XFSZ(4)
#define TX3927_DMA_CCR_XFSZ_8W TX3927_DMA_CCR_XFSZ(5)
#define TX3927_DMA_CCR_XFSZ_16W TX3927_DMA_CCR_XFSZ(6)
#define TX3927_DMA_CCR_XFSZ_32W TX3927_DMA_CCR_XFSZ(7)
#define TX3927_DMA_CCR_MEMIO 0x00000002
#define TX3927_DMA_CCR_ONEAD 0x00000001
/* bits for CSRn */
#define TX3927_DMA_CSR_CHNACT 0x00000100
#define TX3927_DMA_CSR_ABCHC 0x00000080
#define TX3927_DMA_CSR_NCHNC 0x00000040
#define TX3927_DMA_CSR_NTRNFC 0x00000020
#define TX3927_DMA_CSR_EXTDN 0x00000010
#define TX3927_DMA_CSR_CFERR 0x00000008
#define TX3927_DMA_CSR_CHERR 0x00000004
#define TX3927_DMA_CSR_DESERR 0x00000002
#define TX3927_DMA_CSR_SORERR 0x00000001
/*
* IRC
*/
#define TX3927_IR_MAX_LEVEL 7
/* IRCER : Int. Control Enable */
#define TX3927_IRCER_ICE 0x00000001
/* IRCR : Int. Control */
#define TX3927_IRCR_LOW 0x00000000
#define TX3927_IRCR_HIGH 0x00000001
#define TX3927_IRCR_DOWN 0x00000002
#define TX3927_IRCR_UP 0x00000003
/* IRSCR : Int. Status Control */
#define TX3927_IRSCR_EIClrE 0x00000100
#define TX3927_IRSCR_EIClr_MASK 0x0000000f
/* IRCSR : Int. Current Status */
#define TX3927_IRCSR_IF 0x00010000
#define TX3927_IRCSR_ILV_MASK 0x00000700
#define TX3927_IRCSR_IVL_MASK 0x0000001f
#define TX3927_IR_INT0 0
#define TX3927_IR_INT1 1
#define TX3927_IR_INT2 2
#define TX3927_IR_INT3 3
#define TX3927_IR_INT4 4
#define TX3927_IR_INT5 5
#define TX3927_IR_SIO0 6
#define TX3927_IR_SIO1 7
#define TX3927_IR_SIO(ch) (6 + (ch))
#define TX3927_IR_DMA 8
#define TX3927_IR_PIO 9
#define TX3927_IR_PCI 10
#define TX3927_IR_TMR0 13
#define TX3927_IR_TMR1 14
#define TX3927_IR_TMR2 15
#define TX3927_NUM_IR 16
/*
* PCIC
*/
/* bits for PCICMD */
/* see PCI_COMMAND_XXX in linux/pci.h */
/* bits for PCISTAT */
/* see PCI_STATUS_XXX in linux/pci.h */
#define PCI_STATUS_NEW_CAP 0x0010
/* bits for TC */
#define TX3927_PCIC_TC_OF16E 0x00000020
#define TX3927_PCIC_TC_IF8E 0x00000010
#define TX3927_PCIC_TC_OF8E 0x00000008
/* bits for IOBA/MBA */
/* see PCI_BASE_ADDRESS_XXX in linux/pci.h */
/* bits for PBAPMC */
#define TX3927_PCIC_PBAPMC_RPBA 0x00000004
#define TX3927_PCIC_PBAPMC_PBAEN 0x00000002
#define TX3927_PCIC_PBAPMC_BMCEN 0x00000001
/* bits for LBSTAT/LBIM */
#define TX3927_PCIC_LBIM_ALL 0x0000003e
/* bits for PCISTATIM (see also PCI_STATUS_XXX in linux/pci.h */
#define TX3927_PCIC_PCISTATIM_ALL 0x0000f900
/* bits for LBC */
#define TX3927_PCIC_LBC_IBSE 0x00004000
#define TX3927_PCIC_LBC_TIBSE 0x00002000
#define TX3927_PCIC_LBC_TMFBSE 0x00001000
#define TX3927_PCIC_LBC_HRST 0x00000800
#define TX3927_PCIC_LBC_SRST 0x00000400
#define TX3927_PCIC_LBC_EPCAD 0x00000200
#define TX3927_PCIC_LBC_MSDSE 0x00000100
#define TX3927_PCIC_LBC_CRR 0x00000080
#define TX3927_PCIC_LBC_ILMDE 0x00000040
#define TX3927_PCIC_LBC_ILIDE 0x00000020
#define TX3927_PCIC_IDSEL_AD_TO_SLOT(ad) ((ad) - 11)
#define TX3927_PCIC_MAX_DEVNU TX3927_PCIC_IDSEL_AD_TO_SLOT(32)
/*
* CCFG
*/
/* CCFG : Chip Configuration */
#define TX3927_CCFG_TLBOFF 0x00020000
#define TX3927_CCFG_BEOW 0x00010000
#define TX3927_CCFG_WR 0x00008000
#define TX3927_CCFG_TOE 0x00004000
#define TX3927_CCFG_PCIXARB 0x00002000
#define TX3927_CCFG_PCI3 0x00001000
#define TX3927_CCFG_PSNP 0x00000800
#define TX3927_CCFG_PPRI 0x00000400
#define TX3927_CCFG_PLLM 0x00000030
#define TX3927_CCFG_ENDIAN 0x00000004
#define TX3927_CCFG_HALT 0x00000002
#define TX3927_CCFG_ACEHOLD 0x00000001
/* PCFG : Pin Configuration */
#define TX3927_PCFG_SYSCLKEN 0x08000000
#define TX3927_PCFG_SDRCLKEN_ALL 0x07c00000
#define TX3927_PCFG_SDRCLKEN(ch) (0x00400000<<(ch))
#define TX3927_PCFG_PCICLKEN_ALL 0x003c0000
#define TX3927_PCFG_PCICLKEN(ch) (0x00040000<<(ch))
#define TX3927_PCFG_SELALL 0x0003ffff
#define TX3927_PCFG_SELCS 0x00020000
#define TX3927_PCFG_SELDSF 0x00010000
#define TX3927_PCFG_SELSIOC_ALL 0x0000c000
#define TX3927_PCFG_SELSIOC(ch) (0x00004000<<(ch))
#define TX3927_PCFG_SELSIO_ALL 0x00003000
#define TX3927_PCFG_SELSIO(ch) (0x00001000<<(ch))
#define TX3927_PCFG_SELTMR_ALL 0x00000e00
#define TX3927_PCFG_SELTMR(ch) (0x00000200<<(ch))
#define TX3927_PCFG_SELDONE 0x00000100
#define TX3927_PCFG_INTDMA_ALL 0x000000f0
#define TX3927_PCFG_INTDMA(ch) (0x00000010<<(ch))
#define TX3927_PCFG_SELDMA_ALL 0x0000000f
#define TX3927_PCFG_SELDMA(ch) (0x00000001<<(ch))
#ifndef _LANGUAGE_ASSEMBLY
#define tx3927_sdramcptr ((struct tx3927_sdramc_reg *)TX3927_SDRAMC_REG)
#define tx3927_romcptr ((struct tx3927_romc_reg *)TX3927_ROMC_REG)
#define tx3927_dmaptr ((struct tx3927_dma_reg *)TX3927_DMA_REG)
#define tx3927_ircptr ((struct tx3927_irc_reg *)TX3927_IRC_REG)
#define tx3927_pcicptr ((struct tx3927_pcic_reg *)TX3927_PCIC_REG)
#define tx3927_ccfgptr ((struct tx3927_ccfg_reg *)TX3927_CCFG_REG)
#define tx3927_tmrptr(ch) ((struct txx927_tmr_reg *)TX3927_TMR_REG(ch))
#define tx3927_sioptr(ch) ((struct txx927_sio_reg *)TX3927_SIO_REG(ch))
#define tx3927_pioptr ((struct txx927_pio_reg *)TX3927_PIO_REG)
#endif /* _LANGUAGE_ASSEMBLY */
#endif /* __ASM_MIPS_TX3927_H */
--- NEW FILE: txx927.h ---
/* $Id: txx927.h,v 1.1 2001/11/10 03:54:08 jsimmons Exp $
* Common difinitins for TX3927/TX4927
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2000 Toshiba Corporation
*/
#ifndef __ASM_MIPS_TXX927_H
#define __ASM_MIPS_TXX927_H
#ifndef _LANGUAGE_ASSEMBLY
struct txx927_tmr_reg {
volatile unsigned long tcr;
volatile unsigned long tisr;
volatile unsigned long cpra;
volatile unsigned long cprb;
volatile unsigned long itmr;
volatile unsigned long unused0[3];
volatile unsigned long ccdr;
volatile unsigned long unused1[3];
volatile unsigned long pgmr;
volatile unsigned long unused2[3];
volatile unsigned long wtmr;
volatile unsigned long unused3[43];
volatile unsigned long trr;
};
struct txx927_sio_reg {
volatile unsigned long lcr;
volatile unsigned long dicr;
volatile unsigned long disr;
volatile unsigned long cisr;
volatile unsigned long fcr;
volatile unsigned long flcr;
volatile unsigned long bgr;
volatile unsigned long tfifo;
volatile unsigned long rfifo;
};
struct txx927_pio_reg {
volatile unsigned long dout;
volatile unsigned long din;
volatile unsigned long dir;
volatile unsigned long od;
volatile unsigned long flag[2];
volatile unsigned long pol;
volatile unsigned long intc;
volatile unsigned long maskcpu;
volatile unsigned long maskext;
};
#endif /* _LANGUAGE_ASSEMBLY */
/*
* TMR
*/
/* TMTCR : Timer Control */
#define TXx927_TMTCR_TCE 0x00000080
#define TXx927_TMTCR_CCDE 0x00000040
#define TXx927_TMTCR_CRE 0x00000020
#define TXx927_TMTCR_ECES 0x00000008
#define TXx927_TMTCR_CCS 0x00000004
#define TXx927_TMTCR_TMODE_MASK 0x00000003
#define TXx927_TMTCR_TMODE_ITVL 0x00000000
/* TMTISR : Timer Int. Status */
#define TXx927_TMTISR_TPIBS 0x00000004
#define TXx927_TMTISR_TPIAS 0x00000002
#define TXx927_TMTISR_TIIS 0x00000001
/* TMTITMR : Interval Timer Mode */
#define TXx927_TMTITMR_TIIE 0x00008000
#define TXx927_TMTITMR_TZCE 0x00000001
/*
* SIO
*/
/* SILCR : Line Control */
#define TXx927_SILCR_SCS_MASK 0x00000060
#define TXx927_SILCR_SCS_IMCLK 0x00000000
#define TXx927_SILCR_SCS_IMCLK_BG 0x00000020
#define TXx927_SILCR_SCS_SCLK 0x00000040
#define TXx927_SILCR_SCS_SCLK_BG 0x00000060
#define TXx927_SILCR_UEPS 0x00000010
#define TXx927_SILCR_UPEN 0x00000008
#define TXx927_SILCR_USBL_MASK 0x00000004
#define TXx927_SILCR_USBL_1BIT 0x00000004
#define TXx927_SILCR_USBL_2BIT 0x00000000
#define TXx927_SILCR_UMODE_MASK 0x00000003
#define TXx927_SILCR_UMODE_8BIT 0x00000000
#define TXx927_SILCR_UMODE_7BIT 0x00000001
/* SIDICR : DMA/Int. Control */
#define TXx927_SIDICR_TDE 0x00008000
#define TXx927_SIDICR_RDE 0x00004000
#define TXx927_SIDICR_TIE 0x00002000
#define TXx927_SIDICR_RIE 0x00001000
#define TXx927_SIDICR_SPIE 0x00000800
#define TXx927_SIDICR_CTSAC 0x00000600
#define TXx927_SIDICR_STIE_MASK 0x0000003f
#define TXx927_SIDICR_STIE_OERS 0x00000020
#define TXx927_SIDICR_STIE_CTSS 0x00000010
#define TXx927_SIDICR_STIE_RBRKD 0x00000008
#define TXx927_SIDICR_STIE_TRDY 0x00000004
#define TXx927_SIDICR_STIE_TXALS 0x00000002
#define TXx927_SIDICR_STIE_UBRKD 0x00000001
/* SIDISR : DMA/Int. Status */
#define TXx927_SIDISR_UBRK 0x00008000
#define TXx927_SIDISR_UVALID 0x00004000
#define TXx927_SIDISR_UFER 0x00002000
#define TXx927_SIDISR_UPER 0x00001000
#define TXx927_SIDISR_UOER 0x00000800
#define TXx927_SIDISR_ERI 0x00000400
#define TXx927_SIDISR_TOUT 0x00000200
#define TXx927_SIDISR_TDIS 0x00000100
#define TXx927_SIDISR_RDIS 0x00000080
#define TXx927_SIDISR_STIS 0x00000040
#define TXx927_SIDISR_RFDN_MASK 0x0000001f
/* SICISR : Change Int. Status */
#define TXx927_SICISR_OERS 0x00000020
#define TXx927_SICISR_CTSS 0x00000010
#define TXx927_SICISR_RBRKD 0x00000008
#define TXx927_SICISR_TRDY 0x00000004
#define TXx927_SICISR_TXALS 0x00000002
#define TXx927_SICISR_UBRKD 0x00000001
/* SIFCR : FIFO Control */
#define TXx927_SIFCR_SWRST 0x00008000
#define TXx927_SIFCR_RDIL_MASK 0x00000180
#define TXx927_SIFCR_RDIL_1 0x00000000
#define TXx927_SIFCR_RDIL_4 0x00000080
#define TXx927_SIFCR_RDIL_8 0x00000100
#define TXx927_SIFCR_RDIL_12 0x00000180
#define TXx927_SIFCR_RDIL_MAX 0x00000180
#define TXx927_SIFCR_TDIL_MASK 0x00000018
#define TXx927_SIFCR_TDIL_MASK 0x00000018
#define TXx927_SIFCR_TDIL_1 0x00000000
#define TXx927_SIFCR_TDIL_4 0x00000001
#define TXx927_SIFCR_TDIL_8 0x00000010
#define TXx927_SIFCR_TDIL_MAX 0x00000010
#define TXx927_SIFCR_TFRST 0x00000004
#define TXx927_SIFCR_RFRST 0x00000002
#define TXx927_SIFCR_FRSTE 0x00000001
#define TXx927_SIO_TX_FIFO 8
#define TXx927_SIO_RX_FIFO 16
/* SIFLCR : Flow Control */
#define TXx927_SIFLCR_RCS 0x00001000
#define TXx927_SIFLCR_TES 0x00000800
#define TXx927_SIFLCR_RTSSC 0x00000200
#define TXx927_SIFLCR_RSDE 0x00000100
#define TXx927_SIFLCR_TSDE 0x00000080
#define TXx927_SIFLCR_RTSTL_MASK 0x0000001e
#define TXx927_SIFLCR_RTSTL_MAX 0x0000001e
#define TXx927_SIFLCR_TBRK 0x00000001
/* SIBGR : Baudrate Control */
#define TXx927_SIBGR_BCLK_MASK 0x00000300
#define TXx927_SIBGR_BCLK_T0 0x00000000
#define TXx927_SIBGR_BCLK_T2 0x00000100
#define TXx927_SIBGR_BCLK_T4 0x00000200
#define TXx927_SIBGR_BCLK_T6 0x00000300
#define TXx927_SIBGR_BRD_MASK 0x000000ff
/*
* PIO
*/
#endif /* __ASM_MIPS_TXX927_H */
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