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[Linux-mips-commits]CVS: linux/include/asm-mips/sibyte 64bit.h,NONE,1.1 sb1250.h,NONE,1.1 sb1250_defs.h,NONE,1.1 sb1250_dma.h,NONE,1.1 sb1250_genbus.h,NONE,1.1 sb1250_int.h,NONE,1.1 sb1250_l2c.h,NONE,1.1 sb1250_ldt.h,NONE,1.1 sb1250_mac.h,NONE,1.1 sb1250_mc.h,NONE,1.1 sb1250_pci.h,NONE,1.1 sb1250_prof.h,NONE,1.1 sb1250_regs.h,NONE,1.1 sb1250_scd.h,NONE,1.1 sb1250_smbus.h,NONE,1.1 sb1250_syncser.h,NONE,1.1 sb1250_uart.h,NONE,1.1 sbmips.h,NONE,1.1 swarm.h,NONE,1.1
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From: James S. <jsi...@us...> - 2001-11-08 17:28:28
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Update of /cvsroot/linux-mips/linux/include/asm-mips/sibyte
In directory usw-pr-cvs1:/tmp/cvs-serv4111/asm-mips/sibyte
Added Files:
64bit.h sb1250.h sb1250_defs.h sb1250_dma.h sb1250_genbus.h
sb1250_int.h sb1250_l2c.h sb1250_ldt.h sb1250_mac.h
sb1250_mc.h sb1250_pci.h sb1250_prof.h sb1250_regs.h
sb1250_scd.h sb1250_smbus.h sb1250_syncser.h sb1250_uart.h
sbmips.h swarm.h
Log Message:
More Sibyte bulk merging.
--- NEW FILE: 64bit.h ---
/*
* Copyright (C) 2000, 2001 Broadcom Corporation
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#ifndef _SB1_64BIT_H
#define _SB1_64BIT_H
#include <asm/system.h>
/* This is annoying...we can't actually write the 64-bit IO
register properly without having access to 64-bit registers...
which doesn't work by default in o32 format...grrr...*/
extern inline void out64(u64 val, unsigned long addr)
{
u32 low, high;
unsigned long flags;
high = val >> 32;
low = val & 0xffffffff;
// save_flags(flags);
__save_and_cli(flags);
__asm__ __volatile__ (
".set push\n"
".set noreorder\n"
".set noat\n"
".set mips4\n"
" dsll32 $2, %1, 0 \n"
" dsll32 $1, %0, 0 \n"
" dsrl32 $2, $2, 0 \n"
" or $1, $1, $2 \n"
" sd $1, (%2)\n"
".set pop\n"
::"r" (high), "r" (low), "r" (addr)
:"$1", "$2");
__restore_flags(flags);
}
extern inline u64 in64(unsigned long addr)
{
u32 low, high;
unsigned long flags;
__save_and_cli(flags);
__asm__ __volatile__ (
".set push\n"
".set noreorder\n"
".set noat \n"
".set mips4 \n"
" ld %1, (%2)\n"
" dsra32 %0, %1, 0\n"
" sll %1, %1, 0\n"
".set pop\n"
:"=r" (high), "=r" (low): "r" (addr));
__restore_flags(flags);
return (((u64)high) << 32) | low;
}
#endif
--- NEW FILE: sb1250.h ---
/*
* Copyright (C) 2000, 2001 Broadcom Corporation
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#ifndef _ASM_SIBYTE_SB1250_H
#define _ASM_SIBYTE_SB1250_H
extern void sb1250_time_init(void);
extern void sb1250_mask_irq(int cpu, int irq);
extern void sb1250_unmask_irq(int cpu, int irq);
extern void sb1250_smp_finish(void);
#define IO_SPACE_BASE 0xa0000000UL
#endif
--- NEW FILE: sb1250_defs.h ---
/* *********************************************************************
* SB1250 Board Support Package
*
* Global constants and macros File: sb1250_defs.h
*
* This file contains macros and definitions used by the other
* include files.
*
* Author: Mitch Lichtenberg (mi...@si...)
*
*********************************************************************
*
* Copyright 2000,2001
* Broadcom Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
********************************************************************* */
/* *********************************************************************
* Naming schemes for constants in these files:
*
* M_xxx MASK constant (identifies bits in a register).
* For multi-bit fields, all bits in the field will
* be set.
*
* K_xxx "Code" constant (value for data in a multi-bit
* field). The value is right justified.
*
* V_xxx "Value" constant. This is the same as the
* corresponding "K_xxx" constant, except it is
* shifted to the correct position in the register.
*
* S_xxx SHIFT constant. This is the number of bits that
* a field value (code) needs to be shifted
* (towards the left) to put the value in the right
* position for the register.
*
* A_xxx ADDRESS constant. This will be a physical
* address. Use the PHYS_TO_K1 macro to generate
* a K1SEG address.
*
* R_xxx RELATIVE offset constant. This is an offset from
* an A_xxx constant (usually the first register in
* a group).
*
* G_xxx(X) GET value. This macro obtains a multi-bit field
* from a register, masks it, and shifts it to
* the bottom of the register (retrieving a K_xxx
* value, for example).
*
* V_xxx(X) VALUE. This macro computes the value of a
* K_xxx constant shifted to the correct position
* in the register.
********************************************************************* */
#ifndef _SB1250_DEFS_H
#define _SB1250_DEFS_H
/*
* Cast to 64-bit number. Presumably the syntax is different in
* assembly language.
*
* Note: you'll need to define uint32_t and uint64_t in your headers.
*/
#if !defined(__ASSEMBLER__)
#define _SB_MAKE64(x) ((uint64_t)(x))
#define _SB_MAKE32(x) ((uint32_t)(x))
#else
#define _SB_MAKE64(x) (x)
#define _SB_MAKE32(x) (x)
#endif
/*
* Make a mask for 1 bit at position 'n'
*/
#define _SB_MAKEMASK1(n) (_SB_MAKE64(1) << _SB_MAKE64(n))
#define _SB_MAKEMASK1_32(n) (_SB_MAKE32(1) << _SB_MAKE32(n))
/*
* Make a mask for 'v' bits at position 'n'
*/
#define _SB_MAKEMASK(v,n) (_SB_MAKE64((_SB_MAKE64(1)<<(v))-1) << _SB_MAKE64(n))
#define _SB_MAKEMASK_32(v,n) (_SB_MAKE32((_SB_MAKE32(1)<<(v))-1) << _SB_MAKE32(n))
/*
* Make a value at 'v' at bit position 'n'
*/
#define _SB_MAKEVALUE(v,n) (_SB_MAKE64(v) << _SB_MAKE64(n))
#define _SB_MAKEVALUE_32(v,n) (_SB_MAKE32(v) << _SB_MAKE32(n))
#define _SB_GETVALUE(v,n,m) ((_SB_MAKE64(v) & _SB_MAKE64(m)) >> _SB_MAKE64(n))
#define _SB_GETVALUE_32(v,n,m) ((_SB_MAKE32(v) & _SB_MAKE32(m)) >> _SB_MAKE32(n))
/*
* Macros to read/write on-chip registers
* XXX should we do the PHYS_TO_K1 here?
*/
#if !defined(__ASSEMBLER__)
#define SBWRITECSR(csr,val) *((volatile uint64_t *) PHYS_TO_K1(csr)) = (val)
#define SBREADCSR(csr) (*((volatile uint64_t *) PHYS_TO_K1(csr)))
#endif /* __ASSEMBLER__ */
#endif
--- NEW FILE: sb1250_dma.h ---
/* *********************************************************************
* SB1250 Board Support Package
*
* DMA definitions File: sb1250_dma.h
*
* This module contains constants and macros useful for
* programming the SB1250's DMA controllers, both the data mover
* and the Ethernet DMA.
*
* SB1250 specification level: 0.2
*
* Author: Mitch Lichtenberg (mi...@si...)
*
*********************************************************************
*
* Copyright 2000,2001
* Broadcom Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
********************************************************************* */
#ifndef _SB1250_DMA_H
#define _SB1250_DMA_H
#include "sb1250_defs.h"
/* *********************************************************************
* DMA Registers
********************************************************************* */
/*
* Ethernet and Serial DMA Configuration Register 0 (Table 7-4)
* Registers: DMA_CONFIG0_MAC_x_RX_CH_0
* Registers: DMA_CONFIG0_MAC_x_TX_CH_0
* Registers: DMA_CONFIG0_SER_x_RX
* Registers: DMA_CONFIG0_SER_x_TX
*/
#define M_DMA_DROP _SB_MAKEMASK1(0)
#define M_DMA_CHAIN_SEL _SB_MAKEMASK1(1)
#define M_DMA_RESERVED1 _SB_MAKEMASK1(2)
#define M_DMA_EOP_INT_EN _SB_MAKEMASK1(3)
#define M_DMA_HWM_INT_EN _SB_MAKEMASK1(4)
#define M_DMA_LWM_INT_EN _SB_MAKEMASK1(5)
#define M_DMA_TBX_EN _SB_MAKEMASK1(6)
#define M_DMA_TDX_EN _SB_MAKEMASK1(7)
#define S_DMA_INT_PKTCNT _SB_MAKE64(8)
#define M_DMA_INT_PKTCNT _SB_MAKEMASK(8,S_DMA_INT_PKTCNT)
#define V_DMA_INT_PKTCNT(x) _SB_MAKEVALUE(x,S_DMA_INT_PKTCNT)
#define G_DMA_INT_PKTCNT(x) _SB_GETVALUE(x,S_DMA_INT_PKTCNT,M_DMA_INT_PKTCNT)
#define S_DMA_RINGSZ _SB_MAKE64(16)
#define M_DMA_RINGSZ _SB_MAKEMASK(16,S_DMA_RINGSZ)
#define V_DMA_RINGSZ(x) _SB_MAKEVALUE(x,S_DMA_RINGSZ)
#define G_DMA_RINGSZ(x) _SB_GETVALUE(x,S_DMA_RINGSZ,M_DMA_RINGSZ)
#define S_DMA_HIGH_WATERMARK _SB_MAKE64(32)
#define M_DMA_HIGH_WATERMARK _SB_MAKEMASK(16,S_DMA_HIGH_WATERMARK)
#define V_DMA_HIGH_WATERMARK(x) _SB_MAKEVALUE(x,S_DMA_HIGH_WATERMARK)
#define G_DMA_HIGH_WATERMARK(x) _SB_GETVALUE(x,S_DMA_HIGH_WATERMARK,M_DMA_HIGH_WATERMARK)
#define S_DMA_LOW_WATERMARK _SB_MAKE64(48)
#define M_DMA_LOW_WATERMARK _SB_MAKEMASK(16,S_DMA_LOW_WATERMARK)
#define V_DMA_LOW_WATERMARK(x) _SB_MAKEVALUE(x,S_DMA_LOW_WATERMARK)
#define G_DMA_LOW_WATERMARK(x) _SB_GETVALUE(x,S_DMA_LOW_WATERMARK,M_DMA_LOW_WATERMARK)
/*
* Ethernet and Serial DMA Configuration Register 2 (Table 7-5)
* Registers: DMA_CONFIG1_MAC_x_RX_CH_0
* Registers: DMA_CONFIG1_DMA_x_TX_CH_0
* Registers: DMA_CONFIG1_SER_x_RX
* Registers: DMA_CONFIG1_SER_x_TX
*/
#define M_DMA_HDR_CF_EN _SB_MAKEMASK1(0)
#define M_DMA_ASIC_XFR_EN _SB_MAKEMASK1(1)
#define M_DMA_PRE_ADDR_EN _SB_MAKEMASK1(2)
#define M_DMA_FLOW_CTL_EN _SB_MAKEMASK1(3)
#define M_DMA_NO_DSCR_UPDT _SB_MAKEMASK1(4)
#define M_DMA_L2CA _SB_MAKEMASK1(5)
#define M_DMA_MBZ1 _SB_MAKEMASK(6,15)
#define S_DMA_HDR_SIZE _SB_MAKE64(21)
#define M_DMA_HDR_SIZE _SB_MAKEMASK(9,S_DMA_HDR_SIZE)
#define V_DMA_HDR_SIZE(x) _SB_MAKEVALUE(x,S_DMA_HDR_SIZE)
#define G_DMA_HDR_SIZE(x) _SB_GETVALUE(x,S_DMA_HDR_SIZE,M_DMA_HDR_SIZE)
#define M_DMA_MBZ2 _SB_MAKEMASK(5,32)
#define S_DMA_ASICXFR_SIZE _SB_MAKE64(37)
#define M_DMA_ASICXFR_SIZE _SB_MAKEMASK(9,S_DMA_ASICXFR_SIZE)
#define V_DMA_ASICXFR_SIZE(x) _SB_MAKEVALUE(x,S_DMA_ASICXFR_SIZE)
#define G_DMA_ASICXFR_SIZE(x) _SB_GETVALUE(x,S_DMA_ASICXFR_SIZE,M_DMA_ASICXFR_SIZE)
#define S_DMA_INT_TIMEOUT _SB_MAKE64(48)
#define M_DMA_INT_TIMEOUT _SB_MAKEMASK(16,S_DMA_INT_TIMEOUT)
#define V_DMA_INT_TIMEOUT(x) _SB_MAKEVALUE(x,S_DMA_INT_TIMEOUT)
#define G_DMA_INT_TIMEOUT(x) _SB_GETVALUE(x,S_DMA_INT_TIMEOUT,M_DMA_INT_TIMEOUT)
/*
* Ethernet and Serial DMA Descriptor base address (Table 7-6)
*/
#define M_DMA_DSCRBASE_MBZ _SB_MAKEMASK(4,0)
/*
* ASIC Mode Base Address (Table 7-7)
*/
#define M_DMA_ASIC_BASE_MBZ _SB_MAKEMASK(20,0)
/*
* DMA Descriptor Count Registers (Table 7-8)
*/
/* No bitfields */
/*
* Current Descriptor Address Register (Table 7-11)
*/
#define S_DMA_CURDSCR_ADDR _SB_MAKE64(0)
#define M_DMA_CURDSCR_ADDR _SB_MAKEMASK(40,S_DMA_CURDSCR_ADDR)
#define S_DMA_CURDSCR_COUNT _SB_MAKE64(48)
#define M_DMA_CURDSCR_COUNT _SB_MAKEMASK(16,S_DMA_CURDSCR_COUNT)
/* *********************************************************************
* DMA Descriptors
********************************************************************* */
/*
* Descriptor doubleword "A" (Table 7-12)
*/
#define S_DMA_DSCRA_OFFSET _SB_MAKE64(0)
#define M_DMA_DSCRA_OFFSET _SB_MAKEMASK(5,S_DMA_DSCRA_OFFSET)
/* Note: Don't shift the address over, just mask it with the mask below */
#define S_DMA_DSCRA_A_ADDR _SB_MAKE64(5)
#define M_DMA_DSCRA_A_ADDR _SB_MAKEMASK(35,S_DMA_DSCRA_A_ADDR)
#define M_DMA_DSCRA_A_ADDR_OFFSET (M_DMA_DSCRA_OFFSET | M_DMA_DSCRA_A_ADDR)
#define S_DMA_DSCRA_A_SIZE _SB_MAKE64(40)
#define M_DMA_DSCRA_A_SIZE _SB_MAKEMASK(9,S_DMA_DSCRA_A_SIZE)
#define V_DMA_DSCRA_A_SIZE(x) _SB_MAKEVALUE(x,S_DMA_DSCRA_A_SIZE)
#define G_DMA_DSCRA_A_SIZE(x) _SB_GETVALUE(x,S_DMA_DSCRA_A_SIZE,M_DMA_DSCRA_A_SIZE)
#define M_DMA_DSCRA_INTERRUPT _SB_MAKEMASK1(49)
#define M_DMA_DSCRA_OFFSETB _SB_MAKEMASK1(50)
#define S_DMA_DSCRA_STATUS _SB_MAKE64(51)
#define M_DMA_DSCRA_STATUS _SB_MAKEMASK(13,S_DMA_DSCRA_STATUS)
#define V_DMA_DSCRA_STATUS(x) _SB_MAKEVALUE(x,S_DMA_DSCRA_STATUS)
#define G_DMA_DSCRA_STATUS(x) _SB_GETVALUE(x,S_DMA_DSCRA_STATUS,M_DMA_DSCRA_STATUS)
/*
* Descriptor doubleword "B" (Table 7-13)
*/
#define S_DMA_DSCRB_OPTIONS _SB_MAKE64(0)
#define M_DMA_DSCRB_OPTIONS _SB_MAKEMASK(4,S_DMA_DSCRB_OPTIONS)
#define V_DMA_DSCRB_OPTIONS(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_OPTIONS)
#define G_DMA_DSCRB_OPTIONS(x) _SB_GETVALUE(x,S_DMA_DSCRB_OPTIONS,M_DMA_DSCRB_OPTIONS)
#define R_DMA_DSCRB_ADDR _SB_MAKE64(0x10)
/* Note: Don't shift the address over, just mask it with the mask below */
#define S_DMA_DSCRB_B_ADDR _SB_MAKE64(5)
#define M_DMA_DSCRB_B_ADDR _SB_MAKEMASK(35,S_DMA_DSCRB_B_ADDR)
#define S_DMA_DSCRB_B_SIZE _SB_MAKE64(40)
#define M_DMA_DSCRB_B_SIZE _SB_MAKEMASK(9,S_DMA_DSCRB_B_SIZE)
#define V_DMA_DSCRB_B_SIZE(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_B_SIZE)
#define G_DMA_DSCRB_B_SIZE(x) _SB_GETVALUE(x,S_DMA_DSCRB_B_SIZE,M_DMA_DSCRB_B_SIZE)
#define M_DMA_DSCRB_B_VALID _SB_MAKEMASK1(49)
#define S_DMA_DSCRB_PKT_SIZE _SB_MAKE64(50)
#define M_DMA_DSCRB_PKT_SIZE _SB_MAKEMASK(14,S_DMA_DSCRB_PKT_SIZE)
#define V_DMA_DSCRB_PKT_SIZE(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_PKT_SIZE)
#define G_DMA_DSCRB_PKT_SIZE(x) _SB_GETVALUE(x,S_DMA_DSCRB_PKT_SIZE,M_DMA_DSCRB_PKT_SIZE)
/*
* Ethernet Descriptor Status Bits (Table 7-15)
*/
#define M_DMA_ETHRX_BADIP4CS _SB_MAKEMASK1(51)
#define M_DMA_ETHRX_DSCRERR _SB_MAKEMASK1(52)
#define S_DMA_ETHRX_RXCH 53
#define M_DMA_ETHRX_RXCH _SB_MAKEMASK(2,S_DMA_ETHRX_RXCH)
#define V_DMA_ETHRX_RXCH(x) _SB_MAKEVALUE(x,S_DMA_ETHRX_RXCH)
#define G_DMA_ETHRX_RXCH(x) _SB_GETVALUE(x,S_DMA_ETHRX_RXCH,M_DMA_ETHRX_RXCH)
#define S_DMA_ETHRX_PKTTYPE 55
#define M_DMA_ETHRX_PKTTYPE _SB_MAKEMASK(3,S_DMA_ETHRX_PKTTYPE)
#define V_DMA_ETHRX_PKTTYPE(x) _SB_MAKEVALUE(x,S_DMA_ETHRX_PKTTYPE)
#define G_DMA_ETHRX_PKTTYPE(x) _SB_GETVALUE(x,S_DMA_ETHRX_PKTTYPE,M_DMA_ETHRX_PKTTYPE)
#define K_DMA_ETHRX_PKTTYPE_IPV4 0
#define K_DMA_ETHRX_PKTTYPE_ARPV4 1
#define K_DMA_ETHRX_PKTTYPE_802 2
#define K_DMA_ETHRX_PKTTYPE_OTHER 3
#define K_DMA_ETHRX_PKTTYPE_USER0 4
#define K_DMA_ETHRX_PKTTYPE_USER1 5
#define K_DMA_ETHRX_PKTTYPE_USER2 6
#define K_DMA_ETHRX_PKTTYPE_USER3 7
#define M_DMA_ETHRX_MATCH_EXACT _SB_MAKEMASK1(58)
#define M_DMA_ETHRX_MATCH_HASH _SB_MAKEMASK1(59)
#define M_DMA_ETHRX_BCAST _SB_MAKEMASK1(60)
#define M_DMA_ETHRX_MCAST _SB_MAKEMASK1(61)
#define M_DMA_ETHRX_BAD _SB_MAKEMASK1(62)
#define M_DMA_ETHRX_SOP _SB_MAKEMASK1(63)
/*
* Ethernet Transmit Status Bits (Table 7-16)
*/
#define M_DMA_ETHTX_SOP _SB_MAKEMASK1(63)
/*
* Ethernet Transmit Options (Table 7-17)
*/
#define K_DMA_ETHTX_NOTSOP _SB_MAKE64(0x00)
#define K_DMA_ETHTX_APPENDCRC _SB_MAKE64(0x01)
#define K_DMA_ETHTX_REPLACECRC _SB_MAKE64(0x02)
#define K_DMA_ETHTX_APPENDCRC_APPENDPAD _SB_MAKE64(0x03)
#define K_DMA_ETHTX_APPENDVLAN_REPLACECRC _SB_MAKE64(0x04)
#define K_DMA_ETHTX_REMOVEVLAN_REPLACECRC _SB_MAKE64(0x05)
#define K_DMA_ETHTX_REPLACEVLAN_REPLACECRC _SB_MAKE64(0x6)
#define K_DMA_ETHTX_NOMODS _SB_MAKE64(0x07)
#define K_DMA_ETHTX_RESERVED1 _SB_MAKE64(0x08)
#define K_DMA_ETHTX_REPLACESADDR_APPENDCRC _SB_MAKE64(0x09)
#define K_DMA_ETHTX_REPLACESADDR_REPLACECRC _SB_MAKE64(0x0A)
#define K_DMA_ETHTX_REPLACESADDR_APPENDCRC_APPENDPAD _SB_MAKE64(0x0B)
#define K_DMA_ETHTX_REPLACESADDR_APPENDVLAN_REPLACECRC _SB_MAKE64(0x0C)
#define K_DMA_ETHTX_REPLACESADDR_REMOVEVLAN_REPLACECRC _SB_MAKE64(0x0D)
#define K_DMA_ETHTX_REPLACESADDR_REPLACEVLAN_REPLACECRC _SB_MAKE64(0x0E)
#define K_DMA_ETHTX_RESERVED2 _SB_MAKE64(0x0F)
/*
* Serial Receive Options (Table 7-18)
*/
#define M_DMA_SERRX_CRC_ERROR _SB_MAKEMASK1(56)
#define M_DMA_SERRX_ABORT _SB_MAKEMASK1(57)
#define M_DMA_SERRX_OCTET_ERROR _SB_MAKEMASK1(58)
#define M_DMA_SERRX_LONGFRAME_ERROR _SB_MAKEMASK1(59)
#define M_DMA_SERRX_SHORTFRAME_ERROR _SB_MAKEMASK1(60)
#define M_DMA_SERRX_OVERRUN_ERROR _SB_MAKEMASK1(61)
#define M_DMA_SERRX_GOOD _SB_MAKEMASK1(62)
#define M_DMA_SERRX_SOP _SB_MAKEMASK1(63)
/*
* Serial Transmit Status Bits (Table 7-20)
*/
#define M_DMA_SERTX_FLAG _SB_MAKEMASK1(63)
/*
* Serial Transmit Options (Table 7-21)
*/
#define K_DMA_SERTX_RESERVED _SB_MAKEMASK1(0)
#define K_DMA_SERTX_APPENDCRC _SB_MAKEMASK1(1)
#define K_DMA_SERTX_APPENDPAD _SB_MAKEMASK1(2)
#define K_DMA_SERTX_ABORT _SB_MAKEMASK1(3)
/* *********************************************************************
* Data Mover Registers
********************************************************************* */
/*
* Data Mover Descriptor Base Address Register (Table 7-22)
* Register: DM_DSCR_BASE_0
* Register: DM_DSCR_BASE_1
* Register: DM_DSCR_BASE_2
* Register: DM_DSCR_BASE_3
*/
#define M_DM_DSCR_BASE_MBZ _SB_MAKEMASK(3,0)
/* Note: Just mask the base address and then OR it in. */
#define S_DM_DSCR_BASE_ADDR _SB_MAKE64(3)
#define M_DM_DSCR_BASE_ADDR _SB_MAKEMASK(36,S_DM_DSCR_BASE_ADDR)
#define S_DM_DSCR_BASE_RINGSZ _SB_MAKE64(40)
#define M_DM_DSCR_BASE_RINGSZ _SB_MAKEMASK(16,S_DM_DSCR_BASE_RINGSZ)
#define V_DM_DSCR_BASE_RINGSZ(x) _SB_MAKEVALUE(x,S_DM_DSCR_BASE_RINGSZ)
#define G_DM_DSCR_BASE_RINGSZ(x) _SB_GETVALUE(x,S_DM_DSCR_BASE_RINGSZ,M_DM_DSCR_BASE_RINGSZ)
#define S_DM_DSCR_BASE_PRIORITY _SB_MAKE64(56)
#define M_DM_DSCR_BASE_PRIORITY _SB_MAKEMASK(3,S_DM_DSCR_BASE_PRIORITY)
#define V_DM_DSCR_BASE_PRIORITY(x) _SB_MAKEVALUE(x,S_DM_DSCR_BASE_PRIORITY)
#define G_DM_DSCR_BASE_PRIORITY(x) _SB_GETVALUE(x,S_DM_DSCR_BASE_PRIORITY,M_DM_DSCR_BASE_PRIORITY)
#define K_DM_DSCR_BASE_PRIORITY_1 0
#define K_DM_DSCR_BASE_PRIORITY_2 1
#define K_DM_DSCR_BASE_PRIORITY_4 2
#define K_DM_DSCR_BASE_PRIORITY_8 3
#define K_DM_DSCR_BASE_PRIORITY_16 4
#define M_DM_DSCR_BASE_ACTIVE _SB_MAKEMASK1(59)
#define M_DM_DSCR_BASE_INTERRUPT _SB_MAKEMASK1(60)
#define M_DM_DSCR_BASE_RESET _SB_MAKEMASK1(61) /* write register */
#define M_DM_DSCR_BASE_ERROR _SB_MAKEMASK1(61) /* read register */
#define M_DM_DSCR_BASE_ABORT _SB_MAKEMASK1(62)
#define M_DM_DSCR_BASE_ENABL _SB_MAKEMASK1(63)
/*
* Data Mover Descriptor Count Register (Table 7-25)
*/
/* no bitfields */
/*
* Data Mover Current Descriptor Address (Table 7-24)
* Register: DM_CUR_DSCR_ADDR_0
* Register: DM_CUR_DSCR_ADDR_1
* Register: DM_CUR_DSCR_ADDR_2
* Register: DM_CUR_DSCR_ADDR_3
*/
#define S_DM_CUR_DSCR_DSCR_ADDR _SB_MAKE64(0)
#define M_DM_CUR_DSCR_DSCR_ADDR _SB_MAKEMASK(40,S_DM_CUR_DSCR_DSCR_ADDR)
#define S_DM_CUR_DSCR_DSCR_COUNT _SB_MAKE64(48)
#define M_DM_CUR_DSCR_DSCR_COUNT _SB_MAKEMASK(16,S_DM_CUR_DSCR_DSCR_COUNT)
#define V_DM_CUR_DSCR_DSCR_COUNT(r) _SB_MAKEVALUE(r,S_DM_CUR_DSCR_DSCR_COUNT)
#define G_DM_CUR_DSCR_DSCR_COUNT(r) _SB_GETVALUE(r,S_DM_CUR_DSCR_DSCR_COUNT,\
M_DM_CUR_DSCR_DSCR_COUNT)
/*
* Data Mover Descriptor Doubleword "A" (Table 7-26)
*/
#define S_DM_DSCRA_DST_ADDR _SB_MAKE64(0)
#define M_DM_DSCRA_DST_ADDR _SB_MAKEMASK(40,S_DM_DSCRA_DST_ADDR)
#define M_DM_DSCRA_UN_DEST _SB_MAKEMASK1(40)
#define M_DM_DSCRA_UN_SRC _SB_MAKEMASK1(41)
#define M_DM_DSCRA_INTERRUPT _SB_MAKEMASK1(42)
#define M_DM_DSCRA_THROTTLE _SB_MAKEMASK1(43)
#define S_DM_DSCRA_DIR_DEST _SB_MAKE64(44)
#define M_DM_DSCRA_DIR_DEST _SB_MAKEMASK(2,S_DM_DSCRA_DIR_DEST)
#define V_DM_DSCRA_DIR_DEST(x) _SB_MAKEVALUE(x,S_DM_DSCRA_DIR_DEST)
#define G_DM_DSCRA_DIR_DEST(x) _SB_GETVALUE(x,S_DM_DSCRA_DIR_DEST,M_DM_DSCRA_DIR_DEST)
#define K_DM_DSCRA_DIR_DEST_INCR 0
#define K_DM_DSCRA_DIR_DEST_DECR 1
#define K_DM_DSCRA_DIR_DEST_CONST 2
#define V_DM_DSCRA_DIR_DEST_INCR _SB_MAKEVALUE(K_DM_DSCRA_DIR_DEST_INCR,S_DM_DSCRA_DIR_DEST)
#define V_DM_DSCRA_DIR_DEST_DECR _SB_MAKEVALUE(K_DM_DSCRA_DIR_DEST_DECR,S_DM_DSCRA_DIR_DEST)
#define V_DM_DSCRA_DIR_DEST_CONST _SB_MAKEVALUE(K_DM_DSCRA_DIR_DEST_CONST,S_DM_DSCRA_DIR_DEST)
#define S_DM_DSCRA_DIR_SRC _SB_MAKE64(46)
#define M_DM_DSCRA_DIR_SRC _SB_MAKEMASK(2,S_DM_DSCRA_DIR_SRC)
#define V_DM_DSCRA_DIR_SRC(x) _SB_MAKEVALUE(x,S_DM_DSCRA_DIR_SRC)
#define G_DM_DSCRA_DIR_SRC(x) _SB_GETVALUE(x,S_DM_DSCRA_DIR_SRC,M_DM_DSCRA_DIR_SRC)
#define K_DM_DSCRA_DIR_SRC_INCR 0
#define K_DM_DSCRA_DIR_SRC_DECR 1
#define K_DM_DSCRA_DIR_SRC_CONST 2
#define V_DM_DSCRA_DIR_SRC_INCR _SB_MAKEVALUE(K_DM_DSCRA_DIR_SRC_INCR,S_DM_DSCRA_DIR_SRC)
#define V_DM_DSCRA_DIR_SRC_DECR _SB_MAKEVALUE(K_DM_DSCRA_DIR_SRC_DECR,S_DM_DSCRA_DIR_SRC)
#define V_DM_DSCRA_DIR_SRC_CONST _SB_MAKEVALUE(K_DM_DSCRA_DIR_SRC_CONST,S_DM_DSCRA_DIR_SRC)
#define M_DM_DSCRA_ZERO_MEM _SB_MAKEMASK1(48)
#define M_DM_DSCRA_PREFETCH _SB_MAKEMASK1(49)
#define M_DM_DSCRA_L2C_DEST _SB_MAKEMASK1(50)
#define M_DM_DSCRA_L2C_SRC _SB_MAKEMASK1(51)
#define M_DM_DSCRA_RESERVED2 _SB_MAKEMASK(12,52)
/*
* Data Mover Descriptor Doubleword "B" (Table 7-25)
*/
#define S_DM_DSCRB_SRC_ADDR _SB_MAKE64(0)
#define M_DM_DSCRB_SRC_ADDR _SB_MAKEMASK(40,S_DM_DSCRB_SRC_ADDR)
#define S_DM_DSCRB_SRC_LENGTH _SB_MAKE64(40)
#define M_DM_DSCRB_SRC_LENGTH _SB_MAKEMASK(20,S_DM_DSCRB_SRC_LENGTH)
#define V_DM_DSCRB_SRC_LENGTH(x) _SB_MAKEVALUE(x,S_DM_DSCRB_SRC_LENGTH)
#define G_DM_DSCRB_SRC_LENGTH(x) _SB_GETVALUE(x,S_DM_DSCRB_SRC_LENGTH,M_DM_DSCRB_SRC_LENGTH)
#endif
--- NEW FILE: sb1250_genbus.h ---
/* *********************************************************************
* SB1250 Board Support Package
*
* Generic Bus Constants File: sb1250_genbus.h
*
* This module contains constants and macros useful for
* manipulating the SB1250's Generic Bus interface
*
* SB1250 specification level: 0.2
*
* Author: Mitch Lichtenberg (mi...@si...)
*
*********************************************************************
*
* Copyright 2000,2001
* Broadcom Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
********************************************************************* */
#ifndef _SB1250_GENBUS_H
#define _SB1250_GENBUS_H
#include "sb1250_defs.h"
/*
* Generic Bus Region Configuration Registers (Table 11-4)
*/
#define M_IO_RDY_ACTIVE _SB_MAKEMASK1(0)
#define M_IO_ENA_RDY _SB_MAKEMASK1(1)
#define S_IO_WIDTH_SEL 2
#define M_IO_WIDTH_SEL _SB_MAKEMASK(2,S_IO_WIDTH_SEL)
#define K_IO_WIDTH_SEL_1 0
#define K_IO_WIDTH_SEL_2 1
#define K_IO_WIDTH_SEL_4 3
#define V_IO_WIDTH_SEL(x) _SB_MAKEVALUE(x,S_IO_WIDTH_SEL)
#define G_IO_WIDTH_SEL(x) _SB_GETVALUE(x,S_IO_WIDTH_SEL,M_IO_WIDTH_SEL)
#define M_IO_PARITY_ENA _SB_MAKEMASK1(4)
#define M_IO_PARITY_ODD _SB_MAKEMASK1(6)
#define M_IO_NONMUX _SB_MAKEMASK1(7)
#define S_IO_TIMEOUT 8
#define M_IO_TIMEOUT _SB_MAKEMASK(8,S_IO_TIMEOUT)
#define V_IO_TIMEOUT(x) _SB_MAKEVALUE(x,S_IO_TIMEOUT)
#define G_IO_TIMEOUT(x) _SB_GETVALUE(x,S_IO_TIMEOUT,M_IO_TIMEOUT)
/*
* Generic Bus Region Size register (Table 11-5)
*/
#define S_IO_MULT_SIZE 0
#define M_IO_MULT_SIZE _SB_MAKEMASK(12,S_IO_MULT_SIZE)
#define V_IO_MULT_SIZE(x) _SB_MAKEVALUE(x,S_IO_MULT_SIZE)
#define G_IO_MULT_SIZE(x) _SB_GETVALUE(x,S_IO_MULT_SIZE,M_IO_MULT_SIZE)
#define S_IO_REGSIZE 16 /* # bits to shift size for this reg */
/*
* Generic Bus Region Address (Table 11-6)
*/
#define S_IO_START_ADDR 0
#define M_IO_START_ADDR _SB_MAKEMASK(14,S_IO_START_ADDR)
#define V_IO_START_ADDR(x) _SB_MAKEVALUE(x,S_IO_START_ADDR)
#define G_IO_START_ADDR(x) _SB_GETVALUE(x,S_IO_START_ADDR,M_IO_START_ADDR)
#define S_IO_ADDRBASE 16 /* # bits to shift addr for this reg */
/*
* Generic Bus Region 0 Timing Registers (Table 11-7)
*/
#define S_IO_ALE_WIDTH 0
#define M_IO_ALE_WIDTH _SB_MAKEMASK(3,S_IO_ALE_WIDTH)
#define V_IO_ALE_WIDTH(x) _SB_MAKEVALUE(x,S_IO_ALE_WIDTH)
#define G_IO_ALE_WIDTH(x) _SB_GETVALUE(x,S_IO_ALE_WIDTH,M_IO_ALE_WIDTH)
#define S_IO_ALE_TO_CS 4
#define M_IO_ALE_TO_CS _SB_MAKEMASK(2,S_IO_ALE_TO_CS)
#define V_IO_ALE_TO_CS(x) _SB_MAKEVALUE(x,S_IO_ALE_TO_CS)
#define G_IO_ALE_TO_CS(x) _SB_GETVALUE(x,S_IO_ALE_TO_CS,M_IO_ALE_TO_CS)
#define S_IO_CS_WIDTH 8
#define M_IO_CS_WIDTH _SB_MAKEMASK(5,S_IO_CS_WIDTH)
#define V_IO_CS_WIDTH(x) _SB_MAKEVALUE(x,S_IO_CS_WIDTH)
#define G_IO_CS_WIDTH(x) _SB_GETVALUE(x,S_IO_CS_WIDTH,M_IO_CS_WIDTH)
#define S_IO_RDY_SMPLE 13
#define M_IO_RDY_SMPLE _SB_MAKEMASK(3,S_IO_RDY_SMPLE)
#define V_IO_RDY_SMPLE(x) _SB_MAKEVALUE(x,S_IO_RDY_SMPLE)
#define G_IO_RDY_SMPLE(x) _SB_GETVALUE(x,S_IO_RDY_SMPLE,M_IO_RDY_SMPLE)
/*
* Generic Bus Timing 1 Registers (Table 11-8)
*/
#define S_IO_ALE_TO_WRITE 0
#define M_IO_ALE_TO_WRITE _SB_MAKEMASK(3,S_IO_ALE_TO_WRITE)
#define V_IO_ALE_TO_WRITE(x) _SB_MAKEVALUE(x,S_IO_ALE_TO_WRITE)
#define G_IO_ALE_TO_WRITE(x) _SB_GETVALUE(x,S_IO_ALE_TO_WRITE,M_IO_ALE_TO_WRITE)
#define S_IO_WRITE_WIDTH 4
#define M_IO_WRITE_WIDTH _SB_MAKEMASK(4,S_IO_WRITE_WIDTH)
#define V_IO_WRITE_WIDTH(x) _SB_MAKEVALUE(x,S_IO_WRITE_WIDTH)
#define G_IO_WRITE_WIDTH(x) _SB_GETVALUE(x,S_IO_WRITE_WIDTH,M_IO_WRITE_WIDTH)
#define S_IO_IDLE_CYCLE 8
#define M_IO_IDLE_CYCLE _SB_MAKEMASK(4,S_IO_IDLE_CYCLE)
#define V_IO_IDLE_CYCLE(x) _SB_MAKEVALUE(x,S_IO_IDLE_CYCLE)
#define G_IO_IDLE_CYCLE(x) _SB_GETVALUE(x,S_IO_IDLE_CYCLE,M_IO_IDLE_CYCLE)
#define S_IO_CS_TO_OE 12
#define M_IO_CS_TO_OE _SB_MAKEMASK(2,S_IO_CS_TO_OE)
#define V_IO_CS_TO_OE(x) _SB_MAKEVALUE(x,S_IO_CS_TO_OE)
#define G_IO_CS_TO_OE(x) _SB_GETVALUE(x,S_IO_CS_TO_OE,M_IO_CS_TO_OE)
#define S_IO_OE_TO_CS 14
#define M_IO_OE_TO_CS _SB_MAKEMASK(2,S_IO_OE_TO_CS)
#define V_IO_OE_TO_CS(x) _SB_MAKEVALUE(x,S_IO_OE_TO_CS)
#define G_IO_OE_TO_CS(x) _SB_GETVALUE(x,S_IO_OE_TO_CS,M_IO_OE_TO_CS)
/*
* Generic Bus Interrupt Status Register (Table 11-9)
*/
#define M_IO_CS_ERR_INT _SB_MAKEMASK(0,8)
#define M_IO_CS0_ERR_INT _SB_MAKEMASK1(0)
#define M_IO_CS1_ERR_INT _SB_MAKEMASK1(1)
#define M_IO_CS2_ERR_INT _SB_MAKEMASK1(2)
#define M_IO_CS3_ERR_INT _SB_MAKEMASK1(3)
#define M_IO_CS4_ERR_INT _SB_MAKEMASK1(4)
#define M_IO_CS5_ERR_INT _SB_MAKEMASK1(5)
#define M_IO_CS6_ERR_INT _SB_MAKEMASK1(6)
#define M_IO_CS7_ERR_INT _SB_MAKEMASK1(7)
#define M_IO_RD_PAR_INT _SB_MAKEMASK1(9)
#define M_IO_TIMEOUT_INT _SB_MAKEMASK1(10)
#define M_IO_ILL_ADDR_INT _SB_MAKEMASK1(11)
#define M_IO_MULT_CS_INT _SB_MAKEMASK1(12)
/*
* PCMCIA configuration register (Table 12-6)
*/
#define M_PCMCIA_CFG_ATTRMEM _SB_MAKEMASK1(0)
#define M_PCMCIA_CFG_3VEN _SB_MAKEMASK1(1)
#define M_PCMCIA_CFG_5VEN _SB_MAKEMASK1(2)
#define M_PCMCIA_CFG_VPPEN _SB_MAKEMASK1(3)
#define M_PCMCIA_CFG_RESET _SB_MAKEMASK1(4)
#define M_PCMCIA_CFG_APWRONEN _SB_MAKEMASK1(5)
#define M_PCMCIA_CFG_CDMASK _SB_MAKEMASK1(6)
#define M_PCMCIA_CFG_WPMASK _SB_MAKEMASK1(7)
#define M_PCMCIA_CFG_RDYMASK _SB_MAKEMASK1(8)
#define M_PCMCIA_CFG_PWRCTL _SB_MAKEMASK1(9)
/*
* PCMCIA status register (Table 12-7)
*/
#define M_PCMCIA_STATUS_CD1 _SB_MAKEMASK1(0)
#define M_PCMCIA_STATUS_CD2 _SB_MAKEMASK1(1)
#define M_PCMCIA_STATUS_VS1 _SB_MAKEMASK1(2)
#define M_PCMCIA_STATUS_VS2 _SB_MAKEMASK1(3)
#define M_PCMCIA_STATUS_WP _SB_MAKEMASK1(4)
#define M_PCMCIA_STATUS_RDY _SB_MAKEMASK1(5)
#define M_PCMCIA_STATUS_3VEN _SB_MAKEMASK1(6)
#define M_PCMCIA_STATUS_5VEN _SB_MAKEMASK1(7)
#define M_PCMCIA_STATUS_CDCHG _SB_MAKEMASK1(8)
#define M_PCMCIA_STATUS_WPCHG _SB_MAKEMASK1(9)
#define M_PCMCIA_STATUS_RDYCHG _SB_MAKEMASK1(10)
/*
* GPIO Interrupt Type Register (table 13-3)
*/
#define K_GPIO_INTR_DISABLE 0
#define K_GPIO_INTR_EDGE 1
#define K_GPIO_INTR_LEVEL 2
#define K_GPIO_INTR_SPLIT 3
#define S_GPIO_INTR_TYPEX(n) (((n)/2)*2)
#define M_GPIO_INTR_TYPEX(n) _SB_MAKEMASK(2,S_GPIO_INTR_TYPEX(n))
#define V_GPIO_INTR_TYPEX(n,x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPEX(n))
#define G_GPIO_INTR_TYPEX(n,x) _SB_GETVALUE(x,S_GPIO_INTR_TYPEX(n),M_GPIO_INTR_TYPEX(n))
#define S_GPIO_INTR_TYPE0 0
#define M_GPIO_INTR_TYPE0 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE0)
#define V_GPIO_INTR_TYPE0(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE0)
#define G_GPIO_INTR_TYPE0(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE0,M_GPIO_INTR_TYPE0)
#define S_GPIO_INTR_TYPE2 2
#define M_GPIO_INTR_TYPE2 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE2)
#define V_GPIO_INTR_TYPE2(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE2)
#define G_GPIO_INTR_TYPE2(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE2,M_GPIO_INTR_TYPE2)
#define S_GPIO_INTR_TYPE4 4
#define M_GPIO_INTR_TYPE4 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE4)
#define V_GPIO_INTR_TYPE4(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE4)
#define G_GPIO_INTR_TYPE4(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE4,M_GPIO_INTR_TYPE4)
#define S_GPIO_INTR_TYPE6 6
#define M_GPIO_INTR_TYPE6 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE6)
#define V_GPIO_INTR_TYPE6(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE6)
#define G_GPIO_INTR_TYPE6(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE6,M_GPIO_INTR_TYPE6)
#define S_GPIO_INTR_TYPE8 8
#define M_GPIO_INTR_TYPE8 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE8)
#define V_GPIO_INTR_TYPE8(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE8)
#define G_GPIO_INTR_TYPE8(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE8,M_GPIO_INTR_TYPE8)
#define S_GPIO_INTR_TYPE10 10
#define M_GPIO_INTR_TYPE10 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE10)
#define V_GPIO_INTR_TYPE10(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE10)
#define G_GPIO_INTR_TYPE10(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE10,M_GPIO_INTR_TYPE10)
#define S_GPIO_INTR_TYPE12 12
#define M_GPIO_INTR_TYPE12 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE12)
#define V_GPIO_INTR_TYPE12(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE12)
#define G_GPIO_INTR_TYPE12(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE12,M_GPIO_INTR_TYPE12)
#define S_GPIO_INTR_TYPE14 14
#define M_GPIO_INTR_TYPE14 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE14)
#define V_GPIO_INTR_TYPE14(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE14)
#define G_GPIO_INTR_TYPE14(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE14,M_GPIO_INTR_TYPE14)
#endif
--- NEW FILE: sb1250_int.h ---
/* *********************************************************************
* SB1250 Board Support Package
*
* Interrupt Mapper definitions File: sb1250_int.h
*
* This module contains constants for manipulating the SB1250's
* interrupt mapper and definitions for the interrupt sources.
*
* SB1250 specification level: 0.2
*
* Author: Mitch Lichtenberg (mi...@si...)
*
*********************************************************************
*
* Copyright 2000,2001
* Broadcom Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
********************************************************************* */
#ifndef _SB1250_INT_H
#define _SB1250_INT_H
#include "sb1250_defs.h"
/* *********************************************************************
* Interrupt Mapper Constants
********************************************************************* */
/*
* Interrupt sources (Table 4-8, UM 0.2)
*
* First, the interrupt numbers.
*/
#define K_INT_WATCHDOG_TIMER_0 0
#define K_INT_WATCHDOG_TIMER_1 1
#define K_INT_TIMER_0 2
#define K_INT_TIMER_1 3
#define K_INT_TIMER_2 4
#define K_INT_TIMER_3 5
#define K_INT_SMB_0 6
#define K_INT_SMB_1 7
#define K_INT_UART_0 8
#define K_INT_UART_1 9
#define K_INT_SER_0 10
#define K_INT_SER_1 11
#define K_INT_PCMCIA 12
#define K_INT_ADDR_TRAP 13
#define K_INT_PERF_CNT 14
#define K_INT_TRACE_FREEZE 15
#define K_INT_BAD_ECC 16
#define K_INT_COR_ECC 17
#define K_INT_IO_BUS 18
#define K_INT_MAC_0 19
#define K_INT_MAC_1 20
#define K_INT_MAC_2 21
#define K_INT_DM_CH_0 22
#define K_INT_DM_CH_1 23
#define K_INT_DM_CH_2 24
#define K_INT_DM_CH_3 25
#define K_INT_MBOX_0 26
#define K_INT_MBOX_1 27
#define K_INT_MBOX_2 28
#define K_INT_MBOX_3 29
#define K_INT_SPARE_0 30
#define K_INT_SPARE_1 31
#define K_INT_GPIO_0 32
#define K_INT_GPIO_1 33
#define K_INT_GPIO_2 34
#define K_INT_GPIO_3 35
#define K_INT_GPIO_4 36
#define K_INT_GPIO_5 37
#define K_INT_GPIO_6 38
#define K_INT_GPIO_7 39
#define K_INT_GPIO_8 40
#define K_INT_GPIO_9 41
#define K_INT_GPIO_10 42
#define K_INT_GPIO_11 43
#define K_INT_GPIO_12 44
#define K_INT_GPIO_13 45
#define K_INT_GPIO_14 46
#define K_INT_GPIO_15 47
#define K_INT_LDT_FATAL 48
#define K_INT_LDT_NONFATAL 49
#define K_INT_LDT_SMI 50
#define K_INT_LDT_NMI 51
#define K_INT_LDT_INIT 52
#define K_INT_LDT_STARTUP 53
#define K_INT_LDT_EXT 54
#define K_INT_PCI_ERROR 55
#define K_INT_PCI_INTA 56
#define K_INT_PCI_INTB 57
#define K_INT_PCI_INTC 58
#define K_INT_PCI_INTD 59
#define K_INT_SPARE_2 60
#define K_INT_SPARE_3 61
#define K_INT_SPARE_4 62
#define K_INT_SPARE_5 63
/*
* Mask values for each interrupt
*/
#define M_INT_WATCHDOG_TIMER_0 _SB_MAKEMASK1(K_INT_WATCHDOG_TIMER_0)
#define M_INT_WATCHDOG_TIMER_1 _SB_MAKEMASK1(K_INT_WATCHDOG_TIMER_1)
#define M_INT_TIMER_0 _SB_MAKEMASK1(K_INT_TIMER_0)
#define M_INT_TIMER_1 _SB_MAKEMASK1(K_INT_TIMER_1)
#define M_INT_TIMER_2 _SB_MAKEMASK1(K_INT_TIMER_2)
#define M_INT_TIMER_3 _SB_MAKEMASK1(K_INT_TIMER_3)
#define M_INT_SMB_0 _SB_MAKEMASK1(K_INT_SMB_0)
#define M_INT_SMB_1 _SB_MAKEMASK1(K_INT_SMB_1)
#define M_INT_UART_0 _SB_MAKEMASK1(K_INT_UART_0)
#define M_INT_UART_1 _SB_MAKEMASK1(K_INT_UART_1)
#define M_INT_SER_0 _SB_MAKEMASK1(K_INT_SER_0)
#define M_INT_SER_1 _SB_MAKEMASK1(K_INT_SER_1)
#define M_INT_PCMCIA _SB_MAKEMASK1(K_INT_PCMCIA)
#define M_INT_ADDR_TRAP _SB_MAKEMASK1(K_INT_ADDR_TRAP)
#define M_INT_PERF_CNT _SB_MAKEMASK1(K_INT_PERF_CNT)
#define M_INT_TRACE_FREEZE _SB_MAKEMASK1(K_INT_TRACE_FREEZE)
#define M_INT_BAD_ECC _SB_MAKEMASK1(K_INT_BAD_ECC)
#define M_INT_COR_ECC _SB_MAKEMASK1(K_INT_COR_ECC)
#define M_INT_IO_BUS _SB_MAKEMASK1(K_INT_IO_BUS)
#define M_INT_MAC_0 _SB_MAKEMASK1(K_INT_MAC_0)
#define M_INT_MAC_1 _SB_MAKEMASK1(K_INT_MAC_1)
#define M_INT_MAC_2 _SB_MAKEMASK1(K_INT_MAC_2)
#define M_INT_DM_CH_0 _SB_MAKEMASK1(K_INT_DM_CH_0)
#define M_INT_DM_CH_1 _SB_MAKEMASK1(K_INT_DM_CH_1)
#define M_INT_DM_CH_2 _SB_MAKEMASK1(K_INT_DM_CH_2)
#define M_INT_DM_CH_3 _SB_MAKEMASK1(K_INT_DM_CH_3)
#define M_INT_MBOX_0 _SB_MAKEMASK1(K_INT_MBOX_0)
#define M_INT_MBOX_1 _SB_MAKEMASK1(K_INT_MBOX_1)
#define M_INT_MBOX_2 _SB_MAKEMASK1(K_INT_MBOX_2)
#define M_INT_MBOX_3 _SB_MAKEMASK1(K_INT_MBOX_3)
#define M_INT_SPARE_0 _SB_MAKEMASK1(K_INT_SPARE_0)
#define M_INT_SPARE_1 _SB_MAKEMASK1(K_INT_SPARE_1)
#define M_INT_GPIO_0 _SB_MAKEMASK1(K_INT_GPIO_0)
#define M_INT_GPIO_1 _SB_MAKEMASK1(K_INT_GPIO_1)
#define M_INT_GPIO_2 _SB_MAKEMASK1(K_INT_GPIO_2)
#define M_INT_GPIO_3 _SB_MAKEMASK1(K_INT_GPIO_3)
#define M_INT_GPIO_4 _SB_MAKEMASK1(K_INT_GPIO_4)
#define M_INT_GPIO_5 _SB_MAKEMASK1(K_INT_GPIO_5)
#define M_INT_GPIO_6 _SB_MAKEMASK1(K_INT_GPIO_6)
#define M_INT_GPIO_7 _SB_MAKEMASK1(K_INT_GPIO_7)
#define M_INT_GPIO_8 _SB_MAKEMASK1(K_INT_GPIO_8)
#define M_INT_GPIO_9 _SB_MAKEMASK1(K_INT_GPIO_9)
#define M_INT_GPIO_10 _SB_MAKEMASK1(K_INT_GPIO_10)
#define M_INT_GPIO_11 _SB_MAKEMASK1(K_INT_GPIO_11)
#define M_INT_GPIO_12 _SB_MAKEMASK1(K_INT_GPIO_12)
#define M_INT_GPIO_13 _SB_MAKEMASK1(K_INT_GPIO_13)
#define M_INT_GPIO_14 _SB_MAKEMASK1(K_INT_GPIO_14)
#define M_INT_GPIO_15 _SB_MAKEMASK1(K_INT_GPIO_15)
#define M_INT_LDT_FATAL _SB_MAKEMASK1(K_INT_LDT_FATAL)
#define M_INT_LDT_NONFATAL _SB_MAKEMASK1(K_INT_LDT_NONFATAL)
#define M_INT_LDT_SMI _SB_MAKEMASK1(K_INT_LDT_SMI)
#define M_INT_LDT_NMI _SB_MAKEMASK1(K_INT_LDT_NMI)
#define M_INT_LDT_INIT _SB_MAKEMASK1(K_INT_LDT_INIT)
#define M_INT_LDT_STARTUP _SB_MAKEMASK1(K_INT_LDT_STARTUP)
#define M_INT_LDT_EXT _SB_MAKEMASK1(K_INT_LDT_EXT)
#define M_INT_PCI_ERROR _SB_MAKEMASK1(K_INT_PCI_ERROR)
#define M_INT_PCI_INTA _SB_MAKEMASK1(K_INT_PCI_INTA)
#define M_INT_PCI_INTB _SB_MAKEMASK1(K_INT_PCI_INTB)
#define M_INT_PCI_INTC _SB_MAKEMASK1(K_INT_PCI_INTC)
#define M_INT_PCI_INTD _SB_MAKEMASK1(K_INT_PCI_INTD)
#define M_INT_SPARE_2 _SB_MAKEMASK1(K_INT_SPARE_2)
#define M_INT_SPARE_3 _SB_MAKEMASK1(K_INT_SPARE_3)
#define M_INT_SPARE_4 _SB_MAKEMASK1(K_INT_SPARE_4)
#define M_INT_SPARE_5 _SB_MAKEMASK1(K_INT_SPARE_5)
/*
* Interrupt mappings
*/
#define K_INT_MAP_I0 0 /* interrupt pins on processor */
#define K_INT_MAP_I1 1
#define K_INT_MAP_I2 2
#define K_INT_MAP_I3 3
#define K_INT_MAP_I4 4
#define K_INT_MAP_I5 5
#define K_INT_MAP_NMI 6 /* nonmaskable */
#define K_INT_MAP_DINT 7 /* debug interrupt */
/*
* LDT Interrupt Set Register (table 4-5)
*/
#define S_INT_LDT_INTMSG 0
#define M_INT_LDT_INTMSG _SB_MAKEMASK(3,S_INT_LDT_INTMSG)
#define V_INT_LDT_INTMSG(x) _SB_MAKEVALUE(x,S_INT_LDT_INTMSG)
#define G_INT_LDT_INTMSG(x) _SB_GETVALUE(x,S_INT_LDT_INTMSG,M_INT_LDT_INTMSG)
#define K_INT_LDT_INTMSG_FIXED 0
#define K_INT_LDT_INTMSG_ARBITRATED 1
#define K_INT_LDT_INTMSG_SMI 2
#define K_INT_LDT_INTMSG_NMI 3
#define K_INT_LDT_INTMSG_INIT 4
#define K_INT_LDT_INTMSG_STARTUP 5
#define K_INT_LDT_INTMSG_EXTINT 6
#define K_INT_LDT_INTMSG_RESERVED 7
#define M_INT_LDT_EDGETRIGGER 0
#define M_INT_LDT_LEVELTRIGGER _SB_MAKEMASK1(3)
#define M_INT_LDT_PHYSICALDEST 0
#define M_INT_LDT_LOGICALDEST _SB_MAKEMASK1(4)
#define S_INT_LDT_INTDEST 5
#define M_INT_LDT_INTDEST _SB_MAKEMASK(10,S_INT_LDT_INTDEST)
#define V_INT_LDT_INTDEST(x) _SB_MAKEVALUE(x,S_INT_LDT_INTDEST)
#define G_INT_LDT_INTDEST(x) _SB_GETVALUE(x,S_INT_LDT_INTDEST,M_INT_LDT_INTDEST)
#define S_INT_LDT_VECTOR 13
#define M_INT_LDT_VECTOR _SB_MAKEMASK(8,S_INT_LDT_VECTOR)
#define V_INT_LDT_VECTOR(x) _SB_MAKEVALUE(x,S_INT_LDT_VECTOR)
#define G_INT_LDT_VECTOR(x) _SB_GETVALUE(x,S_INT_LDT_VECTOR,M_INT_LDT_VECTOR)
/*
* Vector format (Table 4-6)
*/
#define M_LDTVECT_RAISEINT 0x00
#define M_LDTVECT_RAISEMBOX 0x40
#endif
--- NEW FILE: sb1250_l2c.h ---
/* *********************************************************************
* SB1250 Board Support Package
*
* L2 Cache constants and macros File: sb1250_l2c.h
*
* This module contains constants useful for manipulating the
* level 2 cache.
*
* SB1250 specification level: 0.2
*
* Author: Mitch Lichtenberg (mi...@si...)
*
*********************************************************************
*
* Copyright 2000,2001
* Broadcom Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
********************************************************************* */
#ifndef _SB1250_L2C_H
#define _SB1250_L2C_H
#include "sb1250_defs.h"
/*
* Level 2 Cache Tag register (Table 5-3)
*/
#define S_L2C_TAG_MBZ 0
#define M_L2C_TAG_MBZ _SB_MAKEMASK(5,S_L2C_TAG_MBZ)
#define S_L2C_TAG_INDEX 5
#define M_L2C_TAG_INDEX _SB_MAKEMASK(12,S_L2C_TAG_INDEX)
#define V_L2C_TAG_INDEX(x) _SB_MAKEVALUE(x,S_L2C_TAG_INDEX)
#define G_L2C_TAG_INDEX(x) _SB_GETVALUE(x,S_L2C_TAG_INDEX,M_L2C_TAG_INDEX)
#define S_L2C_TAG_TAG 17
#define M_L2C_TAG_TAG _SB_MAKEMASK(23,S_L2C_TAG_TAG)
#define V_L2C_TAG_TAG(x) _SB_MAKEVALUE(x,S_L2C_TAG_TAG)
#define G_L2C_TAG_TAG(x) _SB_GETVALUE(x,S_L2C_TAG_TAG,M_L2C_TAG_TAG)
#define S_L2C_TAG_ECC 40
#define M_L2C_TAG_ECC _SB_MAKEMASK(6,S_L2C_TAG_ECC)
#define V_L2C_TAG_ECC(x) _SB_MAKEVALUE(x,S_L2C_TAG_ECC)
#define G_L2C_TAG_ECC(x) _SB_GETVALUE(x,S_L2C_TAG_ECC,M_L2C_TAG_ECC)
#define S_L2C_TAG_WAY 46
#define M_L2C_TAG_WAY _SB_MAKEMASK(2,S_L2C_TAG_WAY)
#define V_L2C_TAG_WAY(x) _SB_MAKEVALUE(x,S_L2C_TAG_WAY)
#define G_L2C_TAG_WAY(x) _SB_GETVALUE(x,S_L2C_TAG_WAY,M_L2C_TAG_WAY)
#define M_L2C_TAG_DIRTY _SB_MAKEMASK1(48)
#define M_L2C_TAG_VALID _SB_MAKEMASK1(49)
/*
* Format of level 2 cache management address (table 5-2)
*/
#define S_L2C_MGMT_INDEX 5
#define M_L2C_MGMT_INDEX _SB_MAKEMASK(12,S_L2C_MGMT_INDEX)
#define V_L2C_MGMT_INDEX(x) _SB_MAKEVALUE(x,S_L2C_MGMT_INDEX)
#define G_L2C_MGMT_INDEX(x) _SB_GETVALUE(x,S_L2C_MGMT_INDEX,M_L2C_MGMT_INDEX)
#define S_L2C_MGMT_WAY 17
#define M_L2C_MGMT_WAY _SB_MAKEMASK(2,S_L2C_MGMT_WAY)
#define V_L2C_MGMT_WAY(x) _SB_MAKEVALUE(x,S_L2C_MGMT_WAY)
#define G_L2C_MGMT_WAY(x) _SB_GETVALUE(x,S_L2C_MGMT_WAY,M_L2C_MGMT_WAY)
#define S_L2C_MGMT_TAG 21
#define M_L2C_MGMT_TAG _SB_MAKEMASK(6,S_L2C_MGMT_TAG)
#define V_L2C_MGMT_TAG(x) _SB_MAKEVALUE(x,S_L2C_MGMT_TAG)
#define G_L2C_MGMT_TAG(x) _SB_GETVALUE(x,S_L2C_MGMT_TAG,M_L2C_MGMT_TAG)
#define M_L2C_MGMT_DIRTY _SB_MAKEMASK1(19)
#define M_L2C_MGMT_VALID _SB_MAKEMASK1(20)
#define A_L2C_MGMT_TAG_BASE 0x00D0000000
#define L2C_ENTRIES_PER_WAY 4096
#define L2C_NUM_WAYS 4
#endif
--- NEW FILE: sb1250_ldt.h ---
/* *********************************************************************
* SB1250 Board Support Package
*
* LDT constants File: sb1250_ldt.h
*
* This module contains constants and macros to describe
* the LDT interface on the SB1250.
*
* SB1250 specification level: 0.2 plus errata
*
* Author: Mitch Lichtenberg (mi...@si...)
*
*********************************************************************
*
* Copyright 2000,2001
* Broadcom Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
********************************************************************* */
#ifndef _SB1250_LDT_H
#define _SB1250_LDT_H
#include "sb1250_defs.h"
#define K_LDT_VENDOR_SIBYTE 0x166D
#define K_LDT_DEVICE_SB1250 0x0002
/*
* LDT Interface Type 1 (bridge) configuration header
*/
#define R_LDT_TYPE1_DEVICEID 0x0000
#define R_LDT_TYPE1_CMDSTATUS 0x0004
#define R_LDT_TYPE1_CLASSREV 0x0008
#define R_LDT_TYPE1_DEVHDR 0x000C
#define R_LDT_TYPE1_BAR0 0x0010 /* not used */
#define R_LDT_TYPE1_BAR1 0x0014 /* not used */
#define R_LDT_TYPE1_BUSID 0x0018 /* bus ID register */
#define R_LDT_TYPE1_SECSTATUS 0x001C /* secondary status / I/O base/limit */
#define R_LDT_TYPE1_MEMLIMIT 0x0020
#define R_LDT_TYPE1_PREFETCH 0x0024
#define R_LDT_TYPE1_PREF_BASE 0x0028
#define R_LDT_TYPE1_PREF_LIMIT 0x002C
#define R_LDT_TYPE1_IOLIMIT 0x0030
#define R_LDT_TYPE1_CAPPTR 0x0034
#define R_LDT_TYPE1_ROMADDR 0x0038
#define R_LDT_TYPE1_BRCTL 0x003C
#define R_LDT_TYPE1_CMD 0x0040
#define R_LDT_TYPE1_LINKCTRL 0x0044
#define R_LDT_TYPE1_LINKFREQ 0x0048
#define R_LDT_TYPE1_RESERVED1 0x004C
#define R_LDT_TYPE1_SRICMD 0x0050
#define R_LDT_TYPE1_SRITXNUM 0x0054
#define R_LDT_TYPE1_SRIRXNUM 0x0058
#define R_LDT_TYPE1_ERRSTATUS 0x0068
#define R_LDT_TYPE1_SRICTRL 0x006C
#define R_LDT_TYPE1_TXBUFCNT 0x00C8
#define R_LDT_TYPE1_EXPCRC 0x00DC
#define R_LDT_TYPE1_RXCRC 0x00F0
/*
* LDT Device ID register
*/
#define S_LDT_DEVICEID_VENDOR 0
#define M_LDT_DEVICEID_VENDOR _SB_MAKEMASK_32(16,S_LDT_DEVICEID_VENDOR)
#define V_LDT_DEVICEID_VENDOR(x) _SB_MAKEVALUE_32(x,S_LDT_DEVICEID_VENDOR)
#define G_LDT_DEVICEID_VENDOR(x) _SB_GETVALUE_32(x,S_LDT_DEVICEID_VENDOR,M_LDT_DEVICEID_VENDOR)
#define S_LDT_DEVICEID_DEVICEID 16
#define M_LDT_DEVICEID_DEVICEID _SB_MAKEMASK_32(16,S_LDT_DEVICEID_DEVICEID)
#define V_LDT_DEVICEID_DEVICEID(x) _SB_MAKEVALUE_32(x,S_LDT_DEVICEID_DEVICEID)
#define G_LDT_DEVICEID_DEVICEID(x) _SB_GETVALUE_32(x,S_LDT_DEVICEID_DEVICEID,M_LDT_DEVICEID_DEVICEID)
/*
* LDT Command Register (Table 8-13)
*/
#define M_LDT_CMD_IOSPACE_EN _SB_MAKEMASK1_32(0)
#define M_LDT_CMD_MEMSPACE_EN _SB_MAKEMASK1_32(1)
#define M_LDT_CMD_MASTER_EN _SB_MAKEMASK1_32(2)
#define M_LDT_CMD_SPECCYC_EN _SB_MAKEMASK1_32(3)
#define M_LDT_CMD_MEMWRINV_EN _SB_MAKEMASK1_32(4)
#define M_LDT_CMD_VGAPALSNP_EN _SB_MAKEMASK1_32(5)
#define M_LDT_CMD_PARERRRESP _SB_MAKEMASK1_32(6)
#define M_LDT_CMD_WAITCYCCTRL _SB_MAKEMASK1_32(7)
#define M_LDT_CMD_SERR_EN _SB_MAKEMASK1_32(8)
#define M_LDT_CMD_FASTB2B_EN _SB_MAKEMASK1_32(9)
/*
* LDT class and revision registers
*/
#define S_LDT_CLASSREV_REV 0
#define M_LDT_CLASSREV_REV _SB_MAKEMASK_32(8,S_LDT_CLASSREV_REV)
#define V_LDT_CLASSREV_REV(x) _SB_MAKEVALUE_32(x,S_LDT_CLASSREV_REV)
#define G_LDT_CLASSREV_REV(x) _SB_GETVALUE_32(x,S_LDT_CLASSREV_REV,M_LDT_CLASSREV_REV)
#define S_LDT_CLASSREV_CLASS 8
#define M_LDT_CLASSREV_CLASS _SB_MAKEMASK_32(24,S_LDT_CLASSREV_CLASS)
#define V_LDT_CLASSREV_CLASS(x) _SB_MAKEVALUE_32(x,S_LDT_CLASSREV_CLASS)
#define G_LDT_CLASSREV_CLASS(x) _SB_GETVALUE_32(x,S_LDT_CLASSREV_CLASS,M_LDT_CLASSREV_CLASS)
#define K_LDT_REV 0x01
#define K_LDT_CLASS 0x060000
/*
* Device Header (offset 0x0C)
*/
#define S_LDT_DEVHDR_CLINESZ 0
#define M_LDT_DEVHDR_CLINESZ _SB_MAKEMASK_32(8,S_LDT_DEVHDR_CLINESZ)
#define V_LDT_DEVHDR_CLINESZ(x) _SB_MAKEVALUE_32(x,S_LDT_DEVHDR_CLINESZ)
#define G_LDT_DEVHDR_CLINESZ(x) _SB_GETVALUE_32(x,S_LDT_DEVHDR_CLINESZ,M_LDT_DEVHDR_CLINESZ)
#define S_LDT_DEVHDR_LATTMR 8
#define M_LDT_DEVHDR_LATTMR _SB_MAKEMASK_32(8,S_LDT_DEVHDR_LATTMR)
#define V_LDT_DEVHDR_LATTMR(x) _SB_MAKEVALUE_32(x,S_LDT_DEVHDR_LATTMR)
#define G_LDT_DEVHDR_LATTMR(x) _SB_GETVALUE_32(x,S_LDT_DEVHDR_LATTMR,M_LDT_DEVHDR_LATTMR)
#define S_LDT_DEVHDR_HDRTYPE 16
#define M_LDT_DEVHDR_HDRTYPE _SB_MAKEMASK_32(8,S_LDT_DEVHDR_HDRTYPE)
#define V_LDT_DEVHDR_HDRTYPE(x) _SB_MAKEVALUE_32(x,S_LDT_DEVHDR_HDRTYPE)
#define G_LDT_DEVHDR_HDRTYPE(x) _SB_GETVALUE_32(x,S_LDT_DEVHDR_HDRTYPE,M_LDT_DEVHDR_HDRTYPE)
#define K_LDT_DEVHDR_HDRTYPE_TYPE1 1
#define S_LDT_DEVHDR_BIST 24
#define M_LDT_DEVHDR_BIST _SB_MAKEMASK_32(8,S_LDT_DEVHDR_BIST)
#define V_LDT_DEVHDR_BIST(x) _SB_MAKEVALUE_32(x,S_LDT_DEVHDR_BIST)
#define G_LDT_DEVHDR_BIST(x) _SB_GETVALUE_32(x,S_LDT_DEVHDR_BIST,M_LDT_DEVHDR_BIST)
/*
* LDT Status Register (Table 8-14). Note that these constants
* assume you've read the command and status register
* together (32-bit read at offset 0x04)
*
* These bits also apply to the secondary status
* register (Table 8-15), offset 0x1C
*/
#define M_LDT_STATUS_CAPLIST _SB_MAKEMASK1_32(20)
#define M_LDT_STATUS_66MHZCAP _SB_MAKEMASK1_32(21)
#define M_LDT_STATUS_RESERVED2 _SB_MAKEMASK1_32(22)
#define M_LDT_STATUS_FASTB2BCAP _SB_MAKEMASK1_32(23)
#define M_LDT_STATUS_MSTRDPARERR _SB_MAKEMASK1_32(24)
#define S_LDT_STATUS_DEVSELTIMING 25
#define M_LDT_STATUS_DEVSELTIMING _SB_MAKEMASK_32(2,S_LDT_STATUS_DEVSELTIMING)
#define V_LDT_STATUS_DEVSELTIMING(x) _SB_MAKEVALUE_32(x,S_LDT_STATUS_DEVSELTIMING)
#define G_LDT_STATUS_DEVSELTIMING(x) _SB_GETVALUE_32(x,S_LDT_STATUS_DEVSELTIMING,M_LDT_STATUS_DEVSELTIMING)
#define M_LDT_STATUS_SIGDTGTABORT _SB_MAKEMASK1_32(27)
#define M_LDT_STATUS_RCVDTGTABORT _SB_MAKEMASK1_32(28)
#define M_LDT_STATUS_RCVDMSTRABORT _SB_MAKEMASK1_32(29)
#define M_LDT_STATUS_SIGDSERR _SB_MAKEMASK1_32(30)
#define M_LDT_STATUS_DETPARERR _SB_MAKEMASK1_32(31)
/*
* Bridge Control Register (Table 8-16). Note that these
* constants assume you've read the register as a 32-bit
* read (offset 0x3C)
*/
#define M_LDT_BRCTL_PARERRRESP_EN _SB_MAKEMASK1_32(16)
#define M_LDT_BRCTL_SERR_EN _SB_MAKEMASK1_32(17)
#define M_LDT_BRCTL_ISA_EN _SB_MAKEMASK1_32(18)
#define M_LDT_BRCTL_VGA_EN _SB_MAKEMASK1_32(19)
#define M_LDT_BRCTL_MSTRABORTMODE _SB_MAKEMASK1_32(21)
#define M_LDT_BRCTL_SECBUSRESET _SB_MAKEMASK1_32(22)
#define M_LDT_BRCTL_FASTB2B_EN _SB_MAKEMASK1_32(23)
#define M_LDT_BRCTL_PRIDISCARD _SB_MAKEMASK1_32(24)
#define M_LDT_BRCTL_SECDISCARD _SB_MAKEMASK1_32(25)
#define M_LDT_BRCTL_DISCARDSTAT _SB_MAKEMASK1_32(26)
#define M_LDT_BRCTL_DISCARDSERR_EN _SB_MAKEMASK1_32(27)
/*
* LDT Command Register (Table 8-17). Note that these constants
* assume you've read the command and status register together
* 32-bit read at offset 0x40
*/
#define M_LDT_CMD_WARMRESET _SB_MAKEMASK1_32(16)
#define M_LDT_CMD_DOUBLEENDED _SB_MAKEMASK1_32(17)
#define S_LDT_CMD_CAPTYPE 29
#define M_LDT_CMD_CAPTYPE _SB_MAKEMASK_32(3,S_LDT_CMD_CAPTYPE)
#define V_LDT_CMD_CAPTYPE(x) _SB_MAKEVALUE_32(x,S_LDT_CMD_CAPTYPE)
#define G_LDT_CMD_CAPTYPE(x) _SB_GETVALUE_32(x,S_LDT_CMD_CAPTYPE,M_LDT_CMD_CAPTYPE)
/*
* LDT link control register (Table 8-18), and (Table 8-19)
*/
#define M_LDT_LINKCTRL_CAPSYNCFLOOD_EN _SB_MAKEMASK1_32(1)
#define M_LDT_LINKCTRL_CRCSTARTTEST _SB_MAKEMASK1_32(2)
#define M_LDT_LINKCTRL_CRCFORCEERR _SB_MAKEMASK1_32(3)
#define M_LDT_LINKCTRL_LINKFAIL _SB_MAKEMASK1_32(4)
#define M_LDT_LINKCTRL_INITDONE _SB_MAKEMASK1_32(5)
#define M_LDT_LINKCTRL_EOC _SB_MAKEMASK1_32(6)
#define M_LDT_LINKCTRL_XMITOFF _SB_MAKEMASK1_32(7)
#define S_LDT_LINKCTRL_CRCERR 8
#define M_LDT_LINKCTRL_CRCERR _SB_MAKEMASK_32(4,S_LDT_LINKCTRL_CRCERR)
#define V_LDT_LINKCTRL_CRCERR(x) _SB_MAKEVALUE_32(x,S_LDT_LINKCTRL_CRCERR)
#define G_LDT_LINKCTRL_CRCERR(x) _SB_GETVALUE_32(x,S_LDT_LINKCTRL_CRCERR,M_LDT_LINKCTRL_CRCERR)
#define S_LDT_LINKCTRL_MAXIN 16
#define M_LDT_LINKCTRL_MAXIN _SB_MAKEMASK_32(3,S_LDT_LINKCTRL_MAXIN)
#define V_LDT_LINKCTRL_MAXIN(x) _SB_MAKEVALUE_32(x,S_LDT_LINKCTRL_MAXIN)
#define G_LDT_LINKCTRL_MAXIN(x) _SB_GETVALUE_32(x,S_LDT_LINKCTRL_MAXIN,M_LDT_LINKCTRL_MAXIN)
#define M_LDT_LINKCTRL_DWFCLN _SB_MAKEMASK1_32(19)
#define S_LDT_LINKCTRL_MAXOUT 20
#define M_LDT_LINKCTRL_MAXOUT _SB_MAKEMASK_32(3,S_LDT_LINKCTRL_MAXOUT)
#define V_LDT_LINKCTRL_MAXOUT(x) _SB_MAKEVALUE_32(x,S_LDT_LINKCTRL_MAXOUT)
#define G_LDT_LINKCTRL_MAXOUT(x) _SB_GETVALUE_32(x,S_LDT_LINKCTRL_MAXOUT,M_LDT_LINKCTRL_MAXOUT)
#define M_LDT_LINKCTRL_DWFCOUT _SB_MAKEMASK1_32(23)
#define S_LDT_LINKCTRL_WIDTHIN 24
#define M_LDT_LINKCTRL_WIDTHIN _SB_MAKEMASK_32(3,S_LDT_LINKCTRL_WIDTHIN)
#define V_LDT_LINKCTRL_WIDTHIN(x) _SB_MAKEVALUE_32(x,S_LDT_LINKCTRL_WIDTHIN)
#define G_LDT_LINKCTRL_WIDTHIN(x) _SB_GETVALUE_32(x,S_LDT_LINKCTRL_WIDTHIN,M_LDT_LINKCTRL_WIDTHIN)
#define M_LDT_LINKCTRL_DWFCLIN_EN _SB_MAKEMASK1_32(27)
#define S_LDT_LINKCTRL_WIDTHOUT 28
#define M_LDT_LINKCTRL_WIDTHOUT _SB_MAKEMASK_32(3,S_LDT_LINKCTRL_WIDTHOUT)
#define V_LDT_LINKCTRL_WIDTHOUT(x) _SB_MAKEVALUE_32(x,S_LDT_LINKCTRL_WIDTHOUT)
#define G_LDT_LINKCTRL_WIDTHOUT(x) _SB_GETVALUE_32(x,S_LDT_LINKCTRL_WIDTHOUT,M_LDT_LINKCTRL_WIDTHOUT)
#define M_LDT_LINKCTRL_DWFCOUT_EN _SB_MAKEMASK1_32(31)
/*
* LDT Link frequency register (Table 8-20) offset 0x48
*/
#define S_LDT_LINKFREQ_FREQ 8
#define M_LDT_LINKFREQ_FREQ _SB_MAKEMASK_32(4,S_LDT_LINKFREQ_FREQ)
#define V_LDT_LINKFREQ_FREQ(x) _SB_MAKEVALUE_32(x,S_LDT_LINKFREQ_FREQ)
#define G_LDT_LINKFREQ_FREQ(x) _SB_GETVALUE_32(x,S_LDT_LINKFREQ_FREQ,M_LDT_LINKFREQ_FREQ)
#define K_LDT_LINKFREQ_200MHZ 0
#define K_LDT_LINKFREQ_300MHZ 1
#define K_LDT_LINKFREQ_400MHZ 2
#define K_LDT_LINKFREQ_500MHZ 3
#define K_LDT_LINKFREQ_600MHZ 4
#define K_LDT_LINKFREQ_800MHZ 5
#define K_LDT_LINKFREQ_1000MHZ 6
/*
* LDT SRI Command Register (Table 8-21). Note that these constants
* assume you've read the command and status register together
* 32-bit read at offset 0x50
*/
#define M_LDT_SRICMD_SIPREADY _SB_MAKEMASK1_32(16)
#define M_LDT_SRICMD_SYNCPTRCTL _SB_MAKEMASK1_32(17)
#define M_LDT_SRICMD_REDUCESYNCZERO _SB_MAKEMASK1_32(18)
#define M_LDT_SRICMD_DISSTARVATIONCNT _SB_MAKEMASK1_32(19)
#define S_LDT_SRICMD_RXMARGIN 20
#define M_LDT_SRICMD_RXMARGIN _SB_MAKEMASK_32(5,S_LDT_SRICMD_RXMARGIN)
#define V_LDT_SRICMD_RXMARGIN(x) _SB_MAKEVALUE_32(x,S_LDT_SRICMD_RXMARGIN)
#define G_LDT_SRICMD_RXMARGIN(x) _SB_GETVALUE_32(x,S_LDT_SRICMD_RXMARGIN,M_LDT_SRICMD_RXMARGIN)
#define M_LDT_SRICMD_LDTPLLCOMPAT _SB_MAKEMASK1_32(25)
#define S_LDT_SRICMD_TXINITIALOFFSET 28
#define M_LDT_SRICMD_TXINITIALOFFSET _SB_MAKEMASK_32(3,S_LDT_SRICMD_TXINITIALOFFSET)
#define V_LDT_SRICMD_TXINITIALOFFSET(x) _SB_MAKEVALUE_32(x,S_LDT_SRICMD_TXINITIALOFFSET)
#define G_LDT_SRICMD_TXINITIALOFFSET(x) _SB_GETVALUE_32(x,S_LDT_SRICMD_TXINITIALOFFSET,M_LDT_SRICMD_TXINITIALOFFSET)
#define M_LDT_SRICMD_LINKFREQDIRECT _SB_MAKEMASK1_32(31)
/*
* LDT Error control and status register (Table 8-22) (Table 8-23)
*/
#define M_LDT_ERRCTL_PROTFATAL_EN _SB_MAKEMASK1_32(0)
#define M_LDT_ERRCTL_PROTNONFATAL_EN _SB_MAKEMASK1_32(1)
#define M_LDT_ERRCTL_PROTSYNCFLOOD_EN _SB_MAKEMASK1_32(2)
#define M_LDT_ERRCTL_OVFFATAL_EN _SB_MAKEMASK1_32(3)
#define M_LDT_ERRCTL_OVFNONFATAL_EN _SB_MAKEMASK1_32(4)
#define M_LDT_ERRCTL_OVFSYNCFLOOD_EN _SB_MAKEMASK1_32(5)
#define M_LDT_ERRCTL_EOCNXAFATAL_EN _SB_MAKEMASK1_32(6)
#define M_LDT_ERRCTL_EOCNXANONFATAL_EN _SB_MAKEMASK1_32(7)
#define M_LDT_ERRCTL_EOCNXASYNCFLOOD_EN _SB_MAKEMASK1_32(8)
#define M_LDT_ERRCTL_CRCFATAL_EN _SB_MAKEMASK1_32(9)
#define M_LDT_ERRCTL_CRCNONFATAL_EN _SB_MAKEMASK1_32(10)
#define M_LDT_ERRCTL_SERRFATAL_EN _SB_MAKEMASK1_32(11)
#define M_LDT_ERRCTL_SRCTAGFATAL_EN _SB_MAKEMASK1_32(12)
#define M_LDT_ERRCTL_SRCTAGNONFATAL_EN _SB_MAKEMASK1_32(13)
#define M_LDT_ERRCTL_SRCTAGSYNCFLOOD_EN _SB_MAKEMASK1_32(14)
#define M_LDT_ERRCTL_MAPNXAFATAL_EN _SB_MAKEMASK1_32(15)
#define M_LDT_ERRCTL_MAPNXANONFATAL_EN _SB_MAKEMASK1_32(16)
#define M_LDT_ERRCTL_MAPNXASYNCFLOOD_EN _SB_MAKEMASK1_32(17)
#define M_LDT_ERRCTL_PROTOERR _...
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