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[Linux-mips-commits]CVS: linux/arch/mips/kernel Makefile,1.8,1.9 entry.S,1.6,1.7 head.S,1.8,1.9 irq_cpu.c,1.1,1.2 setup.c,1.21,1.22 traps.c,1.19,1.20
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From: Paul M. <le...@us...> - 2001-10-22 19:16:48
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Update of /cvsroot/linux-mips/linux/arch/mips/kernel
In directory usw-pr-cvs1:/tmp/cvs-serv11592/arch/mips/kernel
Modified Files:
Makefile entry.S head.S irq_cpu.c setup.c traps.c
Log Message:
Further syncing with OSS 2.4.10. Massive restructuring of TLB handling.
Index: Makefile
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/kernel/Makefile,v
retrieving revision 1.8
retrieving revision 1.9
diff -u -d -r1.8 -r1.9
--- Makefile 2001/09/27 22:36:33 1.8
+++ Makefile 2001/10/22 19:16:44 1.9
@@ -23,17 +23,22 @@
ipc.o scall_o32.o unaligned.o fast-sysmips.o
obj-$(CONFIG_MODULES) += mips_ksyms.o
-ifdef CONFIG_CPU_R3000
-obj-y += r2300_misc.o r2300_fpu.o r2300_switch.o
-else
-obj-y += r4k_misc.o r4k_switch.o
-ifdef CONFIG_CPU_R6000
-obj-y += r6000_fpu.o
-else
-obj-y += r4k_fpu.o
-endif
-endif
+obj-$(CONFIG_CPU_R3000) += r2300_fpu.o r2300_switch.o
+obj-$(CONFIG_CPU_R4000) += r4k_fpu.o r4k_switch.o
+obj-$(CONFIG_CPU_VR41XX) += r4k_fpu.o r4k_switch.o
+obj-$(CONFIG_CPU_R4300) += r4k_fpu.o r4k_switch.o
+obj-$(CONFIG_CPU_R4X00) += r4k_fpu.o r4k_switch.o
+obj-$(CONFIG_CPU_R5000) += r4k_fpu.o r4k_switch.o
+obj-$(CONFIG_CPU_R5432) += r4k_fpu.o r4k_switch.o
+obj-$(CONFIG_CPU_RM7000) += r4k_fpu.o r4k_switch.o
+obj-$(CONFIG_CPU_NEVADA) += r4k_fpu.o r4k_switch.o
+obj-$(CONFIG_CPU_R10000) += r4k_fpu.o r4k_switch.o
+obj-$(CONFIG_CPU_SB1) += r4k_fpu.o r4k_switch.o
+obj-$(CONFIG_CPU_MIPS32) += r4k_fpu.o r4k_switch.o
+obj-$(CONFIG_CPU_MIPS64) += r4k_fpu.o r4k_switch.o
+obj-$(CONFIG_CPU_R6000) += r6000_fpu.o r4k_switch.o
+export-objs += smp.o
obj-$(CONFIG_SMP) += smp.o
# Old style irq support, going to die in 2.5.
Index: entry.S
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/kernel/entry.S,v
retrieving revision 1.6
retrieving revision 1.7
diff -u -d -r1.6 -r1.7
--- entry.S 2001/10/02 17:18:31 1.6
+++ entry.S 2001/10/22 19:16:44 1.7
@@ -9,10 +9,12 @@
* Copyright (C) 2001 MIPS Technologies, Inc.
*/
#include <linux/config.h>
+#include <linux/init.h>
#include <linux/sys.h>
#include <asm/addrspace.h>
#include <asm/asm.h>
+#include <asm/cacheops.h>
#include <asm/current.h>
#include <asm/errno.h>
#include <asm/mipsregs.h>
@@ -102,6 +104,82 @@
sw t0,%lo(spurious_count)(t1)
j ret_from_irq
END(spurious_interrupt)
+
+ __INIT
+
+ /*
+ * General exception vector. Used for all CPUs except R4000
+ * and R4400 SC and MC versions.
+ */
+ .set reorder
+
+ NESTED(except_vec1_generic, 0, sp)
+ PANIC("Exception vector 1 called")
+ END(except_vec1_generic)
+
+ NESTED(except_vec3_generic, 0, sp)
+ .set mips0
+ mfc0 k1, CP0_CAUSE
+ la k0, exception_handlers
+ andi k1, k1, 0x7c
+ addu k0, k0, k1
+ lw k0, (k0)
+ jr k0
+ END(except_vec3_generic)
+ .set at
+
+ /* General exception vector R4000 version. */
+ NESTED(except_vec3_r4000, 0, sp)
+ .set noat
+ mfc0 k1, CP0_CAUSE
+ andi k1, k1, 0x7c
+ li k0, 31<<2
+ beq k1, k0, handle_vced
+ li k0, 14<<2
+ beq k1, k0, handle_vcei
+ la k0, exception_handlers
+ addu k0, k0, k1
+ lw k0, (k0)
+ nop
+ jr k0
+ nop
+
+ /*
+ * Big shit, we now may have two dirty primary cache lines for
+ * the same physical address. We can savely invalidate the
+ * line pointed to by c0_badvaddr because after return from
+ * this exception handler the load / store will be re-executed.
+ */
+ .set mips3
+handle_vced:
+ mfc0 k0, CP0_BADVADDR
+ li k1, -4
+ and k0, k1
+ mtc0 zero, CP0_TAGLO
+ cache Index_Store_Tag_D,(k0)
+ cache Hit_Writeback_Inv_SD,(k0)
+#ifdef CONFIG_PROC_FS
+ lui k0, %hi(vced_count)
+ lw k1, %lo(vced_count)(k0)
+ addiu k1, 1
+ sw k1, %lo(vced_count)(k0)
+#endif
+ eret
+
+handle_vcei:
+ mfc0 k0, CP0_BADVADDR
+ cache Hit_Writeback_Inv_SD, (k0) # also cleans pi
+#ifdef CONFIG_PROC_FS
+ lui k0, %hi(vcei_count)
+ lw k1, %lo(vcei_count)(k0)
+ addiu k1, 1
+ sw k1, %lo(vcei_count)(k0)
+#endif
+ eret
+
+ END(except_vec3_r4000)
+
+ __FINIT
/*
* Build a default exception handler for the exceptions that don't need
Index: head.S
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/kernel/head.S,v
retrieving revision 1.8
retrieving revision 1.9
diff -u -d -r1.8 -r1.9
--- head.S 2001/10/11 18:19:06 1.8
+++ head.S 2001/10/22 19:16:44 1.9
@@ -1,6 +1,4 @@
/*
- * arch/mips/kernel/head.S
- *
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
@@ -13,21 +11,14 @@
* Further modifications by David S. Miller and Harald Koerfgen
* Copyright (C) 1999 Silicon Graphics, Inc.
*
- * Head.S contains the MIPS exception handler and startup code.
- *
- **************************************************************************
- * 9 Nov, 2000.
- * Added Cache Error exception handler and SBDDP EJTAG debug exception.
- *
* Kevin Kissell, ke...@mi... and Carsten Langgaard, car...@mi...
* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
- **************************************************************************
*/
#include <linux/config.h>
+#include <linux/init.h>
#include <linux/threads.h>
#include <asm/asm.h>
-#include <asm/cacheops.h>
#include <asm/current.h>
#include <asm/offset.h>
#include <asm/processor.h>
@@ -37,320 +28,18 @@
#include <asm/stackframe.h>
#include <asm/bootinfo.h>
+ __INIT
+
.text
/*
* Reserved space for exception handlers.
* Necessary for machines which link their kernels at KSEG0.
- * FIXME: Use the initcode feature to get rid of unused handler
- * variants.
*/
.fill 0x280
-/*
- * This is space for the interrupt handlers.
- * After trap_init() they are located at virtual address KSEG0.
- *
- * These handlers much be written in a relocatable manner
- * because based upon the cpu type an arbitrary one of the
- * following pieces of code will be copied to the KSEG0
- * vector location.
- */
- /* TLB refill, EXL == 0, R4xx0, non-R4600 version */
- .set noreorder
- .set noat
- LEAF(except_vec0_r4000)
- .set mips3
-#ifdef CONFIG_SMP
- mfc0 k1, CP0_CONTEXT
- la k0, pgd_current
- srl k1, 23
- sll k1, 2
- addu k1, k0, k1
- lw k1, (k1)
-#else
- lw k1, pgd_current # get pgd pointer
-#endif
- mfc0 k0, CP0_BADVADDR # Get faulting address
- srl k0, k0, 22 # get pgd only bits
-
- sll k0, k0, 2
- addu k1, k1, k0 # add in pgd offset
- mfc0 k0, CP0_CONTEXT # get context reg
- lw k1, (k1)
-#if defined(CONFIG_CPU_VR41XX)
- srl k0, k0, 3 # get pte offset
-#else
- srl k0, k0, 1 # get pte offset
-#endif
- and k0, k0, 0xff8
- addu k1, k1, k0 # add in offset
- lw k0, 0(k1) # get even pte
- lw k1, 4(k1) # get odd pte
- srl k0, k0, 6 # convert to entrylo0
- mtc0 k0, CP0_ENTRYLO0 # load it
- srl k1, k1, 6 # convert to entrylo1
- mtc0 k1, CP0_ENTRYLO1 # load it
- b 1f
- tlbwr # write random tlb entry
-1:
- nop
- eret # return from trap
- END(except_vec0_r4000)
-
-#ifdef CONFIG_MIPS_AU1000
- /* TLB refill, EXL == 0, Au1000 version */
- /* we'll worry about smp later */
- .set noreorder
- .set noat
- LEAF(except_vec0_au1000)
- .set mips3
- mfc0 k0, CP0_BADVADDR # Get faulting address
- srl k0, k0, 22 # get pgd only bits
- lw k1, pgd_current # get pgd pointer
- sll k0, k0, 2
- addu k1, k1, k0 # add in pgd offset
- mfc0 k0, CP0_CONTEXT # get context reg
- lw k1, (k1)
- srl k0, k0, 1 # get pte offset
- and k0, k0, 0xff8
- addu k1, k1, k0 # add in offset
- j translate_pte
- nop
- END(except_vec0_au1000)
-#endif
-
- /* TLB refill, EXL == 0, R4600 version */
- LEAF(except_vec0_r4600)
- .set mips3
- mfc0 k0, CP0_BADVADDR
- srl k0, k0, 22
- lw k1, pgd_current # get pgd pointer
- sll k0, k0, 2
- addu k1, k1, k0
- mfc0 k0, CP0_CONTEXT
- lw k1, (k1)
- srl k0, k0, 1
- and k0, k0, 0xff8
- addu k1, k1, k0
- lw k0, 0(k1)
- lw k1, 4(k1)
- srl k0, k0, 6
- mtc0 k0, CP0_ENTRYLO0
- srl k1, k1, 6
- mtc0 k1, CP0_ENTRYLO1
- nop
- tlbwr
- nop
- eret
- END(except_vec0_r4600)
-
- /* TLB refill, EXL == 0, R52x0 "Nevada" version */
- /*
- * This version has a bug workaround for the Nevada. It seems
- * as if under certain circumstances the move from cp0_context
- * might produce a bogus result when the mfc0 instruction and
- * it's consumer are in a different cacheline or a load instruction,
- * probably any memory reference, is between them. This is
- * potencially slower than the R4000 version, so we use this
- * special version.
- */
- .set noreorder
- .set noat
- LEAF(except_vec0_nevada)
- .set mips3
- mfc0 k0, CP0_BADVADDR # Get faulting address
- srl k0, k0, 22 # get pgd only bits
- lw k1, pgd_current # get pgd pointer
- sll k0, k0, 2
- addu k1, k1, k0 # add in pgd offset
- lw k1, (k1)
- mfc0 k0, CP0_CONTEXT # get context reg
- srl k0, k0, 1 # get pte offset
- and k0, k0, 0xff8
- addu k1, k1, k0 # add in offset
- lw k0, 0(k1) # get even pte
- lw k1, 4(k1) # get odd pte
- srl k0, k0, 6 # convert to entrylo0
- mtc0 k0, CP0_ENTRYLO0 # load it
- srl k1, k1, 6 # convert to entrylo1
- mtc0 k1, CP0_ENTRYLO1 # load it
- nop # QED specified nops
- nop
- tlbwr # write random tlb entry
- nop # traditional nop
- eret # return from trap
- END(except_vec0_nevada)
-
- /* TLB refill, EXL == 0, R4[40]00/R5000 badvaddr hwbug version */
- LEAF(except_vec0_r45k_bvahwbug)
- .set mips3
- mfc0 k0, CP0_BADVADDR
- srl k0, k0, 22
- lw k1, pgd_current # get pgd pointer
- sll k0, k0, 2
- addu k1, k1, k0
- mfc0 k0, CP0_CONTEXT
- lw k1, (k1)
- srl k0, k0, 1
- and k0, k0, 0xff8
- addu k1, k1, k0
- lw k0, 0(k1)
- lw k1, 4(k1)
- nop /* XXX */
- tlbp
- srl k0, k0, 6
- mtc0 k0, CP0_ENTRYLO0
- srl k1, k1, 6
- mfc0 k0, CP0_INDEX
- mtc0 k1, CP0_ENTRYLO1
- bltzl k0, 1f
- tlbwr
-1:
- nop
- eret
- END(except_vec0_r45k_bvahwbug)
-
-#ifdef CONFIG_SMP
- /* TLB refill, EXL == 0, R4000 MP badvaddr hwbug version */
- LEAF(except_vec0_r4k_mphwbug)
- .set mips3
- mfc0 k0, CP0_BADVADDR
- srl k0, k0, 22
- lw k1, pgd_current # get pgd pointer
- sll k0, k0, 2
- addu k1, k1, k0
- mfc0 k0, CP0_CONTEXT
- lw k1, (k1)
- srl k0, k0, 1
- and k0, k0, 0xff8
- addu k1, k1, k0
- lw k0, 0(k1)
- lw k1, 4(k1)
- nop /* XXX */
- tlbp
- srl k0, k0, 6
- mtc0 k0, CP0_ENTRYLO0
- srl k1, k1, 6
- mfc0 k0, CP0_INDEX
- mtc0 k1, CP0_ENTRYLO1
- bltzl k0, 1f
- tlbwr
-1:
- nop
- eret
- END(except_vec0_r4k_mphwbug)
-#endif
-
- /* TLB refill, EXL == 0, R4000 UP 250MHZ entrylo[01] hwbug version */
- LEAF(except_vec0_r4k_250MHZhwbug)
- .set mips3
- mfc0 k0, CP0_BADVADDR
- srl k0, k0, 22
- lw k1, pgd_current # get pgd pointer
- sll k0, k0, 2
- addu k1, k1, k0
- mfc0 k0, CP0_CONTEXT
- lw k1, (k1)
- srl k0, k0, 1
- and k0, k0, 0xff8
- addu k1, k1, k0
- lw k0, 0(k1)
- lw k1, 4(k1)
- srl k0, k0, 6
- mtc0 zero, CP0_ENTRYLO0
- mtc0 k0, CP0_ENTRYLO0
- srl k1, k1, 6
- mtc0 zero, CP0_ENTRYLO1
- mtc0 k1, CP0_ENTRYLO1
- b 1f
- tlbwr
-1:
- nop
- eret
- END(except_vec0_r4k_250MHZhwbug)
-
-#ifdef CONFIG_SMP
- /* TLB refill, EXL == 0, R4000 MP 250MHZ entrylo[01]+badvaddr bug version */
- LEAF(except_vec0_r4k_MP250MHZhwbug)
- .set mips3
- mfc0 k0, CP0_BADVADDR
- srl k0, k0, 22
- lw k1, pgd_current # get pgd pointer
- sll k0, k0, 2
- addu k1, k1, k0
- mfc0 k0, CP0_CONTEXT
- lw k1, (k1)
- srl k0, k0, 1
- and k0, k0, 0xff8
- addu k1, k1, k0
- lw k0, 0(k1)
- lw k1, 4(k1)
- nop /* XXX */
- tlbp
- srl k0, k0, 6
- mtc0 zero, CP0_ENTRYLO0
- mtc0 k0, CP0_ENTRYLO0
- mfc0 k0, CP0_INDEX
- srl k1, k1, 6
- mtc0 zero, CP0_ENTRYLO1
- mtc0 k1, CP0_ENTRYLO1
- bltzl k0, 1f
- tlbwr
-1:
- nop
- eret
- END(except_vec0_r4k_MP250MHZhwbug)
-#endif
-
- /* TLB refill, R[23]00 version */
- LEAF(except_vec0_r2300)
- .set noat
- .set mips1
- mfc0 k0, CP0_BADVADDR
- lw k1, pgd_current # get pgd pointer
- srl k0, k0, 22
- sll k0, k0, 2
- addu k1, k1, k0
- mfc0 k0, CP0_CONTEXT
- lw k1, (k1)
- and k0, k0, 0xffc
- addu k1, k1, k0
- lw k0, (k1)
- nop
- mtc0 k0, CP0_ENTRYLO0
- mfc0 k1, CP0_EPC
- tlbwr
- jr k1
- rfe
- END(except_vec0_r2300)
-
- /* XTLB refill, EXL == 0, R4xx0 cpus only use this... */
- NESTED(except_vec1_generic, 0, sp)
- .set noat
- .set mips3
- /* Register saving is delayed as long as we don't know
- * which registers really need to be saved.
- */
- mfc0 k1, CP0_CONTEXT
- dsra k1, 1
- lwu k0, (k1) # May cause another exception
- lwu k1, 4(k1)
- dsrl k0, 6 # Convert to EntryLo format
- dsrl k1, 6 # Convert to EntryLo format
- dmtc0 k0, CP0_ENTRYLO0
- dmtc0 k1, CP0_ENTRYLO1
- nop # Needed for R4[04]00 pipeline
- tlbwr
- nop # Needed for R4[04]00 pipeline
- nop
- nop
- eret
- nop /* Workaround for R4000 bug. */
- eret
- END(except_vec1_generic)
-
/* Cache Error */
LEAF(except_vec2_generic)
+ .set noreorder
.set noat
.set mips0
/*
@@ -373,78 +62,14 @@
nop
END(except_vec2_generic)
- /* General exception vector R4000 version. */
- NESTED(except_vec3_r4000, 0, sp)
- .set noat
- mfc0 k1, CP0_CAUSE
- andi k1, k1, 0x7c
- li k0, 31<<2
- beq k1, k0, handle_vced
- li k0, 14<<2
- beq k1, k0, handle_vcei
- la k0, exception_handlers
- addu k0, k0, k1
- lw k0, (k0)
- nop
- jr k0
- nop
-
-/*
- * Big shit, we now may have two dirty primary cache lines for the same
- * physical address. We can savely invalidate the line pointed to by
- * c0_badvaddr because after return from this exception handler the load /
- * store will be re-executed.
- */
- .set mips3
-handle_vced:
- mfc0 k0, CP0_BADVADDR
- li k1, -4
- and k0, k1
- mtc0 zero, CP0_TAGLO
- cache Index_Store_Tag_D,(k0)
- cache Hit_Writeback_Inv_SD,(k0)
-#ifdef CONFIG_PROC_FS
- lui k0, %hi(vced_count)
- lw k1, %lo(vced_count)(k0)
- addiu k1, 1
- sw k1, %lo(vced_count)(k0)
-#endif
- eret
-
-handle_vcei:
- mfc0 k0, CP0_BADVADDR
- cache Hit_Writeback_Inv_SD,(k0) # also cleans pi
-#ifdef CONFIG_PROC_FS
- lui k0, %hi(vcei_count)
- lw k1, %lo(vcei_count)(k0)
- addiu k1, 1
- sw k1, %lo(vcei_count)(k0)
-#endif
- eret
-
- END(except_vec3_r4000)
.set at
- /* General exception vector. */
- NESTED(except_vec3_generic, 0, sp)
- .set noat
- .set mips0
- mfc0 k1, CP0_CAUSE
- la k0, exception_handlers
- andi k1, k1, 0x7c
- addu k0, k0, k1
- lw k0, (k0)
- nop
- jr k0
- nop
- END(except_vec3_generic)
- .set at
-
/*
* Special interrupt vector for embedded MIPS. This is a
* dedicated interrupt vector which reduces interrupt processing
* overhead. The jump instruction will be inserted here at
- * initialization time. This handler may only be 8 bytes in size!
+ * initialization time. This handler may only be 8 bytes in
+ * size!
*/
NESTED(except_vec4, 0, sp)
1: j 1b /* Dummy, will be replaced */
@@ -482,8 +107,7 @@
.set at
END(ejtag_debug_handler)
-
-/*
+ /*
* Kernel entry point
*/
NESTED(kernel_entry, 16, sp)
@@ -679,6 +303,7 @@
__saved_pte: PTR 0
__saved_ra: PTR 0
#endif
+ __FINIT
.comm kernelsp, NR_CPUS * 8, 8
.comm pgd_current, NR_CPUS * 8, 8
@@ -697,9 +322,12 @@
EXPORT(invalid_pte_table)
.org 0x5000
-/* XXX This label is required to keep GAS trying to be too clever ...
- Bug? */
+/*
+ * Odd MIPS as behaviour but no bug - this label is required to keep as from
+ * trying to be too clever ...
+ */
dummy:
+
/*
* Align to 8kb boundary for init_task_union which follows in the
* .text segment.
Index: irq_cpu.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/kernel/irq_cpu.c,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- irq_cpu.c 2001/09/26 23:20:15 1.1
+++ irq_cpu.c 2001/10/22 19:16:44 1.2
@@ -1,15 +1,13 @@
-/***********************************************************************
+/*
* Copyright 2001 MontaVista Software Inc.
* Author: Jun Sun, js...@mv... or js...@ju...
*
- * arch/mips/ddb5xxx/common/irq_cpu.c
* This file define the irq handler for MIPS CPU interrupts.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
- ***********************************************************************
*/
/*
@@ -28,18 +26,11 @@
#include <asm/mipsregs.h>
-/* [jsun] sooner or later we should move this debug stuff to MIPS common */
-#include <asm/ddb5xxx/debug.h>
-
static int mips_cpu_irq_base=-1;
static void
mips_cpu_irq_enable(unsigned int irq)
{
- MIPS_ASSERT(mips_cpu_irq_base != -1);
- MIPS_ASSERT(irq >= mips_cpu_irq_base);
- MIPS_ASSERT(irq < mips_cpu_irq_base+8);
-
clear_cp0_cause( 1 << (irq - mips_cpu_irq_base + 8));
set_cp0_status(1 << (irq - mips_cpu_irq_base + 8));
}
@@ -47,16 +38,13 @@
static void
mips_cpu_irq_disable(unsigned int irq)
{
- MIPS_ASSERT(mips_cpu_irq_base != -1);
- MIPS_ASSERT(irq >= mips_cpu_irq_base);
- MIPS_ASSERT(irq < mips_cpu_irq_base+8);
-
clear_cp0_status(1 << (irq - mips_cpu_irq_base + 8));
}
static unsigned int mips_cpu_irq_startup(unsigned int irq)
{
mips_cpu_irq_enable(irq);
+
return 0;
}
@@ -65,25 +53,19 @@
static void
mips_cpu_irq_ack(unsigned int irq)
{
- MIPS_ASSERT(mips_cpu_irq_base != -1);
- MIPS_ASSERT(irq >= mips_cpu_irq_base);
- MIPS_ASSERT(irq < mips_cpu_irq_base+8);
-
/* although we attemp to clear the IP bit in cause reigster, I think
* usually it is cleared by device (irq source)
*/
- clear_cp0_cause( 1 << (irq - mips_cpu_irq_base + 8));
+ clear_cp0_cause(1 << (irq - mips_cpu_irq_base + 8));
- /* I am not fully convinced that I should disable irq here */
+ /* disable this interrupt - so that we safe proceed to the handler */
+ mips_cpu_irq_disable(irq);
}
static void
mips_cpu_irq_end(unsigned int irq)
{
- MIPS_ASSERT(mips_cpu_irq_base != -1);
- MIPS_ASSERT(irq >= mips_cpu_irq_base);
- MIPS_ASSERT(irq < mips_cpu_irq_base+8);
- /* I am not fully convinced that I should enable irq here */
+ mips_cpu_irq_enable(irq);
}
static hw_irq_controller mips_cpu_irq_controller = {
Index: setup.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/kernel/setup.c,v
retrieving revision 1.21
retrieving revision 1.22
diff -u -d -r1.21 -r1.22
--- setup.c 2001/10/18 18:08:17 1.21
+++ setup.c 2001/10/22 19:16:44 1.22
@@ -188,8 +188,9 @@
else
mips_cpu.cputype = CPU_R4000SC;
mips_cpu.isa_level = MIPS_CPU_ISA_III;
- mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
- MIPS_CPU_WATCH | MIPS_CPU_VCE;
+ mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU |
+ MIPS_CPU_32FPR | MIPS_CPU_WATCH |
+ MIPS_CPU_VCE;
mips_cpu.tlbsize = 48;
break;
case PRID_IMP_VR41XX:
@@ -208,16 +209,20 @@
mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU;
mips_cpu.tlbsize = 48;
break;
-/*
- * This processor doesn't have an MMU, so it's not "real easy" to
- * run Linux on it. It is left purely for documentation.
- * case PRID_IMP_R4650:
+ #if 0
+ case PRID_IMP_R4650:
+ /*
+ * This processor doesn't have an MMU, so it's not
+ * "real easy" to run Linux on it. It is left purely
+ * for documentation. Commented out because it shares
+ * it's c0_prid id number with the TX3900.
+ */
mips_cpu.cputype = CPU_R4650;
mips_cpu.isa_level = MIPS_CPU_ISA_III;
mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU;
mips_cpu.tlbsize = 48;
break;
-*/
+ #endif
case PRID_IMP_TX39:
mips_cpu.isa_level = MIPS_CPU_ISA_I;
mips_cpu.options = MIPS_CPU_TLB;
@@ -243,32 +248,36 @@
case PRID_IMP_R4700:
mips_cpu.cputype = CPU_R4700;
mips_cpu.isa_level = MIPS_CPU_ISA_III;
- mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR;
+ mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU |
+ MIPS_CPU_32FPR;
mips_cpu.tlbsize = 48;
break;
case PRID_IMP_R5000:
mips_cpu.cputype = CPU_R5000;
mips_cpu.isa_level = MIPS_CPU_ISA_IV;
- mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR;
+ mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU |
+ MIPS_CPU_32FPR;
mips_cpu.tlbsize = 48;
break;
case PRID_IMP_R5432:
mips_cpu.cputype = CPU_R5432;
mips_cpu.isa_level = MIPS_CPU_ISA_IV;
- mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR;
+ mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU |
+ MIPS_CPU_32FPR;
mips_cpu.tlbsize = 48;
break;
case PRID_IMP_R5500:
mips_cpu.cputype = CPU_R5500;
mips_cpu.isa_level = MIPS_CPU_ISA_IV;
- mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR;
+ mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU |
+ MIPS_CPU_32FPR;
mips_cpu.tlbsize = 48;
break;
case PRID_IMP_NEVADA:
mips_cpu.cputype = CPU_NEVADA;
mips_cpu.isa_level = MIPS_CPU_ISA_IV;
- mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
- MIPS_CPU_DIVEC;
+ mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU |
+ MIPS_CPU_32FPR | MIPS_CPU_DIVEC;
mips_cpu.tlbsize = 48;
mips_cpu.icache.ways = 2;
mips_cpu.dcache.ways = 2;
@@ -297,7 +306,17 @@
case PRID_IMP_RM7000:
mips_cpu.cputype = CPU_RM7000;
mips_cpu.isa_level = MIPS_CPU_ISA_IV;
- mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR;
+ mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU |
+ MIPS_CPU_32FPR;
+ /*
+ * Undocumented RM7000: Bit 29 in the info register of
+ * the RM7000 v2.0 indicates if the TLB has 48 or 64
+ * entries.
+ *
+ * 29 1 => 64 entry JTLB
+ * 0 => 48 entry JTLB
+ */
+ mips_cpu.tlbsize = (get_info() & (1 << 29)) ? 64 : 48;
break;
case PRID_IMP_R8000:
mips_cpu.cputype = CPU_R8000;
Index: traps.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/kernel/traps.c,v
retrieving revision 1.19
retrieving revision 1.20
diff -u -d -r1.19 -r1.20
--- traps.c 2001/10/09 21:37:55 1.19
+++ traps.c 2001/10/22 19:16:44 1.20
@@ -794,8 +794,6 @@
void __init trap_init(void)
{
- extern char except_vec0_nevada, except_vec0_r4000;
- extern char except_vec0_r4600, except_vec0_r2300;
extern char except_vec1_generic, except_vec2_generic;
extern char except_vec3_generic, except_vec3_r4000;
extern char except_vec4;
@@ -874,13 +872,6 @@
*/
if ((mips_cpu.options & MIPS_CPU_4KEX)
&& (mips_cpu.options & MIPS_CPU_4KTLB)) {
- if (mips_cpu.cputype == CPU_NEVADA) {
- memcpy((void *)KSEG0, &except_vec0_nevada, 0x80);
- } else if (mips_cpu.cputype == CPU_R4600)
- memcpy((void *)KSEG0, &except_vec0_r4600, 0x80);
- else
- memcpy((void *)KSEG0, &except_vec0_r4000, 0x80);
-
/* Cache error vector already set above. */
if (mips_cpu.options & MIPS_CPU_VCE) {
@@ -904,7 +895,6 @@
* XXX - This should be folded in to the "cleaner" handling,
* above
*/
- memcpy((void *)KSEG0, &except_vec0_r4000, 0x80);
memcpy((void *)(KSEG0 + 0x180), &except_vec3_r4000, 0x80);
save_fp_context = _save_fp_context;
restore_fp_context = _restore_fp_context;
@@ -941,7 +931,6 @@
case CPU_TX3927:
save_fp_context = _save_fp_context;
restore_fp_context = _restore_fp_context;
- memcpy((void *)KSEG0, &except_vec0_r2300, 0x80);
memcpy((void *)(KSEG0 + 0x80), &except_vec3_generic, 0x80);
break;
|
