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[Linux-mips-commits]CVS: linux/arch/mips/ddb5xxx/ddb5476 irq.c,1.1,1.2 pci.c,1.1,1.2 pci_ops.c,1.1,1.2 setup.c,1.1,1.2 vrc5476_irq.c,1.1,1.2
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From: James S. <jsi...@us...> - 2001-10-11 20:45:29
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Update of /cvsroot/linux-mips/linux/arch/mips/ddb5xxx/ddb5476
In directory usw-pr-cvs1:/tmp/cvs-serv14020/arch/mips/ddb5xxx/ddb5476
Modified Files:
irq.c pci.c pci_ops.c setup.c vrc5476_irq.c
Log Message:
Update debug crapola.
Index: irq.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/ddb5xxx/ddb5476/irq.c,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- irq.c 2001/10/07 05:40:22 1.1
+++ irq.c 2001/10/11 20:45:26 1.2
@@ -3,6 +3,11 @@
*
* Copyright (C) 2000 Geert Uytterhoeven <ge...@so...>
* Sony Software Development Center Europe (SDCE), Brussels
+ *
+ * Re-write the whole thing to use new irq.c file.
+ * Copyright (C) 2001 MontaVista Software Inc.
+ * Author: Jun Sun, js...@mv... or js...@ju...
+ *
*/
#include <linux/config.h>
#include <linux/init.h>
Index: pci.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/ddb5xxx/ddb5476/pci.c,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- pci.c 2001/10/07 05:40:22 1.1
+++ pci.c 2001/10/11 20:45:26 1.2
@@ -4,9 +4,9 @@
#include <linux/pci.h>
#include <asm/pci_channel.h>
+#include <asm/debug.h>
#include <asm/ddb5xxx/ddb5xxx.h>
-#include <asm/ddb5xxx/debug.h>
static struct resource extpci_io_resource = {
"pci IO space",
@@ -81,8 +81,8 @@
pci_for_each_dev(dev) {
slot_num = PCI_SLOT(dev->devfn);
- MIPS_ASSERT(slot_num < MAX_SLOT_NUM);
- MIPS_ASSERT(irq_map[slot_num] != 0xff);
+ db_assert(slot_num < MAX_SLOT_NUM);
+ db_assert(irq_map[slot_num] != 0xff);
pci_write_config_byte(dev,
PCI_INTERRUPT_LINE,
@@ -91,7 +91,7 @@
}
}
-#if defined(CONFIG_LL_DEBUG)
+#if defined(CONFIG_DEBUG)
extern void jsun_scan_pci_bus(void);
#endif
Index: pci_ops.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/ddb5xxx/ddb5476/pci_ops.c,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- pci_ops.c 2001/10/07 05:40:22 1.1
+++ pci_ops.c 2001/10/11 20:45:26 1.2
@@ -2,7 +2,7 @@
* Copyright 2001 MontaVista Software Inc.
* Author: Jun Sun, js...@mv... or js...@ju...
*
- * arch/mips/ddb5xxx/ddb5477/pci_ops.c
+ * arch/mips/ddb5xxx/ddb5476/pci_ops.c
* Define the pci_ops for DB5477.
*
* Much of the code is derived from the original DDB5074 port by
@@ -21,8 +21,8 @@
#include <linux/types.h>
#include <asm/addrspace.h>
+#include <asm/debug.h>
-#include <asm/ddb5xxx/debug.h>
#include <asm/ddb5xxx/ddb5xxx.h>
/*
@@ -74,10 +74,10 @@
}
/* minimum pdar (window) size is 2MB */
- MIPS_ASSERT(swap->config_size >= (2 << 20));
+ db_assert(swap->config_size >= (2 << 20));
- MIPS_ASSERT(slot_num < (1 << 5));
- MIPS_ASSERT(bus < (1 << 8));
+ db_assert(slot_num < (1 << 5));
+ db_assert(bus < (1 << 8));
/* backup registers */
swap->pdar_backup = ddb_in32(swap->pdar);
@@ -113,7 +113,7 @@
virt_addr = KSEG1ADDR(swap->config_base + pci_addr);
pciinit_offset = 0;
} else {
- MIPS_ASSERT( (pci_addr & (swap->config_size - 1)) == 0);
+ db_assert( (pci_addr & (swap->config_size - 1)) == 0);
virt_addr = KSEG1ADDR(swap->config_base);
pciinit_offset = pci_addr;
}
@@ -140,13 +140,13 @@
u32 bus, slot_num, func_num;
u32 base;
- MIPS_ASSERT((where & 3) == 0);
- MIPS_ASSERT(where < (1 << 8));
+ db_assert((where & 3) == 0);
+ db_assert(where < (1 << 8));
/* check if the bus is top-level */
if (dev->bus->parent != NULL) {
bus = dev->bus->number;
- MIPS_ASSERT(bus != 0);
+ db_assert(bus != 0);
} else {
bus = 0;
}
@@ -167,7 +167,7 @@
int status;
u32 result;
- MIPS_ASSERT((where & 1) == 0);
+ db_assert((where & 1) == 0);
status = read_config_dword(swap, dev, where & ~3, &result);
if (where & 2) result >>= 16;
@@ -198,13 +198,13 @@
u32 bus, slot_num, func_num;
u32 base;
- MIPS_ASSERT((where & 3) == 0);
- MIPS_ASSERT(where < (1 << 8));
+ db_assert((where & 3) == 0);
+ db_assert(where < (1 << 8));
/* check if the bus is top-level */
if (dev->bus->parent != NULL) {
bus = dev->bus->number;
- MIPS_ASSERT(bus != 0);
+ db_assert(bus != 0);
} else {
bus = 0;
}
@@ -225,7 +225,7 @@
int status, shift=0;
u32 result;
- MIPS_ASSERT((where & 1) == 0);
+ db_assert((where & 1) == 0);
status = read_config_dword(swap, dev, where & ~3, &result);
if (status != PCIBIOS_SUCCESSFUL) return status;
@@ -284,7 +284,7 @@
};
-#if defined(CONFIG_LL_DEBUG)
+#if defined(CONFIG_DEBUG)
void jsun_scan_pci_bus(void)
{
struct pci_bus bus;
@@ -310,7 +310,7 @@
int i;
dev.devfn = devfn;
- MIPS_VERIFY(pci_read_config_dword(&dev, 0, &temp),
+ db_verify(pci_read_config_dword(&dev, 0, &temp),
== PCIBIOS_SUCCESSFUL);
if (temp == 0xffffffff) continue;
@@ -318,21 +318,21 @@
11+devfn/8);
/* verify read word and byte */
- MIPS_VERIFY(pci_read_config_word(&dev, 2, &temp16),
- == PCIBIOS_SUCCESSFUL);
- MIPS_ASSERT(temp16 == (temp >> 16));
- MIPS_VERIFY(pci_read_config_byte(&dev, 3, &temp8),
- == PCIBIOS_SUCCESSFUL);
- MIPS_ASSERT(temp8 == (temp >> 24));
- MIPS_VERIFY(pci_read_config_byte(&dev, 1, &temp8),
- == PCIBIOS_SUCCESSFUL);
- MIPS_ASSERT(temp8 == ((temp >> 8) & 0xff));
+ db_verify(pci_read_config_word(&dev, 2, &temp16),
+ == PCIBIOS_SUCCESSFUL);
+ db_assert(temp16 == (temp >> 16));
+ db_verify(pci_read_config_byte(&dev, 3, &temp8),
+ == PCIBIOS_SUCCESSFUL);
+ db_assert(temp8 == (temp >> 24));
+ db_verify(pci_read_config_byte(&dev, 1, &temp8),
+ == PCIBIOS_SUCCESSFUL);
+ db_assert(temp8 == ((temp >> 8) & 0xff));
for (i=0; i < 16; i++) {
if ((i%4) == 0)
printk(KERN_INFO);
- MIPS_VERIFY(pci_read_config_dword(&dev, i*4, &temp),
- == PCIBIOS_SUCCESSFUL);
+ db_verify(pci_read_config_dword(&dev, i*4, &temp),
+ == PCIBIOS_SUCCESSFUL);
printk("\t%08X", temp);
if ((i%4) == 3)
printk("\n");
Index: setup.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/ddb5xxx/ddb5476/setup.c,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- setup.c 2001/10/07 05:40:22 1.1
+++ setup.c 2001/10/11 20:45:26 1.2
@@ -24,6 +24,7 @@
#include <asm/reboot.h>
#include <asm/gdb-stub.h>
#include <asm/time.h>
+#include <asm/debug.h>
#include <asm/ddb5xxx/ddb5xxx.h>
@@ -189,11 +190,11 @@
{
/* ----------- setup PDARs ------------ */
/* check SDRAM0, whether we are on MEM bus does not matter */
- MIPS_ASSERT((ddb_in32(DDB_SDRAM0) & 0xffffffef) ==
- ddb_calc_pdar(DDB_SDRAM_BASE, DDB_SDRAM_SIZE, 32, 0, 1));
+ db_assert((ddb_in32(DDB_SDRAM0) & 0xffffffef) ==
+ ddb_calc_pdar(DDB_SDRAM_BASE, DDB_SDRAM_SIZE, 32, 0, 1));
/* SDRAM1 should be turned off. What is this for anyway ? */
- MIPS_ASSERT( (ddb_in32(DDB_SDRAM1) & 0xf) == 0);
+ db_assert( (ddb_in32(DDB_SDRAM1) & 0xf) == 0);
/* flash 1&2, DDB status, DDB control */
ddb_set_pdar(DDB_DCS2, DDB_DCS2_BASE, DDB_DCS2_SIZE, 16, 0, 0);
@@ -208,13 +209,13 @@
/* verify VRC5477 base addr */
/* don't care about some details */
- MIPS_ASSERT((ddb_in32(DDB_INTCS) & 0xffffff0f) ==
- ddb_calc_pdar(DDB_INTCS_BASE, DDB_INTCS_SIZE, 8, 0, 0));
+ db_assert((ddb_in32(DDB_INTCS) & 0xffffff0f) ==
+ ddb_calc_pdar(DDB_INTCS_BASE, DDB_INTCS_SIZE, 8, 0, 0));
/* verify BOOT ROM addr */
/* don't care about some details */
- MIPS_ASSERT((ddb_in32(DDB_BOOTCS) & 0xffffff0f) ==
- ddb_calc_pdar(DDB_BOOTCS_BASE, DDB_BOOTCS_SIZE, 8, 0, 0));
+ db_assert((ddb_in32(DDB_BOOTCS) & 0xffffff0f) ==
+ ddb_calc_pdar(DDB_BOOTCS_BASE, DDB_BOOTCS_SIZE, 8, 0, 0));
/* setup PCI windows - window1 for MEM/config, window0 for IO */
ddb_set_pdar(DDB_PCIW0, DDB_PCI_IO_BASE, DDB_PCI_IO_SIZE, 32, 0, 1);
Index: vrc5476_irq.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/ddb5xxx/ddb5476/vrc5476_irq.c,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- vrc5476_irq.c 2001/10/07 05:40:22 1.1
+++ vrc5476_irq.c 2001/10/11 20:45:26 1.2
@@ -18,7 +18,6 @@
#include <asm/system.h>
#include <asm/ddb5xxx/ddb5xxx.h>
-#include <asm/ddb5xxx/debug.h>
static int irq_base;
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