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[Linux-mips-commits]CVS: linux/arch/mips/kernel smp.c,1.2,1.3 head.S,1.6,1.7 r2300_misc.S,1.1,1.2 r4k_misc.S,1.4,1.5 setup.c,1.17,1.18 traps.c,1.18,1.19
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From: James S. <jsi...@us...> - 2001-10-09 21:38:01
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Update of /cvsroot/linux-mips/linux/arch/mips/kernel
In directory usw-pr-cvs1:/tmp/cvs-serv11842
Modified Files:
head.S r2300_misc.S r4k_misc.S setup.c traps.c
Added Files:
smp.c
Log Message:
Consolidate TLB context switching code. This also fixes a bunch very obscure bugs in the 32-bit code which probably didn't bite anybody yet.
Index: head.S
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/kernel/head.S,v
retrieving revision 1.6
retrieving revision 1.7
diff -u -d -r1.6 -r1.7
--- head.S 2001/08/22 05:31:27 1.6
+++ head.S 2001/10/09 21:37:55 1.7
@@ -61,13 +61,13 @@
.set mips3
#ifdef CONFIG_SMP
mfc0 k1, CP0_CONTEXT
- la k0, current_pgd
+ la k0, pgd_current
srl k1, 23
sll k1, 2
addu k1, k0, k1
lw k1, (k1)
#else
- lw k1, current_pgd # get pgd pointer
+ lw k1, pgd_current # get pgd pointer
#endif
mfc0 k0, CP0_BADVADDR # Get faulting address
srl k0, k0, 22 # get pgd only bits
@@ -123,7 +123,7 @@
.set mips3
mfc0 k0, CP0_BADVADDR
srl k0, k0, 22
- lw k1, current_pgd # get pgd pointer
+ lw k1, pgd_current # get pgd pointer
sll k0, k0, 2
addu k1, k1, k0
mfc0 k0, CP0_CONTEXT
@@ -159,7 +159,7 @@
.set mips3
mfc0 k0, CP0_BADVADDR # Get faulting address
srl k0, k0, 22 # get pgd only bits
- lw k1, current_pgd # get pgd pointer
+ lw k1, pgd_current # get pgd pointer
sll k0, k0, 2
addu k1, k1, k0 # add in pgd offset
lw k1, (k1)
@@ -185,7 +185,7 @@
.set mips3
mfc0 k0, CP0_BADVADDR
srl k0, k0, 22
- lw k1, current_pgd # get pgd pointer
+ lw k1, pgd_current # get pgd pointer
sll k0, k0, 2
addu k1, k1, k0
mfc0 k0, CP0_CONTEXT
@@ -215,7 +215,7 @@
.set mips3
mfc0 k0, CP0_BADVADDR
srl k0, k0, 22
- lw k1, current_pgd # get pgd pointer
+ lw k1, pgd_current # get pgd pointer
sll k0, k0, 2
addu k1, k1, k0
mfc0 k0, CP0_CONTEXT
@@ -245,7 +245,7 @@
.set mips3
mfc0 k0, CP0_BADVADDR
srl k0, k0, 22
- lw k1, current_pgd # get pgd pointer
+ lw k1, pgd_current # get pgd pointer
sll k0, k0, 2
addu k1, k1, k0
mfc0 k0, CP0_CONTEXT
@@ -274,7 +274,7 @@
.set mips3
mfc0 k0, CP0_BADVADDR
srl k0, k0, 22
- lw k1, current_pgd # get pgd pointer
+ lw k1, pgd_current # get pgd pointer
sll k0, k0, 2
addu k1, k1, k0
mfc0 k0, CP0_CONTEXT
@@ -306,7 +306,7 @@
.set noat
.set mips1
mfc0 k0, CP0_BADVADDR
- lw k1, current_pgd # get pgd pointer
+ lw k1, pgd_current # get pgd pointer
srl k0, k0, 22
sll k0, k0, 2
addu k1, k1, k0
@@ -680,18 +680,9 @@
__saved_ra: PTR 0
#endif
-#ifndef CONFIG_SMP
-EXPORT(kernelsp)
- PTR 0
-EXPORT(current_pgd)
- PTR 0
-#else
- /* There's almost certainly a better way to do this with the macros...*/
- .globl kernelsp
- .comm kernelsp, NR_CPUS * 8, 8
- .globl current_pgd
- .comm current_pgd, NR_CPUS * 8, 8
-#endif
+ .comm kernelsp, NR_CPUS * 8, 8
+ .comm pgd_current, NR_CPUS * 8, 8
+
.text
.org 0x1000
EXPORT(swapper_pg_dir)
Index: r2300_misc.S
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/kernel/r2300_misc.S,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- r2300_misc.S 2001/09/06 16:12:01 1.1
+++ r2300_misc.S 2001/10/09 21:37:55 1.2
@@ -39,7 +39,7 @@
*/
#define LOAD_PTE(pte, ptr) \
mfc0 pte, CP0_BADVADDR; \
- lw ptr, current_pgd; \
+ lw ptr, pgd_current; \
srl pte, pte, 22; \
sll pte, pte, 2; \
addu ptr, ptr, pte; \
Index: r4k_misc.S
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/kernel/r4k_misc.S,v
retrieving revision 1.4
retrieving revision 1.5
diff -u -d -r1.4 -r1.5
--- r4k_misc.S 2001/09/06 16:12:59 1.4
+++ r4k_misc.S 2001/10/09 21:37:55 1.5
@@ -38,14 +38,14 @@
#ifdef CONFIG_SMP
#define GET_PGD(scratch, ptr) \
mfc0 ptr, CP0_CONTEXT; \
- la scratch, current_pgd;\
+ la scratch, pgd_current;\
srl ptr, 23; \
sll ptr, 2; \
addu ptr, scratch, ptr; \
lw ptr, (ptr);
#else
#define GET_PGD(scratch, ptr) \
- lw ptr, current_pgd;
+ lw ptr, pgd_current;
#endif
Index: setup.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/kernel/setup.c,v
retrieving revision 1.17
retrieving revision 1.18
diff -u -d -r1.17 -r1.18
--- setup.c 2001/10/02 18:35:48 1.17
+++ setup.c 2001/10/09 21:37:55 1.18
@@ -41,8 +41,9 @@
#include <asm/sgialib.h>
#endif
-
-struct mips_cpuinfo boot_cpu_data = { 0, NULL, NULL, 0 };
+#ifndef CONFIG_SMP
+struct cpuinfo_mips cpu_data[1];
+#endif
/*
* Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
Index: traps.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/kernel/traps.c,v
retrieving revision 1.18
retrieving revision 1.19
diff -u -d -r1.18 -r1.19
--- traps.c 2001/09/27 17:27:49 1.18
+++ traps.c 2001/10/09 21:37:55 1.19
@@ -917,7 +917,7 @@
case CPU_R6000A:
save_fp_context = _save_fp_context;
restore_fp_context = _restore_fp_context;
-
+
/*
* The R6000 is the only R-series CPU that features a machine
* check exception (similar to the R4000 cache error) and
@@ -956,6 +956,8 @@
atomic_inc(&init_mm.mm_count); /* XXX UP? */
current->active_mm = &init_mm;
- write_32bit_cp0_register(CP0_CONTEXT, smp_processor_id()<<23);
- current_pgd[0] = init_mm.pgd;
+
+ /* XXX Must be done for all CPUs */
+ current_cpu_data.asid_cache = ASID_FIRST_VERSION;
+ TLBMISS_HANDLER_SETUP();
}
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