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[Linux-mips-commits]CVS: linux/arch/mips/mm pg-r4xx0.S,NONE,1.1 Makefile,1.3,1.4 andes.c,1.3,1.4 mips32.c,1.3,1.4 r2300.c,1.3,1.4 r4xx0.c,1.6,1.7 r5432.c,1.2,1.3
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From: James S. <jsi...@us...> - 2001-10-08 16:29:36
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Update of /cvsroot/linux-mips/linux/arch/mips/mm
In directory usw-pr-cvs1:/tmp/cvs-serv31620
Modified Files:
Makefile andes.c mips32.c r2300.c r4xx0.c r5432.c
Added Files:
pg-r4xx0.S
Log Message:
Move all clear_page / copy_page variations in separate files. Rewrite all R4xx0 variants to assembler code.
--- NEW FILE: pg-r4xx0.S ---
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* r4xx0.c: R4000 processor variant specific MMU/Cache routines.
*
* Copyright (C) 1996 David S. Miller (dm...@en...)
* Copyright (C) 1997, 1998, 1999, 2000 Ralf Baechle ra...@gn...
*/
#include <asm/addrspace.h>
#include <asm/asm.h>
#include <asm/regdef.h>
#include <asm/cacheops.h>
#include <asm/mipsregs.h>
#define PAGE_SIZE 0x1000
.text
.set mips3
.set noreorder
.set nomacro
.set noat
/*
* Zero an entire page. Basically a simple unrolled loop should do the
* job but we want more performance by saving memory bus bandwidth. We
* have five flavours of the routine available for:
*
* - 16byte cachelines and no second level cache
* - 32byte cachelines second level cache
* - a version which handles the buggy R4600 v1.x
* - a version which handles the buggy R4600 v2.0
* - Finally a last version without fancy cache games for the SC and MC
* versions of R4000 and R4400.
*/
LEAF(r4k_clear_page_d16)
addiu AT, a0, PAGE_SIZE
1: cache Create_Dirty_Excl_D, (a0)
sd zero, (a0)
sd zero, 8(a0)
cache Create_Dirty_Excl_D, 16(a0)
sd zero, 16(a0)
sd zero, 24(a0)
addiu a0, 64
cache Create_Dirty_Excl_D, -32(a0)
sd zero, -32(a0)
sd zero, -24(a0)
cache Create_Dirty_Excl_D, -16(a0)
sd zero, -16(a0)
bne AT, a0, 1b
sd zero, -8(a0)
jr ra
END(r4k_clear_page_d16)
LEAF(r4k_clear_page_d32)
addiu AT, a0, PAGE_SIZE
1: cache Create_Dirty_Excl_D, (a0)
sd zero, (a0)
sd zero, 8(a0)
sd zero, 16(a0)
sd zero, 24(a0)
addiu a0, 64
cache Create_Dirty_Excl_D, -32(a0)
sd zero, -32(a0)
sd zero, -24(a0)
sd zero, -16(a0)
bne AT, a0, 1b
sd zero, -8(a0)
jr ra
END(r4k_clear_page_d32)
/*
* This flavour of r4k_clear_page is for the R4600 V1.x. Cite from the
* IDT R4600 V1.7 errata:
*
* 18. The CACHE instructions Hit_Writeback_Invalidate_D, Hit_Writeback_D,
* Hit_Invalidate_D and Create_Dirty_Excl_D should only be
* executed if there is no other dcache activity. If the dcache is
* accessed for another instruction immeidately preceding when these
* cache instructions are executing, it is possible that the dcache
* tag match outputs used by these cache instructions will be
* incorrect. These cache instructions should be preceded by at least
* four instructions that are not any kind of load or store
* instruction.
*
* This is not allowed: lw
* nop
* nop
* nop
* cache Hit_Writeback_Invalidate_D
*
* This is allowed: lw
* nop
* nop
* nop
* nop
* cache Hit_Writeback_Invalidate_D
*/
LEAF(r4k_clear_page_r4600_v1)
addiu AT, a0, PAGE_SIZE
1: nop
nop
nop
nop
cache Create_Dirty_Excl_D, (a0)
sd zero, (a0)
sd zero, 8(a0)
sd zero, 16(a0)
sd zero, 24(a0)
addiu a0, 64
nop
nop
nop
cache Create_Dirty_Excl_D, -32(a0)
sd zero, -32(a0)
sd zero, -24(a0)
sd zero, -16(a0)
bne AT, a0, 1b
sd zero, -8(a0)
jr ra
END(r4k_clear_page_r4600_v1)
LEAF(r4k_clear_page_r4600_v2)
mfc0 a1, CP0_STATUS
ori AT, a1, 1
xori AT, 1
mtc0 AT, CP0_STATUS
nop
nop
nop
.set volatile
la AT, KSEG1
lw zero, (AT)
.set novolatile
addiu AT, a0, PAGE_SIZE
1: cache Create_Dirty_Excl_D, (a0)
sd zero, (a0)
sd zero, 8(a0)
sd zero, 16(a0)
sd zero, 24(a0)
addiu a0, 64
cache Create_Dirty_Excl_D, -32(a0)
sd zero, -32(a0)
sd zero, -24(a0)
sd zero, -16(a0)
bne AT, a0, 1b
sd zero, -8(a0)
mfc0 AT, CP0_STATUS # __restore_flags
andi a1, 1
ori AT, 1
xori AT, 1
or a1, AT
mtc0 a1, CP0_STATUS
nop
nop
nop
jr ra
END(r4k_clear_page_r4600_v2)
/*
* The next 4 versions are optimized for all possible scache configurations
* of the SC / MC versions of R4000 and R4400 ...
*
* Todo: For even better performance we should have a routine optimized for
* every legal combination of dcache / scache linesize. When I (Ralf) tried
* this the kernel crashed shortly after mounting the root filesystem. CPU
* bug? Weirdo cache instruction semantics?
*/
LEAF(r4k_clear_page_s16)
addiu AT, a0, PAGE_SIZE
1: cache Create_Dirty_Excl_SD, (a0)
sd zero, (a0)
sd zero, 8(a0)
cache Create_Dirty_Excl_SD, 16(a0)
sd zero, 16(a0)
sd zero, 24(a0)
addiu a0, 64
cache Create_Dirty_Excl_SD, -32(a0)
sd zero, -32(a0)
sd zero, -24(a0)
cache Create_Dirty_Excl_SD, -16(a0)
sd zero, -16(a0)
bne AT, a0, 1b
sd zero, -8(a0)
jr ra
END(r4k_clear_page_s16)
LEAF(r4k_clear_page_s32)
addiu AT, a0, PAGE_SIZE
1: cache Create_Dirty_Excl_SD, (a0)
sd zero, (a0)
sd zero, 8(a0)
sd zero, 16(a0)
sd zero, 24(a0)
addiu a0, 64
cache Create_Dirty_Excl_SD, -32(a0)
sd zero, -32(a0)
sd zero, -24(a0)
sd zero, -16(a0)
bne AT, a0, 1b
sd zero, -8(a0)
jr ra
END(r4k_clear_page_s32)
LEAF(r4k_clear_page_s64)
addiu AT, a0, PAGE_SIZE
1: cache Create_Dirty_Excl_SD, (a0)
sd zero, (a0)
sd zero, 8(a0)
sd zero, 16(a0)
sd zero, 24(a0)
addiu a0, 64
sd zero, -32(a0)
sd zero, -24(a0)
sd zero, -16(a0)
bne AT, a0, 1b
sd zero, -8(a0)
jr ra
END(r4k_clear_page_s64)
LEAF(r4k_clear_page_s128)
addiu AT, a0, PAGE_SIZE
1: cache Create_Dirty_Excl_SD, (a0)
sd zero, (a0)
sd zero, 8(a0)
sd zero, 16(a0)
sd zero, 24(a0)
sd zero, 32(a0)
sd zero, 40(a0)
sd zero, 48(a0)
sd zero, 56(a0)
addiu a0, 128
sd zero, -64(a0)
sd zero, -56(a0)
sd zero, -48(a0)
sd zero, -40(a0)
sd zero, -32(a0)
sd zero, -24(a0)
sd zero, -16(a0)
bne AT, a0, 1b
sd zero, -8(a0)
jr ra
END(r4k_clear_page_s128)
/*
* This is still inefficient. We only can do better if we know the
* virtual address where the copy will be accessed.
*/
LEAF(r4k_copy_page_d16)
addiu AT, a0, PAGE_SIZE
1: cache Create_Dirty_Excl_D, (a0)
lw a3, (a1)
lw a2, 4(a1)
lw v1, 8(a1)
lw v0, 12(a1)
sw a3, (a0)
sw a2, 4(a0)
sw v1, 8(a0)
sw v0, 12(a0)
cache Create_Dirty_Excl_D, 16(a0)
lw a3, 16(a1)
lw a2, 20(a1)
lw v1, 24(a1)
lw v0, 28(a1)
sw a3, 16(a0)
sw a2, 20(a0)
sw v1, 24(a0)
sw v0, 28(a0)
cache Create_Dirty_Excl_D, 32(a0)
addiu a0, 64
addiu a1, 64
lw a3, -32(a1)
lw a2, -28(a1)
lw v1, -24(a1)
lw v0, -20(a1)
sw a3, -32(a0)
sw a2, -28(a0)
sw v1, -24(a0)
sw v0, -20(a0)
cache Create_Dirty_Excl_D, -16(a0)
lw a3, -16(a1)
lw a2, -12(a1)
lw v1, -8(a1)
lw v0, -4(a1)
sw a3, -16(a0)
sw a2, -12(a0)
sw v1, -8(a0)
bne AT, a0, 1b
sw v0, -4(a0)
jr ra
END(r4k_copy_page_d16)
LEAF(r4k_copy_page_d32)
addiu AT, a0, PAGE_SIZE
1: cache Create_Dirty_Excl_D, (a0)
lw a3, (a1)
lw a2, 4(a1)
lw v1, 8(a1)
lw v0, 12(a1)
sw a3, (a0)
sw a2, 4(a0)
sw v1, 8(a0)
sw v0, 12(a0)
lw a3, 16(a1)
lw a2, 20(a1)
lw v1, 24(a1)
lw v0, 28(a1)
sw a3, 16(a0)
sw a2, 20(a0)
sw v1, 24(a0)
sw v0, 28(a0)
cache Create_Dirty_Excl_D, 32(a0)
addiu a0, 64
addiu a1, 64
lw a3, -32(a1)
lw a2, -28(a1)
lw v1, -24(a1)
lw v0, -20(a1)
sw a3, -32(a0)
sw a2, -28(a0)
sw v1, -24(a0)
sw v0, -20(a0)
lw a3, -16(a1)
lw a2, -12(a1)
lw v1, -8(a1)
lw v0, -4(a1)
sw a3, -16(a0)
sw a2, -12(a0)
sw v1, -8(a0)
bne AT, a0, 1b
sw v0, -4(a0)
jr ra
END(r4k_copy_page_d32)
/*
* Again a special version for the R4600 V1.x
*/
LEAF(r4k_copy_page_r4600_v1)
addiu AT, a0, PAGE_SIZE
1: nop
nop
nop
nop
cache Create_Dirty_Excl_D, (a0)
lw a3, (a1)
lw a2, 4(a1)
lw v1, 8(a1)
lw v0, 12(a1)
sw a3, (a0)
sw a2, 4(a0)
sw v1, 8(a0)
sw v0, 12(a0)
lw a3, 16(a1)
lw a2, 20(a1)
lw v1, 24(a1)
lw v0, 28(a1)
sw a3, 16(a0)
sw a2, 20(a0)
sw v1, 24(a0)
sw v0, 28(a0)
nop
nop
nop
nop
cache Create_Dirty_Excl_D, 32(a0)
addiu a0, 64
addiu a1, 64
lw a3, -32(a1)
lw a2, -28(a1)
lw v1, -24(a1)
lw v0, -20(a1)
sw a3, -32(a0)
sw a2, -28(a0)
sw v1, -24(a0)
sw v0, -20(a0)
lw a3, -16(a1)
lw a2, -12(a1)
lw v1, -8(a1)
lw v0, -4(a1)
sw a3, -16(a0)
sw a2, -12(a0)
sw v1, -8(a0)
bne AT, a0, 1b
sw v0, -4(a0)
jr ra
END(r4k_copy_page_r4600_v1)
LEAF(r4k_copy_page_r4600_v2)
mfc0 v1, CP0_STATUS
ori AT, v1, 1
xori AT, 1
mtc0 AT, CP0_STATUS
nop
nop
nop
addiu AT, a0, PAGE_SIZE
1: nop
nop
nop
nop
cache Create_Dirty_Excl_D, (a0)
lw t1, (a1)
lw t0, 4(a1)
lw a3, 8(a1)
lw a2, 12(a1)
sw t1, (a0)
sw t0, 4(a0)
sw a3, 8(a0)
sw a2, 12(a0)
lw t1, 16(a1)
lw t0, 20(a1)
lw a3, 24(a1)
lw a2, 28(a1)
sw t1, 16(a0)
sw t0, 20(a0)
sw a3, 24(a0)
sw a2, 28(a0)
nop
nop
nop
nop
cache Create_Dirty_Excl_D, 32(a0)
addiu a0, 64
addiu a1, 64
lw t1, -32(a1)
lw t0, -28(a1)
lw a3, -24(a1)
lw a2, -20(a1)
sw t1, -32(a0)
sw t0, -28(a0)
sw a3, -24(a0)
sw a2, -20(a0)
lw t1, -16(a1)
lw t0, -12(a1)
lw a3, -8(a1)
lw a2, -4(a1)
sw t1, -16(a0)
sw t0, -12(a0)
sw a3, -8(a0)
bne AT, a0, 1b
sw a2, -4(a0)
mfc0 AT, CP0_STATUS # __restore_flags
andi v1, 1
ori AT, 1
xori AT, 1
or v1, AT
mtc0 v1, CP0_STATUS
nop
nop
nop
jr ra
END(r4k_copy_page_r4600_v2)
/*
* These are for R4000SC / R4400MC
*/
LEAF(r4k_copy_page_s16)
addiu AT, a0, PAGE_SIZE
1: cache Create_Dirty_Excl_SD, (a0)
lw a3, (a1)
lw a2, 4(a1)
lw v1, 8(a1)
lw v0, 12(a1)
sw a3, (a0)
sw a2, 4(a0)
sw v1, 8(a0)
sw v0, 12(a0)
cache Create_Dirty_Excl_SD, 16(a0)
lw a3, 16(a1)
lw a2, 20(a1)
lw v1, 24(a1)
lw v0, 28(a1)
sw a3, 16(a0)
sw a2, 20(a0)
sw v1, 24(a0)
sw v0, 28(a0)
cache Create_Dirty_Excl_SD, 32(a0)
addiu a0, 64
addiu a1, 64
lw a3, -32(a1)
lw a2, -28(a1)
lw v1, -24(a1)
lw v0, -20(a1)
sw a3, -32(a0)
sw a2, -28(a0)
sw v1, -24(a0)
sw v0, -20(a0)
cache Create_Dirty_Excl_SD, -16(a0)
lw a3, -16(a1)
lw a2, -12(a1)
lw v1, -8(a1)
lw v0, -4(a1)
sw a3, -16(a0)
sw a2, -12(a0)
sw v1, -8(a0)
bne AT, a0, 1b
sw v0, -4(a0)
jr ra
END(r4k_copy_page_s16)
LEAF(r4k_copy_page_s32)
addiu AT, a0, PAGE_SIZE
1: cache Create_Dirty_Excl_SD, (a0)
lw a3, (a1)
lw a2, 4(a1)
lw v1, 8(a1)
lw v0, 12(a1)
sw a3, (a0)
sw a2, 4(a0)
sw v1, 8(a0)
sw v0, 12(a0)
lw a3, 16(a1)
lw a2, 20(a1)
lw v1, 24(a1)
lw v0, 28(a1)
sw a3, 16(a0)
sw a2, 20(a0)
sw v1, 24(a0)
sw v0, 28(a0)
cache Create_Dirty_Excl_SD, 32(a0)
addiu a0, 64
addiu a1, 64
lw a3, -32(a1)
lw a2, -28(a1)
lw v1, -24(a1)
lw v0, -20(a1)
sw a3, -32(a0)
sw a2, -28(a0)
sw v1, -24(a0)
sw v0, -20(a0)
lw a3, -16(a1)
lw a2, -12(a1)
lw v1, -8(a1)
lw v0, -4(a1)
sw a3, -16(a0)
sw a2, -12(a0)
sw v1, -8(a0)
bne AT, a0, 1b
sw v0, -4(a0)
jr ra
END(r4k_copy_page_s32)
LEAF(r4k_copy_page_s64)
addiu AT, a0, PAGE_SIZE
1: cache Create_Dirty_Excl_SD, (a0)
lw a3, (a1)
lw a2, 4(a1)
lw v1, 8(a1)
lw v0, 12(a1)
sw a3, (a0)
sw a2, 4(a0)
sw v1, 8(a0)
sw v0, 12(a0)
lw a3, 16(a1)
lw a2, 20(a1)
lw v1, 24(a1)
lw v0, 28(a1)
sw a3, 16(a0)
sw a2, 20(a0)
sw v1, 24(a0)
sw v0, 28(a0)
addiu a0, 64
addiu a1, 64
lw a3, -32(a1)
lw a2, -28(a1)
lw v1, -24(a1)
lw v0, -20(a1)
sw a3, -32(a0)
sw a2, -28(a0)
sw v1, -24(a0)
sw v0, -20(a0)
lw a3, -16(a1)
lw a2, -12(a1)
lw v1, -8(a1)
lw v0, -4(a1)
sw a3, -16(a0)
sw a2, -12(a0)
sw v1, -8(a0)
bne AT, a0, 1b
sw v0, -4(a0)
jr ra
END(r4k_copy_page_s64)
LEAF(r4k_copy_page_s128)
addiu AT, a0, PAGE_SIZE
1: cache Create_Dirty_Excl_SD, (a0)
lw a3, (a1)
lw a2, 4(a1)
lw v1, 8(a1)
lw v0, 12(a1)
sw a3, (a0)
sw a2, 4(a0)
sw v1, 8(a0)
sw v0, 12(a0)
lw a3, 16(a1)
lw a2, 20(a1)
lw v1, 24(a1)
lw v0, 28(a1)
sw a3, 16(a0)
sw a2, 20(a0)
sw v1, 24(a0)
sw v0, 28(a0)
lw a3, 32(a1)
lw a2, 36(a1)
lw v1, 40(a1)
lw v0, 44(a1)
sw a3, 32(a0)
sw a2, 36(a0)
sw v1, 40(a0)
sw v0, 44(a0)
lw a3, 48(a1)
lw a2, 52(a1)
lw v1, 56(a1)
lw v0, 60(a1)
sw a3, 48(a0)
sw a2, 52(a0)
sw v1, 56(a0)
sw v0, 60(a0)
addiu a0, 128
addiu a1, 128
lw a3, -64(a1)
lw a2, -60(a1)
lw v1, -56(a1)
lw v0, -52(a1)
sw a3, -64(a0)
sw a2, -60(a0)
sw v1, -56(a0)
sw v0, -52(a0)
lw a3, -48(a1)
lw a2, -44(a1)
lw v1, -40(a1)
lw v0, -36(a1)
sw a3, -48(a0)
sw a2, -44(a0)
sw v1, -40(a0)
sw v0, -36(a0)
lw a3, -32(a1)
lw a2, -28(a1)
lw v1, -24(a1)
lw v0, -20(a1)
sw a3, -32(a0)
sw a2, -28(a0)
sw v1, -24(a0)
sw v0, -20(a0)
lw a3, -16(a1)
lw a2, -12(a1)
lw v1, -8(a1)
lw v0, -4(a1)
sw a3, -16(a0)
sw a2, -12(a0)
sw v1, -8(a0)
bne AT, a0, 1b
sw v0, -4(a0)
jr ra
END(r4k_copy_page_s128)
Index: Makefile
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/mm/Makefile,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- Makefile 2001/08/16 17:10:03 1.3
+++ Makefile 2001/10/08 16:29:33 1.4
@@ -12,16 +12,17 @@
export-objs += ioremap.o umap.o
obj-y += extable.o init.o ioremap.o fault.o loadmmu.o
-obj-$(CONFIG_CPU_R3000) += r2300.o
-obj-$(CONFIG_CPU_R4300) += r4xx0.o
-obj-$(CONFIG_CPU_R4X00) += r4xx0.o
-obj-$(CONFIG_CPU_VR41XX) += r4xx0.o
-obj-$(CONFIG_CPU_R5000) += r4xx0.o
-obj-$(CONFIG_CPU_NEVADA) += r4xx0.o
-obj-$(CONFIG_CPU_R5432) += r5432.o
-obj-$(CONFIG_CPU_RM7000) += rm7k.o
-obj-$(CONFIG_CPU_MIPS32) += mips32.o
-obj-$(CONFIG_CPU_MIPS64) += mips32.o
+obj-$(CONFIG_CPU_R3000) += pg-r2300.o r2300.o
+obj-$(CONFIG_CPU_R4300) += pg-r4xx0.o r4xx0.o
+obj-$(CONFIG_CPU_R4X00) += pg-r4xx0.o r4xx0.o
+obj-$(CONFIG_CPU_VR41XX) += pg-r4xx0.o r4xx0.o
+obj-$(CONFIG_CPU_R5000) += pg-r4xx0.o r4xx0.o
+obj-$(CONFIG_CPU_NEVADA) += pg-r4xx0.o r4xx0.o
+obj-$(CONFIG_CPU_R5432) += pg-r5432.o r5432.o
+obj-$(CONFIG_CPU_RM7000) += pg-rm7k.o rm7k.o
+obj-$(CONFIG_CPU_MIPS32) += pg-mips32.o mips32.o
+obj-$(CONFIG_CPU_MIPS64) += pg-mips32.o mips32.o
+
obj-$(CONFIG_SGI_IP22) += umap.o
obj-$(CONFIG_BAGET_MIPS) += umap.o
Index: andes.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/mm/andes.c,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- andes.c 2001/07/23 23:53:57 1.3
+++ andes.c 2001/10/08 16:29:33 1.4
@@ -13,83 +13,6 @@
#include <asm/sgialib.h>
#include <asm/mmu_context.h>
-/* page functions */
-void andes_clear_page(void * page)
-{
- __asm__ __volatile__(
- ".set\tnoreorder\n\t"
- ".set\tnoat\n\t"
- "addiu\t$1,%0,%2\n"
- "1:\tsw\t$0,(%0)\n\t"
- "sw\t$0,4(%0)\n\t"
- "sw\t$0,8(%0)\n\t"
- "sw\t$0,12(%0)\n\t"
- "addiu\t%0,32\n\t"
- "sw\t$0,-16(%0)\n\t"
- "sw\t$0,-12(%0)\n\t"
- "sw\t$0,-8(%0)\n\t"
- "bne\t$1,%0,1b\n\t"
- "sw\t$0,-4(%0)\n\t"
- ".set\tat\n\t"
- ".set\treorder"
- :"=r" (page)
- :"0" (page),
- "I" (PAGE_SIZE)
- :"$1","memory");
-}
-
-static void andes_copy_page(void * to, void * from)
-{
- unsigned long dummy1, dummy2;
- unsigned long reg1, reg2, reg3, reg4;
-
- __asm__ __volatile__(
- ".set\tnoreorder\n\t"
- ".set\tnoat\n\t"
- "addiu\t$1,%0,%8\n"
- "1:\tlw\t%2,(%1)\n\t"
- "lw\t%3,4(%1)\n\t"
- "lw\t%4,8(%1)\n\t"
- "lw\t%5,12(%1)\n\t"
- "sw\t%2,(%0)\n\t"
- "sw\t%3,4(%0)\n\t"
- "sw\t%4,8(%0)\n\t"
- "sw\t%5,12(%0)\n\t"
- "lw\t%2,16(%1)\n\t"
- "lw\t%3,20(%1)\n\t"
- "lw\t%4,24(%1)\n\t"
- "lw\t%5,28(%1)\n\t"
- "sw\t%2,16(%0)\n\t"
- "sw\t%3,20(%0)\n\t"
- "sw\t%4,24(%0)\n\t"
- "sw\t%5,28(%0)\n\t"
- "addiu\t%0,64\n\t"
- "addiu\t%1,64\n\t"
- "lw\t%2,-32(%1)\n\t"
- "lw\t%3,-28(%1)\n\t"
- "lw\t%4,-24(%1)\n\t"
- "lw\t%5,-20(%1)\n\t"
- "sw\t%2,-32(%0)\n\t"
- "sw\t%3,-28(%0)\n\t"
- "sw\t%4,-24(%0)\n\t"
- "sw\t%5,-20(%0)\n\t"
- "lw\t%2,-16(%1)\n\t"
- "lw\t%3,-12(%1)\n\t"
- "lw\t%4,-8(%1)\n\t"
- "lw\t%5,-4(%1)\n\t"
- "sw\t%2,-16(%0)\n\t"
- "sw\t%3,-12(%0)\n\t"
- "sw\t%4,-8(%0)\n\t"
- "bne\t$1,%0,1b\n\t"
- "sw\t%5,-4(%0)\n\t"
- ".set\tat\n\t"
- ".set\treorder"
- :"=r" (dummy1), "=r" (dummy2),
- "=&r" (reg1), "=&r" (reg2), "=&r" (reg3), "=&r" (reg4)
- :"0" (to), "1" (from),
- "I" (PAGE_SIZE));
-}
-
/* Cache operations. XXX Write these dave... */
static inline void andes_flush_cache_all(void)
{
Index: mips32.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/mm/mips32.c,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- mips32.c 2001/07/23 23:53:57 1.3
+++ mips32.c 2001/10/08 16:29:33 1.4
@@ -37,11 +37,11 @@
".set reorder\n\t")
/* Primary cache parameters. */
-static int icache_size, dcache_size; /* Size in bytes */
-static int ic_lsize, dc_lsize; /* LineSize in bytes */
+int icache_size, dcache_size; /* Size in bytes */
+int ic_lsize, dc_lsize; /* LineSize in bytes */
/* Secondary cache (if present) parameters. */
-static unsigned int scache_size, sc_lsize; /* Again, in bytes */
+unsigned int scache_size, sc_lsize; /* Again, in bytes */
#include <asm/cacheops.h>
#include <asm/mips32_cache.h>
@@ -59,103 +59,6 @@
};
struct bcache_ops *bcops = &no_sc_ops;
-
-
-/*
- * Zero an entire page.
- */
-
-static void mips32_clear_page_dc(unsigned long page)
-{
- unsigned long i;
-
- if (mips_cpu.options & MIPS_CPU_CACHE_CDEX) {
- for (i=page; i<page+PAGE_SIZE; i+=dc_lsize) {
- __asm__ __volatile__(
- ".set\tnoreorder\n\t"
- ".set\tnoat\n\t"
- ".set\tmips3\n\t"
- "cache\t%2,(%0)\n\t"
- ".set\tmips0\n\t"
- ".set\tat\n\t"
- ".set\treorder"
- :"=r" (i)
- :"0" (i),
- "I" (Create_Dirty_Excl_D));
- }
- }
- for (i=page; i<page+PAGE_SIZE; i+=4)
- *(unsigned long *)(i) = 0;
-}
-
-static void mips32_clear_page_sc(unsigned long page)
-{
- unsigned long i;
-
- if (mips_cpu.options & MIPS_CPU_CACHE_CDEX) {
- for (i=page; i<page+PAGE_SIZE; i+=sc_lsize) {
- __asm__ __volatile__(
- ".set\tnoreorder\n\t"
- ".set\tnoat\n\t"
- ".set\tmips3\n\t"
- "cache\t%2,(%0)\n\t"
- ".set\tmips0\n\t"
- ".set\tat\n\t"
- ".set\treorder"
- :"=r" (i)
- :"0" (i),
- "I" (Create_Dirty_Excl_SD));
- }
- }
- for (i=page; i<page+PAGE_SIZE; i+=4)
- *(unsigned long *)(i) = 0;
-}
-
-static void mips32_copy_page_dc(unsigned long to, unsigned long from)
-{
- unsigned long i;
-
- if (mips_cpu.options & MIPS_CPU_CACHE_CDEX) {
- for (i=to; i<to+PAGE_SIZE; i+=dc_lsize) {
- __asm__ __volatile__(
- ".set\tnoreorder\n\t"
- ".set\tnoat\n\t"
- ".set\tmips3\n\t"
- "cache\t%2,(%0)\n\t"
- ".set\tmips0\n\t"
- ".set\tat\n\t"
- ".set\treorder"
- :"=r" (i)
- :"0" (i),
- "I" (Create_Dirty_Excl_D));
- }
- }
- for (i=0; i<PAGE_SIZE; i+=4)
- *(unsigned long *)(to+i) = *(unsigned long *)(from+i);
-}
-
-static void mips32_copy_page_sc(unsigned long to, unsigned long from)
-{
- unsigned long i;
-
- if (mips_cpu.options & MIPS_CPU_CACHE_CDEX) {
- for (i=to; i<to+PAGE_SIZE; i+=sc_lsize) {
- __asm__ __volatile__(
- ".set\tnoreorder\n\t"
- ".set\tnoat\n\t"
- ".set\tmips3\n\t"
- "cache\t%2,(%0)\n\t"
- ".set\tmips0\n\t"
- ".set\tat\n\t"
- ".set\treorder"
- :"=r" (i)
- :"0" (i),
- "I" (Create_Dirty_Excl_SD));
- }
- }
- for (i=0; i<PAGE_SIZE; i+=4)
- *(unsigned long *)(to+i) = *(unsigned long *)(from+i);
-}
static inline void mips32_flush_cache_all_sc(void)
{
Index: r2300.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/mm/r2300.c,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- r2300.c 2001/07/17 17:27:36 1.3
+++ r2300.c 2001/10/08 16:29:33 1.4
@@ -41,83 +41,6 @@
#undef DEBUG_TLB
#undef DEBUG_CACHE
-/* page functions */
-void r3k_clear_page(void * page)
-{
- __asm__ __volatile__(
- ".set\tnoreorder\n\t"
- ".set\tnoat\n\t"
- "addiu\t$1,%0,%2\n"
- "1:\tsw\t$0,(%0)\n\t"
- "sw\t$0,4(%0)\n\t"
- "sw\t$0,8(%0)\n\t"
- "sw\t$0,12(%0)\n\t"
- "addiu\t%0,32\n\t"
- "sw\t$0,-16(%0)\n\t"
- "sw\t$0,-12(%0)\n\t"
- "sw\t$0,-8(%0)\n\t"
- "bne\t$1,%0,1b\n\t"
- "sw\t$0,-4(%0)\n\t"
- ".set\tat\n\t"
- ".set\treorder"
- :"=r" (page)
- :"0" (page),
- "I" (PAGE_SIZE)
- :"$1","memory");
-}
-
-static void r3k_copy_page(void * to, void * from)
-{
- unsigned long dummy1, dummy2;
- unsigned long reg1, reg2, reg3, reg4;
-
- __asm__ __volatile__(
- ".set\tnoreorder\n\t"
- ".set\tnoat\n\t"
- "addiu\t$1,%0,%8\n"
- "1:\tlw\t%2,(%1)\n\t"
- "lw\t%3,4(%1)\n\t"
- "lw\t%4,8(%1)\n\t"
- "lw\t%5,12(%1)\n\t"
- "sw\t%2,(%0)\n\t"
- "sw\t%3,4(%0)\n\t"
- "sw\t%4,8(%0)\n\t"
- "sw\t%5,12(%0)\n\t"
- "lw\t%2,16(%1)\n\t"
- "lw\t%3,20(%1)\n\t"
- "lw\t%4,24(%1)\n\t"
- "lw\t%5,28(%1)\n\t"
- "sw\t%2,16(%0)\n\t"
- "sw\t%3,20(%0)\n\t"
- "sw\t%4,24(%0)\n\t"
- "sw\t%5,28(%0)\n\t"
- "addiu\t%0,64\n\t"
- "addiu\t%1,64\n\t"
- "lw\t%2,-32(%1)\n\t"
- "lw\t%3,-28(%1)\n\t"
- "lw\t%4,-24(%1)\n\t"
- "lw\t%5,-20(%1)\n\t"
- "sw\t%2,-32(%0)\n\t"
- "sw\t%3,-28(%0)\n\t"
- "sw\t%4,-24(%0)\n\t"
- "sw\t%5,-20(%0)\n\t"
- "lw\t%2,-16(%1)\n\t"
- "lw\t%3,-12(%1)\n\t"
- "lw\t%4,-8(%1)\n\t"
- "lw\t%5,-4(%1)\n\t"
- "sw\t%2,-16(%0)\n\t"
- "sw\t%3,-12(%0)\n\t"
- "sw\t%4,-8(%0)\n\t"
- "bne\t$1,%0,1b\n\t"
- "sw\t%5,-4(%0)\n\t"
- ".set\tat\n\t"
- ".set\treorder"
- :"=r" (dummy1), "=r" (dummy2),
- "=&r" (reg1), "=&r" (reg2), "=&r" (reg3), "=&r" (reg4)
- :"0" (to), "1" (from),
- "I" (PAGE_SIZE));
-}
-
unsigned long __init r3k_cache_size(unsigned long ca_flags)
{
unsigned long flags, status, dummy, size;
Index: r4xx0.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/mm/r4xx0.c,v
retrieving revision 1.6
retrieving revision 1.7
diff -u -d -r1.6 -r1.7
--- r4xx0.c 2001/08/16 17:13:31 1.6
+++ r4xx0.c 2001/10/08 16:29:33 1.7
@@ -66,835 +66,6 @@
#define dcache_waybit (dcache_size >> 1)
/*
- * Zero an entire page. Basically a simple unrolled loop should do the
- * job but we want more performance by saving memory bus bandwidth. We
- * have five flavours of the routine available for:
- *
- * - 16byte cachelines and no second level cache
- * - 32byte cachelines second level cache
- * - a version which handles the buggy R4600 v1.x
- * - a version which handles the buggy R4600 v2.0
- * - Finally a last version without fancy cache games for the SC and MC
- * versions of R4000 and R4400.
- */
-
-static void r4k_clear_page_d16(void * page)
-{
- __asm__ __volatile__(
- ".set\tnoreorder\n\t"
- ".set\tnoat\n\t"
- ".set\tmips3\n\t"
- "daddiu\t$1,%0,%2\n"
- "1:\tcache\t%3,(%0)\n\t"
- "sd\t$0,(%0)\n\t"
- "sd\t$0,8(%0)\n\t"
- "cache\t%3,16(%0)\n\t"
- "sd\t$0,16(%0)\n\t"
- "sd\t$0,24(%0)\n\t"
- "daddiu\t%0,64\n\t"
- "cache\t%3,-32(%0)\n\t"
- "sd\t$0,-32(%0)\n\t"
- "sd\t$0,-24(%0)\n\t"
- "cache\t%3,-16(%0)\n\t"
- "sd\t$0,-16(%0)\n\t"
- "bne\t$1,%0,1b\n\t"
- "sd\t$0,-8(%0)\n\t"
- ".set\tmips0\n\t"
- ".set\tat\n\t"
- ".set\treorder"
- :"=r" (page)
- :"0" (page),
- "I" (PAGE_SIZE),
- "i" (Create_Dirty_Excl_D)
- :"$1","memory");
-}
-
-static void r4k_clear_page_d32(void * page)
-{
- __asm__ __volatile__(
- ".set\tnoreorder\n\t"
- ".set\tnoat\n\t"
- ".set\tmips3\n\t"
- "daddiu\t$1,%0,%2\n"
- "1:\tcache\t%3,(%0)\n\t"
- "sd\t$0,(%0)\n\t"
- "sd\t$0,8(%0)\n\t"
- "sd\t$0,16(%0)\n\t"
- "sd\t$0,24(%0)\n\t"
- "daddiu\t%0,64\n\t"
- "cache\t%3,-32(%0)\n\t"
- "sd\t$0,-32(%0)\n\t"
- "sd\t$0,-24(%0)\n\t"
- "sd\t$0,-16(%0)\n\t"
- "bne\t$1,%0,1b\n\t"
- "sd\t$0,-8(%0)\n\t"
- ".set\tmips0\n\t"
- ".set\tat\n\t"
- ".set\treorder"
- :"=r" (page)
- :"0" (page),
- "I" (PAGE_SIZE),
- "i" (Create_Dirty_Excl_D)
- :"$1","memory");
-}
-
-
-/*
- * This flavour of r4k_clear_page is for the R4600 V1.x. Cite from the
- * IDT R4600 V1.7 errata:
- *
- * 18. The CACHE instructions Hit_Writeback_Invalidate_D, Hit_Writeback_D,
- * Hit_Invalidate_D and Create_Dirty_Excl_D should only be
- * executed if there is no other dcache activity. If the dcache is
- * accessed for another instruction immeidately preceding when these
- * cache instructions are executing, it is possible that the dcache
- * tag match outputs used by these cache instructions will be
- * incorrect. These cache instructions should be preceded by at least
- * four instructions that are not any kind of load or store
- * instruction.
- *
- * This is not allowed: lw
- * nop
- * nop
- * nop
- * cache Hit_Writeback_Invalidate_D
- *
- * This is allowed: lw
- * nop
- * nop
- * nop
- * nop
- * cache Hit_Writeback_Invalidate_D
- */
-static void r4k_clear_page_r4600_v1(void * page)
-{
- __asm__ __volatile__(
- ".set\tnoreorder\n\t"
- ".set\tnoat\n\t"
- ".set\tmips3\n\t"
- "daddiu\t$1,%0,%2\n"
- "1:\tnop\n\t"
- "nop\n\t"
- "nop\n\t"
- "nop\n\t"
- "cache\t%3,(%0)\n\t"
- "sd\t$0,(%0)\n\t"
- "sd\t$0,8(%0)\n\t"
- "sd\t$0,16(%0)\n\t"
- "sd\t$0,24(%0)\n\t"
- "daddiu\t%0,64\n\t"
- "nop\n\t"
- "nop\n\t"
- "nop\n\t"
- "cache\t%3,-32(%0)\n\t"
- "sd\t$0,-32(%0)\n\t"
- "sd\t$0,-24(%0)\n\t"
- "sd\t$0,-16(%0)\n\t"
- "bne\t$1,%0,1b\n\t"
- "sd\t$0,-8(%0)\n\t"
- ".set\tmips0\n\t"
- ".set\tat\n\t"
- ".set\treorder"
- :"=r" (page)
- :"0" (page),
- "I" (PAGE_SIZE),
- "i" (Create_Dirty_Excl_D)
- :"$1","memory");
-}
-
-/*
- * And this one is for the R4600 V2.0
- */
-static void r4k_clear_page_r4600_v2(void * page)
-{
- unsigned int flags;
-
- __save_and_cli(flags);
- *(volatile unsigned int *)KSEG1;
- __asm__ __volatile__(
- ".set\tnoreorder\n\t"
- ".set\tnoat\n\t"
- ".set\tmips3\n\t"
- "daddiu\t$1,%0,%2\n"
- "1:\tcache\t%3,(%0)\n\t"
- "sd\t$0,(%0)\n\t"
- "sd\t$0,8(%0)\n\t"
- "sd\t$0,16(%0)\n\t"
- "sd\t$0,24(%0)\n\t"
- "daddiu\t%0,64\n\t"
- "cache\t%3,-32(%0)\n\t"
- "sd\t$0,-32(%0)\n\t"
- "sd\t$0,-24(%0)\n\t"
- "sd\t$0,-16(%0)\n\t"
- "bne\t$1,%0,1b\n\t"
- "sd\t$0,-8(%0)\n\t"
- ".set\tmips0\n\t"
- ".set\tat\n\t"
- ".set\treorder"
- :"=r" (page)
- :"0" (page),
- "I" (PAGE_SIZE),
- "i" (Create_Dirty_Excl_D)
- :"$1","memory");
- __restore_flags(flags);
-}
-
-/*
- * The next 4 versions are optimized for all possible scache configurations
- * of the SC / MC versions of R4000 and R4400 ...
- *
- * Todo: For even better performance we should have a routine optimized for
- * every legal combination of dcache / scache linesize. When I (Ralf) tried
- * this the kernel crashed shortly after mounting the root filesystem. CPU
- * bug? Weirdo cache instruction semantics?
- */
-static void r4k_clear_page_s16(void * page)
-{
- __asm__ __volatile__(
- ".set\tnoreorder\n\t"
- ".set\tnoat\n\t"
- ".set\tmips3\n\t"
- "daddiu\t$1,%0,%2\n"
- "1:\tcache\t%3,(%0)\n\t"
- "sd\t$0,(%0)\n\t"
- "sd\t$0,8(%0)\n\t"
- "cache\t%3,16(%0)\n\t"
- "sd\t$0,16(%0)\n\t"
- "sd\t$0,24(%0)\n\t"
- "daddiu\t%0,64\n\t"
- "cache\t%3,-32(%0)\n\t"
- "sd\t$0,-32(%0)\n\t"
- "sd\t$0,-24(%0)\n\t"
- "cache\t%3,-16(%0)\n\t"
- "sd\t$0,-16(%0)\n\t"
- "bne\t$1,%0,1b\n\t"
- "sd\t$0,-8(%0)\n\t"
- ".set\tmips0\n\t"
- ".set\tat\n\t"
- ".set\treorder"
- :"=r" (page)
- :"0" (page),
- "I" (PAGE_SIZE),
- "i" (Create_Dirty_Excl_SD)
- :"$1","memory");
-}
-
-static void r4k_clear_page_s32(void * page)
-{
- __asm__ __volatile__(
- ".set\tnoreorder\n\t"
- ".set\tnoat\n\t"
- ".set\tmips3\n\t"
- "daddiu\t$1,%0,%2\n"
- "1:\tcache\t%3,(%0)\n\t"
- "sd\t$0,(%0)\n\t"
- "sd\t$0,8(%0)\n\t"
- "sd\t$0,16(%0)\n\t"
- "sd\t$0,24(%0)\n\t"
- "daddiu\t%0,64\n\t"
- "cache\t%3,-32(%0)\n\t"
- "sd\t$0,-32(%0)\n\t"
- "sd\t$0,-24(%0)\n\t"
- "sd\t$0,-16(%0)\n\t"
- "bne\t$1,%0,1b\n\t"
- "sd\t$0,-8(%0)\n\t"
- ".set\tmips0\n\t"
- ".set\tat\n\t"
- ".set\treorder"
- :"=r" (page)
- :"0" (page),
- "I" (PAGE_SIZE),
- "i" (Create_Dirty_Excl_SD)
- :"$1","memory");
-}
-
-static void r4k_clear_page_s64(void * page)
-{
- __asm__ __volatile__(
- ".set\tnoreorder\n\t"
- ".set\tnoat\n\t"
- ".set\tmips3\n\t"
- "daddiu\t$1,%0,%2\n"
- "1:\tcache\t%3,(%0)\n\t"
- "sd\t$0,(%0)\n\t"
- "sd\t$0,8(%0)\n\t"
- "sd\t$0,16(%0)\n\t"
- "sd\t$0,24(%0)\n\t"
- "daddiu\t%0,64\n\t"
- "sd\t$0,-32(%0)\n\t"
- "sd\t$0,-24(%0)\n\t"
- "sd\t$0,-16(%0)\n\t"
- "bne\t$1,%0,1b\n\t"
- "sd\t$0,-8(%0)\n\t"
- ".set\tmips0\n\t"
- ".set\tat\n\t"
- ".set\treorder"
- :"=r" (page)
- :"0" (page),
- "I" (PAGE_SIZE),
- "i" (Create_Dirty_Excl_SD)
- :"$1","memory");
-}
-
-static void r4k_clear_page_s128(void * page)
-{
- __asm__ __volatile__(
- ".set\tnoreorder\n\t"
- ".set\tnoat\n\t"
- ".set\tmips3\n\t"
- "daddiu\t$1,%0,%2\n"
- "1:\tcache\t%3,(%0)\n\t"
- "sd\t$0,(%0)\n\t"
- "sd\t$0,8(%0)\n\t"
- "sd\t$0,16(%0)\n\t"
- "sd\t$0,24(%0)\n\t"
- "sd\t$0,32(%0)\n\t"
- "sd\t$0,40(%0)\n\t"
- "sd\t$0,48(%0)\n\t"
- "sd\t$0,56(%0)\n\t"
- "daddiu\t%0,128\n\t"
- "sd\t$0,-64(%0)\n\t"
- "sd\t$0,-56(%0)\n\t"
- "sd\t$0,-48(%0)\n\t"
- "sd\t$0,-40(%0)\n\t"
- "sd\t$0,-32(%0)\n\t"
- "sd\t$0,-24(%0)\n\t"
- "sd\t$0,-16(%0)\n\t"
- "bne\t$1,%0,1b\n\t"
- "sd\t$0,-8(%0)\n\t"
- ".set\tmips0\n\t"
- ".set\tat\n\t"
- ".set\treorder"
- :"=r" (page)
- :"0" (page),
- "I" (PAGE_SIZE),
- "i" (Create_Dirty_Excl_SD)
- :"$1","memory");
-}
-
-
-/*
- * This is still inefficient. We only can do better if we know the
- * virtual address where the copy will be accessed.
- */
-
-static void r4k_copy_page_d16(void * to, void * from)
-{
- unsigned long dummy1, dummy2;
- unsigned long reg1, reg2, reg3, reg4;
-
- __asm__ __volatile__(
- ".set\tnoreorder\n\t"
- ".set\tnoat\n\t"
- ".set\tmips3\n\t"
- "daddiu\t$1,%0,%8\n"
- "1:\tcache\t%9,(%0)\n\t"
- "lw\t%2,(%1)\n\t"
- "lw\t%3,4(%1)\n\t"
- "lw\t%4,8(%1)\n\t"
- "lw\t%5,12(%1)\n\t"
- "sw\t%2,(%0)\n\t"
- "sw\t%3,4(%0)\n\t"
- "sw\t%4,8(%0)\n\t"
- "sw\t%5,12(%0)\n\t"
- "cache\t%9,16(%0)\n\t"
- "lw\t%2,16(%1)\n\t"
- "lw\t%3,20(%1)\n\t"
- "lw\t%4,24(%1)\n\t"
- "lw\t%5,28(%1)\n\t"
- "sw\t%2,16(%0)\n\t"
- "sw\t%3,20(%0)\n\t"
- "sw\t%4,24(%0)\n\t"
- "sw\t%5,28(%0)\n\t"
- "cache\t%9,32(%0)\n\t"
- "daddiu\t%0,64\n\t"
- "daddiu\t%1,64\n\t"
- "lw\t%2,-32(%1)\n\t"
- "lw\t%3,-28(%1)\n\t"
- "lw\t%4,-24(%1)\n\t"
- "lw\t%5,-20(%1)\n\t"
- "sw\t%2,-32(%0)\n\t"
- "sw\t%3,-28(%0)\n\t"
- "sw\t%4,-24(%0)\n\t"
- "sw\t%5,-20(%0)\n\t"
- "cache\t%9,-16(%0)\n\t"
- "lw\t%2,-16(%1)\n\t"
- "lw\t%3,-12(%1)\n\t"
- "lw\t%4,-8(%1)\n\t"
- "lw\t%5,-4(%1)\n\t"
- "sw\t%2,-16(%0)\n\t"
- "sw\t%3,-12(%0)\n\t"
- "sw\t%4,-8(%0)\n\t"
- "bne\t$1,%0,1b\n\t"
- "sw\t%5,-4(%0)\n\t"
- ".set\tmips0\n\t"
- ".set\tat\n\t"
- ".set\treorder"
- :"=r" (dummy1), "=r" (dummy2),
- "=&r" (reg1), "=&r" (reg2), "=&r" (reg3), "=&r" (reg4)
- :"0" (to), "1" (from),
- "I" (PAGE_SIZE),
- "i" (Create_Dirty_Excl_D));
-}
-
-static void r4k_copy_page_d32(void * to, void * from)
-{
- unsigned long dummy1, dummy2;
- unsigned long reg1, reg2, reg3, reg4;
-
- __asm__ __volatile__(
- ".set\tnoreorder\n\t"
- ".set\tnoat\n\t"
- ".set\tmips3\n\t"
- "daddiu\t$1,%0,%8\n"
- "1:\tcache\t%9,(%0)\n\t"
- "lw\t%2,(%1)\n\t"
- "lw\t%3,4(%1)\n\t"
- "lw\t%4,8(%1)\n\t"
- "lw\t%5,12(%1)\n\t"
- "sw\t%2,(%0)\n\t"
- "sw\t%3,4(%0)\n\t"
- "sw\t%4,8(%0)\n\t"
- "sw\t%5,12(%0)\n\t"
- "lw\t%2,16(%1)\n\t"
- "lw\t%3,20(%1)\n\t"
- "lw\t%4,24(%1)\n\t"
- "lw\t%5,28(%1)\n\t"
- "sw\t%2,16(%0)\n\t"
- "sw\t%3,20(%0)\n\t"
- "sw\t%4,24(%0)\n\t"
- "sw\t%5,28(%0)\n\t"
- "cache\t%9,32(%0)\n\t"
- "daddiu\t%0,64\n\t"
- "daddiu\t%1,64\n\t"
- "lw\t%2,-32(%1)\n\t"
- "lw\t%3,-28(%1)\n\t"
- "lw\t%4,-24(%1)\n\t"
- "lw\t%5,-20(%1)\n\t"
- "sw\t%2,-32(%0)\n\t"
- "sw\t%3,-28(%0)\n\t"
- "sw\t%4,-24(%0)\n\t"
- "sw\t%5,-20(%0)\n\t"
- "lw\t%2,-16(%1)\n\t"
- "lw\t%3,-12(%1)\n\t"
- "lw\t%4,-8(%1)\n\t"
- "lw\t%5,-4(%1)\n\t"
- "sw\t%2,-16(%0)\n\t"
- "sw\t%3,-12(%0)\n\t"
- "sw\t%4,-8(%0)\n\t"
- "bne\t$1,%0,1b\n\t"
- "sw\t%5,-4(%0)\n\t"
- ".set\tmips0\n\t"
- ".set\tat\n\t"
- ".set\treorder"
- :"=r" (dummy1), "=r" (dummy2),
- "=&r" (reg1), "=&r" (reg2), "=&r" (reg3), "=&r" (reg4)
- :"0" (to), "1" (from),
- "I" (PAGE_SIZE),
- "i" (Create_Dirty_Excl_D));
-}
-
-/*
- * Again a special version for the R4600 V1.x
- */
-static void r4k_copy_page_r4600_v1(void * to, void * from)
-{
- unsigned long dummy1, dummy2;
- unsigned long reg1, reg2, reg3, reg4;
-
- __asm__ __volatile__(
- ".set\tnoreorder\n\t"
- ".set\tnoat\n\t"
- ".set\tmips3\n\t"
- "daddiu\t$1,%0,%8\n"
- "1:\tnop\n\t"
- "nop\n\t"
- "nop\n\t"
- "nop\n\t"
- "\tcache\t%9,(%0)\n\t"
- "lw\t%2,(%1)\n\t"
- "lw\t%3,4(%1)\n\t"
- "lw\t%4,8(%1)\n\t"
- "lw\t%5,12(%1)\n\t"
- "sw\t%2,(%0)\n\t"
- "sw\t%3,4(%0)\n\t"
- "sw\t%4,8(%0)\n\t"
- "sw\t%5,12(%0)\n\t"
- "lw\t%2,16(%1)\n\t"
- "lw\t%3,20(%1)\n\t"
- "lw\t%4,24(%1)\n\t"
- "lw\t%5,28(%1)\n\t"
- "sw\t%2,16(%0)\n\t"
- "sw\t%3,20(%0)\n\t"
- "sw\t%4,24(%0)\n\t"
- "sw\t%5,28(%0)\n\t"
- "nop\n\t"
- "nop\n\t"
- "nop\n\t"
- "nop\n\t"
- "cache\t%9,32(%0)\n\t"
- "daddiu\t%0,64\n\t"
- "daddiu\t%1,64\n\t"
- "lw\t%2,-32(%1)\n\t"
- "lw\t%3,-28(%1)\n\t"
- "lw\t%4,-24(%1)\n\t"
- "lw\t%5,-20(%1)\n\t"
- "sw\t%2,-32(%0)\n\t"
- "sw\t%3,-28(%0)\n\t"
- "sw\t%4,-24(%0)\n\t"
- "sw\t%5,-20(%0)\n\t"
- "lw\t%2,-16(%1)\n\t"
- "lw\t%3,-12(%1)\n\t"
- "lw\t%4,-8(%1)\n\t"
- "lw\t%5,-4(%1)\n\t"
- "sw\t%2,-16(%0)\n\t"
- "sw\t%3,-12(%0)\n\t"
- "sw\t%4,-8(%0)\n\t"
- "bne\t$1,%0,1b\n\t"
- "sw\t%5,-4(%0)\n\t"
- ".set\tmips0\n\t"
- ".set\tat\n\t"
- ".set\treorder"
- :"=r" (dummy1), "=r" (dummy2),
- "=&r" (reg1), "=&r" (reg2), "=&r" (reg3), "=&r" (reg4)
- :"0" (to), "1" (from),
- "I" (PAGE_SIZE),
- "i" (Create_Dirty_Excl_D));
-}
-
-static void r4k_copy_page_r4600_v2(void * to, void * from)
-{
- unsigned long dummy1, dummy2;
- unsigned long reg1, reg2, reg3, reg4;
- unsigned int flags;
-
- __save_and_cli(flags);
- __asm__ __volatile__(
- ".set\tnoreorder\n\t"
- ".set\tnoat\n\t"
- ".set\tmips3\n\t"
- "daddiu\t$1,%0,%8\n"
- "1:\tnop\n\t"
- "nop\n\t"
- "nop\n\t"
- "nop\n\t"
- "\tcache\t%9,(%0)\n\t"
- "lw\t%2,(%1)\n\t"
- "lw\t%3,4(%1)\n\t"
- "lw\t%4,8(%1)\n\t"
- "lw\t%5,12(%1)\n\t"
- "sw\t%2,(%0)\n\t"
- "sw\t%3,4(%0)\n\t"
- "sw\t%4,8(%0)\n\t"
- "sw\t%5,12(%0)\n\t"
- "lw\t%2,16(%1)\n\t"
- "lw\t%3,20(%1)\n\t"
- "lw\t%4,24(%1)\n\t"
- "lw\t%5,28(%1)\n\t"
- "sw\t%2,16(%0)\n\t"
- "sw\t%3,20(%0)\n\t"
- "sw\t%4,24(%0)\n\t"
- "sw\t%5,28(%0)\n\t"
- "nop\n\t"
- "nop\n\t"
- "nop\n\t"
- "nop\n\t"
- "cache\t%9,32(%0)\n\t"
- "daddiu\t%0,64\n\t"
- "daddiu\t%1,64\n\t"
- "lw\t%2,-32(%1)\n\t"
- "lw\t%3,-28(%1)\n\t"
- "lw\t%4,-24(%1)\n\t"
- "lw\t%5,-20(%1)\n\t"
- "sw\t%2,-32(%0)\n\t"
- "sw\t%3,-28(%0)\n\t"
- "sw\t%4,-24(%0)\n\t"
- "sw\t%5,-20(%0)\n\t"
- "lw\t%2,-16(%1)\n\t"
- "lw\t%3,-12(%1)\n\t"
- "lw\t%4,-8(%1)\n\t"
- "lw\t%5,-4(%1)\n\t"
- "sw\t%2,-16(%0)\n\t"
- "sw\t%3,-12(%0)\n\t"
- "sw\t%4,-8(%0)\n\t"
- "bne\t$1,%0,1b\n\t"
- "sw\t%5,-4(%0)\n\t"
- ".set\tmips0\n\t"
- ".set\tat\n\t"
- ".set\treorder"
- :"=r" (dummy1), "=r" (dummy2),
- "=&r" (reg1), "=&r" (reg2), "=&r" (reg3), "=&r" (reg4)
- :"0" (to), "1" (from),
- "I" (PAGE_SIZE),
- "i" (Create_Dirty_Excl_D));
- __restore_flags(flags);
-}
-
-/*
- * These are for R4000SC / R4400MC
- */
-static void r4k_copy_page_s16(void * to, void * from)
-{
- unsigned long dummy1, dummy2;
- unsigned long reg1, reg2, reg3, reg4;
-
- __asm__ __volatile__(
- ".set\tnoreorder\n\t"
- ".set\tnoat\n\t"
- ".set\tmips3\n\t"
- "daddiu\t$1,%0,%8\n"
- "1:\tcache\t%9,(%0)\n\t"
- "lw\t%2,(%1)\n\t"
- "lw\t%3,4(%1)\n\t"
- "lw\t%4,8(%1)\n\t"
- "lw\t%5,12(%1)\n\t"
- "sw\t%2,(%0)\n\t"
- "sw\t%3,4(%0)\n\t"
- "sw\t%4,8(%0)\n\t"
- "sw\t%5,12(%0)\n\t"
- "cache\t%9,16(%0)\n\t"
- "lw\t%2,16(%1)\n\t"
- "lw\t%3,20(%1)\n\t"
- "lw\t%4,24(%1)\n\t"
- "lw\t%5,28(%1)\n\t"
- "sw\t%2,16(%0)\n\t"
- "sw\t%3,20(%0)\n\t"
- "sw\t%4,24(%0)\n\t"
- "sw\t%5,28(%0)\n\t"
- "cache\t%9,32(%0)\n\t"
- "daddiu\t%0,64\n\t"
- "daddiu\t%1,64\n\t"
- "lw\t%2,-32(%1)\n\t"
- "lw\t%3,-28(%1)\n\t"
- "lw\t%4,-24(%1)\n\t"
- "lw\t%5,-20(%1)\n\t"
- "sw\t%2,-32(%0)\n\t"
- "sw\t%3,-28(%0)\n\t"
- "sw\t%4,-24(%0)\n\t"
- "sw\t%5,-20(%0)\n\t"
- "cache\t%9,-16(%0)\n\t"
- "lw\t%2,-16(%1)\n\t"
- "lw\t%3,-12(%1)\n\t"
- "lw\t%4,-8(%1)\n\t"
- "lw\t%5,-4(%1)\n\t"
- "sw\t%2,-16(%0)\n\t"
- "sw\t%3,-12(%0)\n\t"
- "sw\t%4,-8(%0)\n\t"
- "bne\t$1,%0,1b\n\t"
- "sw\t%5,-4(%0)\n\t"
- ".set\tmips0\n\t"
- ".set\tat\n\t"
- ".set\treorder"
- :"=r" (dummy1), "=r" (dummy2),
- "=&r" (reg1), "=&r" (reg2), "=&r" (reg3), "=&r" (reg4)
- :"0" (to), "1" (from),
- "I" (PAGE_SIZE),
- "i" (Create_Dirty_Excl_SD));
-}
-
-static void r4k_copy_page_s32(void * to, void * from)
-{
- unsigned long dummy1, dummy2;
- unsigned long reg1, reg2, reg3, reg4;
-
- __asm__ __volatile__(
- ".set\tnoreorder\n\t"
- ".set\tnoat\n\t"
- ".set\tmips3\n\t"
- "daddiu\t$1,%0,%8\n"
- "1:\tcache\t%9,(%0)\n\t"
- "lw\t%2,(%1)\n\t"
- "lw\t%3,4(%1)\n\t"
- "lw\t%4,8(%1)\n\t"
- "lw\t%5,12(%1)\n\t"
- "sw\t%2,(%0)\n\t"
- "sw\t%3,4(%0)\n\t"
- "sw\t%4,8(%0)\n\t"
- "sw\t%5,12(%0)\n\t"
- "lw\t%2,16(%1)\n\t"
- "lw\t%3,20(%1)\n\t"
- "lw\t%4,24(%1)\n\t"
- "lw\t%5,28(%1)\n\t"
- "sw\t%2,16(%0)\n\t"
- "sw\t%3,20(%0)\n\t"
- "sw\t%4,24(%0)\n\t"
- "sw\t%5,28(%0)\n\t"
- "cache\t%9,32(%0)\n\t"
- "daddiu\t%0,64\n\t"
- "daddiu\t%1,64\n\t"
- "lw\t%2,-32(%1)\n\t"
- "lw\t%3,-28(%1)\n\t"
- "lw\t%4,-24(%1)\n\t"
- "lw\t%5,-20(%1)\n\t"
- "sw\t%2,-32(%0)\n\t"
- "sw\t%3,-28(%0)\n\t"
- "sw\t%4,-24(%0)\n\t"
- "sw\t%5,-20(%0)\n\t"
- "lw\t%2,-16(%1)\n\t"
- "lw\t%3,-12(%1)\n\t"
- "lw\t%4,-8(%1)\n\t"
- "lw\t%5,-4(%1)\n\t"
- "sw\t%2,-16(%0)\n\t"
- "sw\t%3,-12(%0)\n\t"
- "sw\t%4,-8(%0)\n\t"
- "bne\t$1,%0,1b\n\t"
- "sw\t%5,-4(%0)\n\t"
- ".set\tmips0\n\t"
- ".set\tat\n\t"
- ".set\treorder"
- :"=r" (dummy1), "=r" (dummy2),
- "=&r" (reg1), "=&r" (reg2), "=&r" (reg3), "=&r" (reg4)
- :"0" (to), "1" (from),
- "I" (PAGE_SIZE),
- "i" (Create_Dirty_Excl_SD));
-}
-
-static void r4k_copy_page_s64(void * to, void * from)
-{
- unsigned long dummy1, dummy2;
- unsigned long reg1, reg2, reg3, reg4;
-
- __asm__ __volatile__(
- ".set\tnoreorder\n\t"
- ".set\tnoat\n\t"
- ".set\tmips3\n\t"
- "daddiu\t$1,%0,%8\n"
- "1:\tcache\t%9,(%0)\n\t"
- "lw\t%2,(%1)\n\t"
- "lw\t%3,4(%1)\n\t"
- "lw\t%4,8(%1)\n\t"
- "lw\t%5,12(%1)\n\t"
- "sw\t%2,(%0)\n\t"
- "sw\t%3,4(%0)\n\t"
- "sw\t%4,8(%0)\n\t"
- "sw\t%5,12(%0)\n\t"
- "lw\t%2,16(%1)\n\t"
- "lw\t%3,20(%1)\n\t"
- "lw\t%4,24(%1)\n\t"
- "lw\t%5,28(%1)\n\t"
- "sw\t%2,16(%0)\n\t"
- "sw\t%3,20(%0)\n\t"
- "sw\t%4,24(%0)\n\t"
- "sw\t%5,28(%0)\n\t"
- "daddiu\t%0,64\n\t"
- "daddiu\t%1,64\n\t"
- "lw\t%2,-32(%1)\n\t"
- "lw\t%3,-28(%1)\n\t"
- "lw\t%4,-24(%1)\n\t"
- "lw\t%5,-20(%1)\n\t"
- "sw\t%2,-32(%0)\n\t"
- "sw\t%3,-28(%0)\n\t"
- "sw\t%4,-24(%0)\n\t"
- "sw\t%5,-20(%0)\n\t"
- "lw\t%2,-16(%1)\n\t"
- "lw\t%3,-12(%1)\n\t"
- "lw\t%4,-8(%1)\n\t"
- "lw\t%5,-4(%1)\n\t"
- "sw\t%2,-16(%0)\n\t"
- "sw\t%3,-12(%0)\n\t"
- "sw\t%4,-8(%0)\n\t"
- "bne\t$1,%0,1b\n\t"
- "sw\t%5,-4(%0)\n\t"
- ".set\tmips0\n\t"
- ".set\tat\n\t"
- ".set\treorder"
- :"=r" (dummy1), "=r" (dummy2),
- "=&r" (reg1), "=&r" (reg2), "=&r" (reg3), "=&r" (reg4)
- :"0" (to), "1" (from),
- "I" (PAGE_SIZE),
- "i" (Create_Dirty_Excl_SD));
-}
-
-static void r4k_copy_page_s128(void * to, void * from)
-{
- unsigned long dummy1, dummy2;
- unsigned long reg1, reg2, reg3, reg4;
-
- __asm__ __volatile__(
- ".set\tnoreorder\n\t"
- ".set\tnoat\n\t"
- ".set\tmips3\n\t"
- "daddiu\t$1,%0,%8\n"
- "1:\tcache\t%9,(%0)\n\t"
- "lw\t%2,(%1)\n\t"
- "lw\t%3,4(%1)\n\t"
- "lw\t%4,8(%1)\n\t"
- "lw\t%5,12(%1)\n\t"
- "sw\t%2,(%0)\n\t"
- "sw\t%3,4(%0)\n\t"
- "sw\t%4,8(%0)\n\t"
- "sw\t%5,12(%0)\n\t"
- "lw\t%2,16(%1)\n\t"
- "lw\t%3,20(%1)\n\t"
- "lw\t%4,24(%1)\n\t"
- "lw\t%5,28(%1)\n\t"
- "sw\t%2,16(%0)\n\t"
- "sw\t%3,20(%0)\n\t"
- "sw\t%4,24(%0)\n\t"
- "sw\t%5,28(%0)\n\t"
- "lw\t%2,32(%1)\n\t"
- "lw\t%3,36(%1)\n\t"
- "lw\t%4,40(%1)\n\t"
- "lw\t%5,44(%1)\n\t"
- "sw\t%2,32(%0)\n\t"
- "sw\t%3,36(%0)\n\t"
- "sw\t%4,40(%0)\n\t"
- "sw\t%5,44(%0)\n\t"
- "lw\t%2,48(%1)\n\t"
- "lw\t%3,52(%1)\n\t"
- "lw\t%4,56(%1)\n\t"
- "lw\t%5,60(%1)\n\t"
- "sw\t%2,48(%0)\n\t"
- "sw\t%3,52(%0)\n\t"
- "sw\t%4,56(%0)\n\t"
- "sw\t%5,60(%0)\n\t"
- "daddiu\t%0,128\n\t"
- "daddiu\t%1,128\n\t"
- "lw\t%2,-64(%1)\n\t"
- "lw\t%3,-60(%1)\n\t"
- "lw\t%4,-56(%1)\n\t"
- "lw\t%5,-52(%1)\n\t"
- "sw\t%2,-64(%0)\n\t"
- "sw\t%3,-60(%0)\n\t"
- "sw\t%4,-56(%0)\n\t"
- "sw\t%5,-52(%0)\n\t"
- "lw\t%2,-48(%1)\n\t"
- "lw\t%3,-44(%1)\n\t"
- "lw\t%4,-40(%1)\n\t"
- "lw\t%5,-36(%1)\n\t"
- "sw\t%2,-48(%0)\n\t"
- "sw\t%3,-44(%0)\n\t"
- "sw\t%4,-40(%0)\n\t"
- "sw\t%5,-36(%0)\n\t"
- "lw\t%2,-32(%1)\n\t"
- "lw\t%3,-28(%1)\n\t"
- "lw\t%4,-24(%1)\n\t"
- "lw\t%5,-20(%1)\n\t"
- "sw\t%2,-32(%0)\n\t"
- "sw\t%3,-28(%0)\n\t"
- "sw\t%4,-24(%0)\n\t"
- "sw\t%5,-20(%0)\n\t"
- "lw\t%2,-16(%1)\n\t"
- "lw\t%3,-12(%1)\n\t"
- "lw\t%4,-8(%1)\n\t"
- "lw\t%5,-4(%1)\n\t"
- "sw\t%2,-16(%0)\n\t"
- "sw\t%3,-12(%0)\n\t"
- "sw\t%4,-8(%0)\n\t"
- "bne\t$1,%0,1b\n\t"
- "sw\t%5,-4(%0)\n\t"
- ".set\tmips0\n\t"
- ".set\tat\n\t"
- ".set\treorder"
- :"=r" (dummy1), "=r" (dummy2),
- "=&r" (reg1), "=&r" (reg2), "=&r" (reg3), "=&r" (reg4)
- :"0" (to), "1" (from),
- "I" (PAGE_SIZE),
- "i" (Create_Dirty_Excl_SD));
-}
-
-
-/*
* If you think for one second that this stuff coming up is a lot
* of bulky code eating too many kernel cache lines. Think _again_.
*
Index: r5432.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/mm/r5432.c,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -d -r1.2 -r1.3
--- r5432.c 2001/07/23 23:53:57 1.2
+++ r5432.c 2001/10/08 16:29:33 1.3
@@ -254,100 +254,6 @@
/* -------------------------------------------------------------------- */
-static void r5432_clear_page_d32(void * page)
-{
- __asm__ __volatile__(
- ".set\tnoreorder\n\t"
- ".set\tnoat\n\t"
- ".set\tmips3\n\t"
- "daddiu\t$1,%0,%2\n"
- "1:\tcache\t%3,(%0)\n\t"
- "sd\t$0,(%0)\n\t"
- "sd\t$0,8(%0)\n\t"
- "sd\t$0,16(%0)\n\t"
- "sd\t$0,24(%0)\n\t"
- "daddiu\t%0,64\n\t"
- "cache\t%3,-32(%0)\n\t"
- "sd\t$0,-32(%0)\n\t"
- "sd\t$0,-24(%0)\n\t"
- "sd\t$0,-16(%0)\n\t"
- "bne\t$1,%0,1b\n\t"
- "sd\t$0,-8(%0)\n\t"
- ".set\tmips0\n\t"
- ".set\tat\n\t"
- ".set\treorder"
- :"=r" (page)
- :"0" (page),
- "I" (PAGE_SIZE),
- "i" (Create_Dirty_Excl_D)
- :"$1","memory");
-}
-
-
-
-/*
- * This is still inefficient. We only can do better if we know the
- * virtual address where the copy will be accessed.
- */
-
-static void r5432_copy_page_d32(void * to, void * from)
-{
- unsigned long dummy1, dummy2;
- unsigned long reg1, reg2, reg3, reg4;
-
- __asm__ __volatile__(
- ".set\tnoreorder\n\t"
- ".set\tnoat\n\t"
- ".set\tmips3\n\t"
- "daddiu\t$1,%0,%8\n"
- "1:\tcache\t%9,(%0)\n\t"
- "lw\t%2,(%1)\n\t"
- "lw\t%3,4(%1)\n\t"
- "lw\t%4,8(%1)\n\t"
- "lw\t%5,12(%1)\n\t"
- "sw\t%2,(%0)\n\t"
- "sw\t%3,4(%0)\n\t"
- "sw\t%4,8(%0)\n\t"
- "sw\t%5,12(%0)\n\t"
- "lw\t%2,16(%1)\n\t"
- "lw\t%3,20(%1)\n\t"
- "lw\t%4,24(%1)\n\t"
- "lw\t%5,28(%1)\n\t"
- "sw\t%2,16(%0)\n\t"
- "sw\t%3,20(%0)\n\t"
- "sw\t%4,24(%0)\n\t"
- "sw\t%5,28(%0)\n\t"
- "cache\t%9,32(%0)\n\t"
- "daddiu\t%0,64\n\t"
- "daddiu\t%1,64\n\t"
- "lw\t%2,-32(%1)\n\t"
- "lw\t%3,-28(%1)\n\t"
- "lw\t%4,-24(%1)\n\t"
- "lw\t%5,-20(%1)\n\t"
- "sw\t%2,-32(%0)\n\t"
- "sw\t%3,-28(%0)\n\t"
- "sw\t%4,-24(%0)\n\t"
- "sw\t%5,-20(%0)\n\t"
- "lw\t%2,-16(%1)\n\t"
- "lw\t%3,-12(%1)\n\t"
- "lw\t%4,-8(%1)\n\t"
- "lw\t%5,-4(%1)\n\t"
- "sw\t%2,-16(%0)\n\t"
- "sw\t%3,-12(%0)\n\t"
- "sw\t%4,-8(%0)\n\t"
- "bne\t$1,%0,1b\n\t"
- "sw\t%5,-4(%0)\n\t"
- ".set\tmips0\n\t"
- ".set\tat\n\t"
- ".set\treorder"
- :"=r" (dummy1), "=r" (dummy2),
- "=&r" (reg1), "=&r" (reg2), "=&r" (reg3), "=&r" (reg4)
- :"0" (to), "1" (from),
- "I" (PAGE_SIZE),
- "i" (Create_Dirty_Excl_D));
-}
-
-
/*
* If you think for one second that this stuff coming up is a lot
* of bulky code eating too many kernel cache lines. Think _again_.
|
