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[Linux-mips-commits]CVS: linux/arch/mips/vr4181/osprey Makefile,1.2,1.3 dbg_io.c,1.1,1.2 prom.c,1.3,1.4 reset.c,1.2,1.3 setup.c,1.3,1.4
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From: Jun S. <ju...@us...> - 2001-10-07 16:57:23
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Update of /cvsroot/linux-mips/linux/arch/mips/vr4181/osprey
In directory usw-pr-cvs1:/tmp/cvs-serv4535/arch/mips/vr4181/osprey
Modified Files:
Makefile dbg_io.c prom.c reset.c setup.c
Log Message:
Update Osprey code. Sync up with OSS CVS tree.
Index: Makefile
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/vr4181/osprey/Makefile,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -d -r1.2 -r1.3
--- Makefile 2001/09/27 23:59:15 1.2
+++ Makefile 2001/10/07 16:57:20 1.3
@@ -11,7 +11,7 @@
.S.o:
$(CC) $(CFLAGS) -c $< -o $*.o
-O_TARGET:= osprey.o
+O_TARGET := osprey.o
obj-y := setup.o prom.o reset.o dbg_io.o
Index: dbg_io.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/vr4181/osprey/dbg_io.c,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- dbg_io.c 2001/09/22 04:27:15 1.1
+++ dbg_io.c 2001/10/07 16:57:20 1.2
@@ -9,37 +9,37 @@
/* --- END OF CONFIG --- */
-#define UART16550_BAUD_2400 2400
-#define UART16550_BAUD_4800 4800
-#define UART16550_BAUD_9600 9600
-#define UART16550_BAUD_19200 19200
-#define UART16550_BAUD_38400 38400
-#define UART16550_BAUD_57600 57600
-#define UART16550_BAUD_115200 115200
+#define UART16550_BAUD_2400 2400
+#define UART16550_BAUD_4800 4800
+#define UART16550_BAUD_9600 9600
+#define UART16550_BAUD_19200 19200
+#define UART16550_BAUD_38400 38400
+#define UART16550_BAUD_57600 57600
+#define UART16550_BAUD_115200 115200
-#define UART16550_PARITY_NONE 0
-#define UART16550_PARITY_ODD 0x08
-#define UART16550_PARITY_EVEN 0x18
-#define UART16550_PARITY_MARK 0x28
-#define UART16550_PARITY_SPACE 0x38
+#define UART16550_PARITY_NONE 0
+#define UART16550_PARITY_ODD 0x08
+#define UART16550_PARITY_EVEN 0x18
+#define UART16550_PARITY_MARK 0x28
+#define UART16550_PARITY_SPACE 0x38
-#define UART16550_DATA_5BIT 0x0
-#define UART16550_DATA_6BIT 0x1
-#define UART16550_DATA_7BIT 0x2
-#define UART16550_DATA_8BIT 0x3
+#define UART16550_DATA_5BIT 0x0
+#define UART16550_DATA_6BIT 0x1
+#define UART16550_DATA_7BIT 0x2
+#define UART16550_DATA_8BIT 0x3
-#define UART16550_STOP_1BIT 0x0
-#define UART16550_STOP_2BIT 0x4
+#define UART16550_STOP_1BIT 0x0
+#define UART16550_STOP_2BIT 0x4
/* ----------------------------------------------------- */
/* === CONFIG === */
/* [jsun] we use the debug board serial port for kdb */
-#define BASE 0xb7fffff0
-#define MAX_BAUD 115200
+#define BASE 0xb7fffff0
+#define MAX_BAUD 115200
-#define REG_OFFSET 1
+#define REG_OFFSET 1
static int remoteDebugInitialized = 1;
@@ -47,27 +47,27 @@
/* register offset */
-#define OFS_RCV_BUFFER 0
-#define OFS_TRANS_HOLD 0
-#define OFS_SEND_BUFFER 0
-#define OFS_INTR_ENABLE (1*REG_OFFSET)
-#define OFS_INTR_ID (2*REG_OFFSET)
-#define OFS_DATA_FORMAT (3*REG_OFFSET)
-#define OFS_LINE_CONTROL (3*REG_OFFSET)
-#define OFS_MODEM_CONTROL (4*REG_OFFSET)
-#define OFS_RS232_OUTPUT (4*REG_OFFSET)
-#define OFS_LINE_STATUS (5*REG_OFFSET)
-#define OFS_MODEM_STATUS (6*REG_OFFSET)
-#define OFS_RS232_INPUT (6*REG_OFFSET)
-#define OFS_SCRATCH_PAD (7*REG_OFFSET)
+#define OFS_RCV_BUFFER 0
+#define OFS_TRANS_HOLD 0
+#define OFS_SEND_BUFFER 0
+#define OFS_INTR_ENABLE (1*REG_OFFSET)
+#define OFS_INTR_ID (2*REG_OFFSET)
+#define OFS_DATA_FORMAT (3*REG_OFFSET)
+#define OFS_LINE_CONTROL (3*REG_OFFSET)
+#define OFS_MODEM_CONTROL (4*REG_OFFSET)
+#define OFS_RS232_OUTPUT (4*REG_OFFSET)
+#define OFS_LINE_STATUS (5*REG_OFFSET)
+#define OFS_MODEM_STATUS (6*REG_OFFSET)
+#define OFS_RS232_INPUT (6*REG_OFFSET)
+#define OFS_SCRATCH_PAD (7*REG_OFFSET)
-#define OFS_DIVISOR_LSB (0*REG_OFFSET)
-#define OFS_DIVISOR_MSB (1*REG_OFFSET)
+#define OFS_DIVISOR_LSB (0*REG_OFFSET)
+#define OFS_DIVISOR_MSB (1*REG_OFFSET)
/* memory-mapped read/write of the port */
-#define UART16550_READ(y) (*((volatile uint8*)(BASE + y)))
-#define UART16550_WRITE(y, z) ((*((volatile uint8*)(BASE + y))) = z)
+#define UART16550_READ(y) (*((volatile uint8*)(BASE + y)))
+#define UART16550_WRITE(y, z) ((*((volatile uint8*)(BASE + y))) = z)
void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop)
{
Index: prom.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/vr4181/osprey/prom.c,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- prom.c 2001/09/27 23:59:15 1.3
+++ prom.c 2001/10/07 16:57:20 1.4
@@ -1,17 +1,15 @@
-/***********************************************************************
- *
+/*
* Copyright 2001 MontaVista Software Inc.
* Author: js...@mv... or js...@ju...
*
* arch/mips/vr4181/osprey/prom.c
* prom code for osprey.
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
- ***********************************************************************
*/
#include <linux/init.h>
@@ -32,15 +30,15 @@
void __init prom_init()
{
strcpy(arcs_cmdline, "ip=bootp ");
- strcat(arcs_cmdline, "ether=46,0x03fe0300,eth0 ");
- // strcpy(arcs_cmdline, "ether=0,0x0300,eth0 "
+ strcat(arcs_cmdline, "ether=46,0x03fe0300,eth0 ");
+ // strcpy(arcs_cmdline, "ether=0,0x0300,eth0 "
// strcat(arcs_cmdline, "video=vr4181fb:xres:240,yres:320,bpp:8 ");
- mips_machgroup = MACH_GROUP_NEC_VR41XX;
- mips_machtype = MACH_NEC_OSPREY;
+ mips_machgroup = MACH_GROUP_NEC_VR41XX;
+ mips_machtype = MACH_NEC_OSPREY;
- /* 16MB fixed */
- add_memory_region(0, 16 << 20, BOOT_MEM_RAM);
+ /* 16MB fixed */
+ add_memory_region(0, 16 << 20, BOOT_MEM_RAM);
}
void __init prom_free_prom_memory(void)
Index: reset.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/vr4181/osprey/reset.c,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -d -r1.2 -r1.3
--- reset.c 2001/09/22 16:35:15 1.2
+++ reset.c 2001/10/07 16:57:20 1.3
@@ -1,6 +1,6 @@
/*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
@@ -30,7 +30,7 @@
printk(KERN_NOTICE "\n** You can safely turn off the power\n");
while (1)
__asm__(".set\tmips3\n\t"
- "wait\n\t"
+ "wait\n\t"
".set\tmips0");
}
Index: setup.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/vr4181/osprey/setup.c,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- setup.c 2001/10/01 19:33:00 1.3
+++ setup.c 2001/10/07 16:57:20 1.4
@@ -6,6 +6,9 @@
* Copyright (C) 1999 Bradley D. LaRonde
* Copyright (C) 1999, 2000 Michael Klar
*
+ * Copyright 2001 MontaVista Software Inc.
+ * Author: js...@mv... or js...@ju...
+ *
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
@@ -21,63 +24,11 @@
#include <asm/vr4181/vr4181.h>
#include <asm/io.h>
-#include <linux/pc_keyb.h>
-extern struct kbd_ope no_kbd_ops;
-struct semaphore vr4181_dma_sem;
-
-// This enables the CF hacks below, to be replaced with real CF driver eventually
-#if defined(CONFIG_EVEREX_FREESTYLE)
-#define CF_HACK
-#else
-// If CF doesn't work on your device, try changing this to #define:
-#undef CF_HACK
-#endif
-
-#ifdef CONFIG_TCIC
-#define TCIC_BASE 0x240
-
-#define TCIC_MODE 0x08
-#define TCIC_AUX 0x0E
-
-#define TCIC_MODE_PGMMASK 0x1f
-#define TCIC_AUX_ILOCK (6<<5)
-#define TCIC_ILOCK_CRESET 0x04
-#endif
-
extern void nec_osprey_restart(char* c);
extern void nec_osprey_halt(void);
extern void nec_osprey_power_off(void);
-#if defined(CF_HACK) || defined(CONFIG_I82365)
-void __init put_cf_reg(unsigned char reg, unsigned char val)
-{
-#ifdef CONFIG_CPU_VR4181
- *VR4181_PCCARDINDEX = reg;
- barrier();
- *VR4181_PCCARDDATA = val;
-#else
- outb(reg, 0x3e0);
- outb(val, 0x3e1);
-#endif
-}
-#endif
-
-#if defined(CONFIG_NEC_OSPREY) || defined(CONFIG_IBM_WORKPAD) || \
- defined(CONFIG_NEC_MOBILEGEAR2_R300) || \
- defined(CONFIG_NEC_MOBILEGEAR2_R310) || \
- defined(CONFIG_NEC_MOBILEGEAR2_R430) || \
- defined(CONFIG_NEC_MOBILEGEAR2_R530) || \
- defined(CONFIG_NEC_MOBILEGEAR2_R700) || \
- defined(CONFIG_NEC_MOBILEGEAR2_R730) || \
- defined(CONFIG_DOCOMO_SIGMARION) || \
- defined(CONFIG_AGENDA_VR3)
-// extern void platdep_setup(void);
-void platdep_setup(void) {}
-#else
-void platdep_setup(void) {}
-#endif
-
extern void vr4181_init_serial(void);
extern void vr4181_init_time(void);
@@ -89,91 +40,17 @@
vr4181_init_serial();
vr4181_init_time();
-#ifdef CONFIG_BLK_DEV_IDE
- ide_ops = &vr4181_ide_ops;
-#endif
-
#ifdef CONFIG_FB
conswitchp = &dummy_con;
#endif
- // reset the PC card, and power off
-#ifdef CONFIG_I82365
- put_cf_reg(0x03, 0x20); // socket 0
- put_cf_reg(0x43, 0x20); // socket 1
- put_cf_reg(0x02, 0x00); // socket 0
- put_cf_reg(0x42, 0x00); // socket 1
-#endif
-#ifdef CONFIG_TCIC
-{
- u_char mode;
- mode = (inb(TCIC_BASE+TCIC_MODE) & TCIC_MODE_PGMMASK) | TCIC_AUX_ILOCK;
- outb(mode, TCIC_BASE+TCIC_MODE);
- outb(TCIC_ILOCK_CRESET, TCIC_BASE+TCIC_AUX);
-}
-#endif
-
-#ifdef CF_HACK
- // this is a nasty hack to initialize the CF registers, eventually this
- // is to be replaced with a real CF controller driver
- {
- unsigned char i;
- unsigned char cfinitdata[] = { 0x90, 0x63, 0x00, 0x35, 0x00, 0x55,
- 0x76, 0x03, 0x77, 0x03, 0x70, 0x01, 0x78, 0x01, 0x10, 0x00,
- 0x1f, 0x00, 0xf0, 0x7f, 0x00, 0x00, 0x20, 0x00, 0xe4, 0x00,
- 0xe0, 0x3f, 0x00, 0x02, 0xe5, 0x00, 0xed, 0x00, 0x1b, 0x3f,
- 0x00, 0x00, 0xee, 0x00, 0xf6, 0x00, 0x00, 0x00, 0x00, 0x01,
- 0xf7, 0x00, 0xff, 0x00, 0x00, 0x00 };
-
-#ifdef CONFIG_CPU_VR4181
- // Enable CF, not key scan.
- *VR4181_KEYEN = 0;
-
- // Unmask all CF IRQs for now except for IRQ 3 (which makes it fail)
- // I think the bit sense in reversed from what User Manual states
- *VR4181_INTMSKREG = 0xdeb0;
-
- // Set CF wait states.
- *VR4181_CFG_REG_1 = 1;
-#else
-#warning "Generic CF hack in use, assuming non-i82365 registers set up prior to boot"
-#endif
-
- put_cf_reg(0x02, 0x10);
- udelay(1);
-
- for (i = 0x02; i < 0x36; i++)
- put_cf_reg(i, cfinitdata[i-2]);
-
- // enable the IO and mem windows, now that start and stop values set up
- put_cf_reg(0x06, 0xdf);
-
- // reset the card
- put_cf_reg(0x03, 0x23);
- udelay(1);
- put_cf_reg(0x03, 0x63);
- mdelay(30);
-
- // now set up CF config register (this assumes it is a CF card...)
- writeb(0x43, ioremap(0x10200, 1));
- }
-#endif
-
_machine_restart = nec_osprey_restart;
_machine_halt = nec_osprey_halt;
_machine_power_off = nec_osprey_power_off;
/* setup resource limit */
ioport_resource.end = 0xffffffff;
- iomem_resource.end = 0xffffffff;
-
- // Insure that vr4181_dma_sem is initialized as unlocked, even
- // in the case of a failed hibernate/wakeup:
- init_MUTEX(&vr4181_dma_sem);
-
- // Do platform-dependent setup.
- // This is mostly stuff that doesn't fit well anywhere else.
- platdep_setup();
+ iomem_resource.end = 0xffffffff;
/* [jsun] hack */
/*
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