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[Linux-mips-commits]CVS: linux/arch/mips/vr4181/common int_handler.S,1.2,1.3 irq.c,1.5,1.6 serial.c,1.2,1.3 time.c,1.3,1.4
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From: Jun S. <ju...@us...> - 2001-10-07 16:57:23
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Update of /cvsroot/linux-mips/linux/arch/mips/vr4181/common
In directory usw-pr-cvs1:/tmp/cvs-serv4535/arch/mips/vr4181/common
Modified Files:
int_handler.S irq.c serial.c time.c
Log Message:
Update Osprey code. Sync up with OSS CVS tree.
Index: int_handler.S
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/vr4181/common/int_handler.S,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -d -r1.2 -r1.3
--- int_handler.S 2001/09/29 00:42:25 1.2
+++ int_handler.S 2001/10/07 16:57:19 1.3
@@ -1,13 +1,5 @@
/*
- * linux/arch/mips/vr4181/common/int_handler.S
- *
- * Copyright (C) 1995, 1996, 1997 Paul M. Antoine and Harald Koerfgen
- *
- * Written by Ralf Baechle and Andreas Busse, modified for DECStation
- * support by Paul Antoine and Harald Koerfgen.
- *
- * completly rewritten:
- * Copyright (C) 1998 Harald Koerfgen
+ * arch/mips/vr4181/common/int_handler.S
*
* Adapted to the VR4181 and almost entirely rewritten:
* Copyright (C) 1999 Bradley D. LaRonde and Michael Klar
@@ -47,86 +39,86 @@
.set at
.set noreorder
- mfc0 t0, CP0_CAUSE
- mfc0 t2, CP0_STATUS
+ mfc0 t0, CP0_CAUSE
+ mfc0 t2, CP0_STATUS
- and t0, t2
+ and t0, t2
/* we check IP3 first; it happens most frequently */
- andi t1, t0, STATUSF_IP3
- bnez t1, ll_cpu_ip3
- andi t1, t0, STATUSF_IP2
- bnez t1, ll_cpu_ip2
- andi t1, t0, STATUSF_IP7 /* cpu timer */
- bnez t1, ll_cputimer_irq
- andi t1, t0, STATUSF_IP4
- bnez t1, ll_cpu_ip4
- andi t1, t0, STATUSF_IP5
- bnez t1, ll_cpu_ip5
- andi t1, t0, STATUSF_IP6
- bnez t1, ll_cpu_ip6
- andi t1, t0, STATUSF_IP0 /* software int 0 */
- bnez t1, ll_cpu_ip0
- andi t1, t0, STATUSF_IP1 /* software int 1 */
- bnez t1, ll_cpu_ip1
- nop
+ andi t1, t0, STATUSF_IP3
+ bnez t1, ll_cpu_ip3
+ andi t1, t0, STATUSF_IP2
+ bnez t1, ll_cpu_ip2
+ andi t1, t0, STATUSF_IP7 /* cpu timer */
+ bnez t1, ll_cputimer_irq
+ andi t1, t0, STATUSF_IP4
+ bnez t1, ll_cpu_ip4
+ andi t1, t0, STATUSF_IP5
+ bnez t1, ll_cpu_ip5
+ andi t1, t0, STATUSF_IP6
+ bnez t1, ll_cpu_ip6
+ andi t1, t0, STATUSF_IP0 /* software int 0 */
+ bnez t1, ll_cpu_ip0
+ andi t1, t0, STATUSF_IP1 /* software int 1 */
+ bnez t1, ll_cpu_ip1
+ nop
.set reorder
do_spurious:
- j spurious_interrupt
+ j spurious_interrupt
/*
* regular CPU irqs
*/
ll_cputimer_irq:
- li a0, VR4181_IRQ_TIMER
- move a1, sp
- jal do_IRQ
- j ret_from_irq
+ li a0, VR4181_IRQ_TIMER
+ move a1, sp
+ jal do_IRQ
+ j ret_from_irq
ll_cpu_ip0:
- li a0, VR4181_IRQ_SW1
- move a1, sp
- jal do_IRQ
- j ret_from_irq
+ li a0, VR4181_IRQ_SW1
+ move a1, sp
+ jal do_IRQ
+ j ret_from_irq
ll_cpu_ip1:
- li a0, VR4181_IRQ_SW2
- move a1, sp
- jal do_IRQ
- j ret_from_irq
+ li a0, VR4181_IRQ_SW2
+ move a1, sp
+ jal do_IRQ
+ j ret_from_irq
ll_cpu_ip3:
- li a0, VR4181_IRQ_INT1
- move a1, sp
- jal do_IRQ
- j ret_from_irq
+ li a0, VR4181_IRQ_INT1
+ move a1, sp
+ jal do_IRQ
+ j ret_from_irq
ll_cpu_ip4:
- li a0, VR4181_IRQ_INT2
- move a1, sp
- jal do_IRQ
- j ret_from_irq
+ li a0, VR4181_IRQ_INT2
+ move a1, sp
+ jal do_IRQ
+ j ret_from_irq
ll_cpu_ip5:
- li a0, VR4181_IRQ_INT3
- move a1, sp
- jal do_IRQ
- j ret_from_irq
+ li a0, VR4181_IRQ_INT3
+ move a1, sp
+ jal do_IRQ
+ j ret_from_irq
ll_cpu_ip6:
- li a0, VR4181_IRQ_INT4
- move a1, sp
- jal do_IRQ
- j ret_from_irq
+ li a0, VR4181_IRQ_INT4
+ move a1, sp
+ jal do_IRQ
+ j ret_from_irq
/*
* One of the sys irq has happend.
*
* In the interest of speed, we first determine in the following order
* which 16-irq block have pending interrupts:
- * sysint1 (16 sources, including cascading intrs from GPIO)
+ * sysint1 (16 sources, including cascading intrs from GPIO)
* sysint2
* gpio (16 intr sources)
*
@@ -135,8 +127,8 @@
ll_cpu_ip2:
lui t3,%hi(VR4181_SYSINT1REG)
- lhu t0,%lo(VR4181_SYSINT1REG)(t3)
- lhu t2,%lo(VR4181_MSYSINT1REG)(t3)
+ lhu t0,%lo(VR4181_SYSINT1REG)(t3)
+ lhu t2,%lo(VR4181_MSYSINT1REG)(t3)
and t0, 0xfffb /* hack - remove RTC Long 1 intr */
and t0, t2
beqz t0, check_sysint2
@@ -151,24 +143,22 @@
check_sysint2:
- lhu t0,%lo(VR4181_SYSINT2REG)(t3)
- lhu t2,%lo(VR4181_MSYSINT2REG)(t3)
+ lhu t0,%lo(VR4181_SYSINT2REG)(t3)
+ lhu t2,%lo(VR4181_MSYSINT2REG)(t3)
and t0, 0xfffe /* hack - remove RTC Long 2 intr */
and t0, t2
li a0, VR4181_SYS_IRQ_BASE + 16 - 1
j check_16
check_gpio_int:
- lui t3,%hi(VR4181_GPINTMSK)
- lhu t0,%lo(VR4181_GPINTMSK)(t3)
- lhu t2,%lo(VR4181_GPINTSTAT)(t3)
+ lui t3,%hi(VR4181_GPINTMSK)
+ lhu t0,%lo(VR4181_GPINTMSK)(t3)
+ lhu t2,%lo(VR4181_GPINTSTAT)(t3)
xori t0, 0xffff /* why? reverse logic? */
and t0, t2
li a0, VR4181_GPIO_IRQ_BASE - 1
j check_16
-
-
/*
* When we reach check_16, we have 16-bit status in t0 and base irq number
* in a0.
@@ -181,7 +171,6 @@
addi a0, 8
j check_8
-
/*
* When we reach check_8, we have 8-bit status in t0 and base irq number
* in a0.
@@ -213,5 +202,5 @@
jal do_IRQ
j ret_from_irq
-
+
END(vr4181_handle_irq)
Index: irq.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/vr4181/common/irq.c,v
retrieving revision 1.5
retrieving revision 1.6
diff -u -d -r1.5 -r1.6
--- irq.c 2001/09/29 00:42:25 1.5
+++ irq.c 2001/10/07 16:57:19 1.6
@@ -7,13 +7,12 @@
*
* Credits to Bradley D. LaRonde and Michael Klar for writing the original
* irq.c file which was derived from the common irq.c file.
- *
+ *
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
*/
-
#include <linux/types.h>
#include <linux/init.h>
#include <linux/kernel_stat.h>
@@ -76,19 +75,19 @@
return 0;
}
-#define sys_irq_shutdown sys_irq_disable
-#define sys_irq_ack sys_irq_disable
-#define sys_irq_end sys_irq_enable
+#define sys_irq_shutdown sys_irq_disable
+#define sys_irq_ack sys_irq_disable
+#define sys_irq_end sys_irq_enable
static hw_irq_controller sys_irq_controller = {
- "vr4181_sys_irq",
- sys_irq_startup,
- sys_irq_shutdown,
- sys_irq_enable,
- sys_irq_disable,
- sys_irq_ack,
- sys_irq_end,
- NULL /* no affinity stuff for UP */
+ "vr4181_sys_irq",
+ sys_irq_startup,
+ sys_irq_shutdown,
+ sys_irq_enable,
+ sys_irq_disable,
+ sys_irq_ack,
+ sys_irq_end,
+ NULL /* no affinity stuff for UP */
};
/* ---------------------- gpio irq ------------------------ */
@@ -149,17 +148,17 @@
}
}
-#define gpio_irq_end gpio_irq_enable
+#define gpio_irq_end gpio_irq_enable
static hw_irq_controller gpio_irq_controller = {
- "vr4181_gpio_irq",
- gpio_irq_startup,
- gpio_irq_shutdown,
- gpio_irq_enable,
- gpio_irq_disable,
- gpio_irq_ack,
- gpio_irq_end,
- NULL /* no affinity stuff for UP */
+ "vr4181_gpio_irq",
+ gpio_irq_startup,
+ gpio_irq_shutdown,
+ gpio_irq_enable,
+ gpio_irq_disable,
+ gpio_irq_ack,
+ gpio_irq_end,
+ NULL /* no affinity stuff for UP */
};
/* --------------------- IRQ init stuff ---------------------- */
@@ -187,36 +186,36 @@
/* init sys irqs */
sys_irq_base = VR4181_SYS_IRQ_BASE;
for (i=sys_irq_base; i < sys_irq_base + VR4181_NUM_SYS_IRQ; i++) {
- irq_desc[i].status = IRQ_DISABLED;
- irq_desc[i].action = NULL;
- irq_desc[i].depth = 1;
- irq_desc[i].handler = &sys_irq_controller;
- }
+ irq_desc[i].status = IRQ_DISABLED;
+ irq_desc[i].action = NULL;
+ irq_desc[i].depth = 1;
+ irq_desc[i].handler = &sys_irq_controller;
+ }
/* init gpio irqs */
gpio_irq_base = VR4181_GPIO_IRQ_BASE;
for (i=gpio_irq_base; i < gpio_irq_base + VR4181_NUM_GPIO_IRQ; i++) {
- irq_desc[i].status = IRQ_DISABLED;
- irq_desc[i].action = NULL;
- irq_desc[i].depth = 1;
- irq_desc[i].handler = &gpio_irq_controller;
- }
+ irq_desc[i].status = IRQ_DISABLED;
+ irq_desc[i].action = NULL;
+ irq_desc[i].depth = 1;
+ irq_desc[i].handler = &gpio_irq_controller;
+ }
- /* Default all ICU IRQs to off ... */
- *VR4181_MSYSINT1REG = 0;
- *VR4181_MSYSINT2REG = 0;
+ /* Default all ICU IRQs to off ... */
+ *VR4181_MSYSINT1REG = 0;
+ *VR4181_MSYSINT2REG = 0;
- /* We initialize the level 2 ICU registers to all bits disabled. */
- *VR4181_MPIUINTREG = 0;
- *VR4181_MAIUINTREG = 0;
- *VR4181_MKIUINTREG = 0;
+ /* We initialize the level 2 ICU registers to all bits disabled. */
+ *VR4181_MPIUINTREG = 0;
+ *VR4181_MAIUINTREG = 0;
+ *VR4181_MKIUINTREG = 0;
/* disable all GPIO intrs */
- *VR4181_GPINTMSK = 0xffff;
+ *VR4181_GPINTMSK = 0xffff;
- /* vector handler. What these do is register the IRQ as non-sharable */
- setup_irq(VR4181_IRQ_INT0, &cascade);
- setup_irq(VR4181_IRQ_GIU, &cascade);
+ /* vector handler. What these do is register the IRQ as non-sharable */
+ setup_irq(VR4181_IRQ_INT0, &cascade);
+ setup_irq(VR4181_IRQ_GIU, &cascade);
/*
* RTC interrupts are interesting. They have two destinations.
@@ -225,11 +224,11 @@
* We enable them here, but timer routine will register later
* with CPU IP3/IP4.
*/
- setup_irq(VR4181_IRQ_RTCL1, &reserved);
- setup_irq(VR4181_IRQ_RTCL2, &reserved);
+ setup_irq(VR4181_IRQ_RTCL1, &reserved);
+ setup_irq(VR4181_IRQ_RTCL2, &reserved);
#ifdef CONFIG_REMOTE_DEBUG
- printk("Setting debug traps - please connect the remote debugger.\n");
+ printk("Setting debug traps - please connect the remote debugger.\n");
set_debug_traps();
@@ -237,4 +236,3 @@
breakpoint();
#endif
}
-
Index: serial.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/vr4181/common/serial.c,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -d -r1.2 -r1.3
--- serial.c 2001/09/25 19:57:07 1.2
+++ serial.c 2001/10/07 16:57:19 1.3
@@ -5,8 +5,8 @@
* arch/mips/vr4181/common/serial.c
* initialize serial port on vr4181.
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
@@ -15,8 +15,8 @@
/*
* [jsun, 010925]
* You need to make sure rs_table has at least one element in
- * drivers/char/serial.c file. There is no good way to do it right
- * now. A workaround is to include CONFIG_SERIAL_MANY_PORTS in your
+ * drivers/char/serial.c file. There is no good way to do it right
+ * now. A workaround is to include CONFIG_SERIAL_MANY_PORTS in your
* configure file, which would gives you 64 ports and wastes 11K ram.
*/
@@ -29,21 +29,21 @@
void __init vr4181_init_serial(void)
{
- struct serial_struct s;
+ struct serial_struct s;
/* turn on UART clock */
*VR4181_CMUCLKMSK |= VR4181_CMUCLKMSK_MSKSIU;
- /* clear memory */
- memset(&s, 0, sizeof(s));
+ /* clear memory */
+ memset(&s, 0, sizeof(s));
- s.line = 0; /* we set the first one */
- s.baud_base = 1152000;
- s.irq = VR4181_IRQ_SIU;
- s.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST; /* STD_COM_FLAGS */
- s.iomem_base = (u8*)VR4181_SIURB;
- s.iomem_reg_shift = 0;
- s.io_type = SERIAL_IO_MEM;
+ s.line = 0; /* we set the first one */
+ s.baud_base = 1152000;
+ s.irq = VR4181_IRQ_SIU;
+ s.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST; /* STD_COM_FLAGS */
+ s.iomem_base = (u8*)VR4181_SIURB;
+ s.iomem_reg_shift = 0;
+ s.io_type = SERIAL_IO_MEM;
if (early_serial_setup(&s) != 0) {
panic("vr4181_init_serial() failed!\n");
}
Index: time.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/vr4181/common/time.c,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- time.c 2001/10/01 19:32:59 1.3
+++ time.c 2001/10/07 16:57:19 1.4
@@ -2,11 +2,11 @@
* Copyright 2001 MontaVista Software Inc.
* Author: js...@mv... or js...@ju...
*
- * rtc and time ops for vr4181. Part of code is drived from
- * linux-vr, originally written by Bradley D. LaRonde & Michael Klar.
+ * rtc and time ops for vr4181. Part of code is drived from
+ * linux-vr, originally written by Bradley D. LaRonde & Michael Klar.
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
@@ -35,48 +35,48 @@
static inline unsigned short
read_time_reg(volatile unsigned short *reg)
{
- unsigned short value;
- do {
- value = *reg;
- barrier();
- } while (value != *reg);
- return value;
+ unsigned short value;
+ do {
+ value = *reg;
+ barrier();
+ } while (value != *reg);
+ return value;
}
static unsigned long
vr4181_rtc_get_time(void)
{
- unsigned short regh, regm, regl;
+ unsigned short regh, regm, regl;
- // why this crazy order, you ask? to guarantee that neither m
- // nor l wrap before all 3 read
- do {
- regm = read_time_reg(VR4181_ETIMEMREG);
- barrier();
- regh = read_time_reg(VR4181_ETIMEHREG);
- barrier();
- regl = read_time_reg(VR4181_ETIMELREG);
- } while (regm != read_time_reg(VR4181_ETIMEMREG));
- return ((regh << 17) | (regm << 1) | (regl >> 15));
+ // why this crazy order, you ask? to guarantee that neither m
+ // nor l wrap before all 3 read
+ do {
+ regm = read_time_reg(VR4181_ETIMEMREG);
+ barrier();
+ regh = read_time_reg(VR4181_ETIMEHREG);
+ barrier();
+ regl = read_time_reg(VR4181_ETIMELREG);
+ } while (regm != read_time_reg(VR4181_ETIMEMREG));
+ return ((regh << 17) | (regm << 1) | (regl >> 15));
}
static int
vr4181_rtc_set_time(unsigned long timeval)
{
- unsigned short intreg;
- unsigned long flags;
+ unsigned short intreg;
+ unsigned long flags;
- spin_lock_irqsave(&rtc_lock, flags);
- intreg = *VR4181_RTCINTREG & 0x05;
- barrier();
- *VR4181_ETIMELREG = timeval << 15;
- *VR4181_ETIMEMREG = timeval >> 1;
- *VR4181_ETIMEHREG = timeval >> 17;
- barrier();
- // assume that any ints that just triggered are invalid, since the
- // time value is written non-atomically in 3 separate regs
- *VR4181_RTCINTREG = 0x05 ^ intreg;
- spin_unlock_irqrestore(&rtc_lock, flags);
+ spin_lock_irqsave(&rtc_lock, flags);
+ intreg = *VR4181_RTCINTREG & 0x05;
+ barrier();
+ *VR4181_ETIMELREG = timeval << 15;
+ *VR4181_ETIMEMREG = timeval >> 1;
+ *VR4181_ETIMEHREG = timeval >> 17;
+ barrier();
+ // assume that any ints that just triggered are invalid, since the
+ // time value is written non-atomically in 3 separate regs
+ *VR4181_RTCINTREG = 0x05 ^ intreg;
+ spin_unlock_irqrestore(&rtc_lock, flags);
return 0;
}
@@ -91,7 +91,7 @@
static void
vr4181_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
{
- /* Clear the interrupt. */
+ /* Clear the interrupt. */
*VR4181_RTCINTREG = 0x2;
/* call the generic one */
@@ -103,7 +103,7 @@
* vr4181_time_init:
*
* We pick the following choices:
- * . we use elapsed timer as the RTC. We set some reasonable init data since
+ * . we use elapsed timer as the RTC. We set some reasonable init data since
* it does not persist across reset
* . we use RTC1 as the system timer interrupt source.
* . we use CPU counter for fast_gettimeoffset and we calivrate the cpu
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