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[Linux-mips-commits]CVS: linux/include/asm-mips/ddb5xxx ddb5476.h,NONE,1.1 ddb5477.h,1.2,1.3 ddb5xxx.h,1.1.1.1,1.2
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From: Jun S. <ju...@us...> - 2001-10-07 05:40:25
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Update of /cvsroot/linux-mips/linux/include/asm-mips/ddb5xxx In directory usw-pr-cvs1:/tmp/cvs-serv16561/include/asm-mips/ddb5xxx Modified Files: ddb5477.h ddb5xxx.h Added Files: ddb5476.h Log Message: Update DDB5476 and sync up with oss tree. --- NEW FILE: ddb5476.h --- /* * header file specific for ddb5476 * * Copyright (C) 2001 MontaVista Software Inc. * Author: Jun Sun, js...@mv... or js...@ju... * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. * */ /* * Memory map (physical address) * * Note most of the following address must be properly aligned by the * corresponding size. For example, if PCI_IO_SIZE is 16MB, then * PCI_IO_BASE must be aligned along 16MB boundary. */ #define DDB_SDRAM_BASE 0x00000000 #define DDB_SDRAM_SIZE 0x04000000 /* 64MB */ #define DDB_DCS3_BASE 0x04000000 /* flash 1 */ #define DDB_DCS3_SIZE 0x01000000 /* 16MB */ #define DDB_DCS2_BASE 0x05000000 /* flash 2 */ #define DDB_DCS2_SIZE 0x01000000 /* 16MB */ #define DDB_PCI_IO_BASE 0x06000000 #define DDB_PCI_IO_SIZE 0x02000000 /* 32 MB */ #define DDB_PCI_MEM_BASE 0x08000000 #define DDB_PCI_MEM_SIZE 0x08000000 /* 128 MB */ #define DDB_DCS5_BASE 0x13000000 /* DDB status regs */ #define DDB_DCS5_SIZE 0x00200000 /* 2MB, 8-bit */ #define DDB_DCS4_BASE 0x14000000 /* DDB control regs */ #define DDB_DCS4_SIZE 0x00200000 /* 2MB, 8-bit */ #define DDB_INTCS_BASE 0x1fa00000 /* VRC5476 control regs */ #define DDB_INTCS_SIZE 0x00200000 /* 2MB */ #define DDB_BOOTCS_BASE 0x1fc00000 /* Boot ROM / EPROM /Flash */ #define DDB_BOOTCS_SIZE 0x00200000 /* 2 MB - doc says 4MB */ /* aliases */ #define DDB_PCI_CONFIG_BASE DDB_PCI_MEM_BASE #define DDB_PCI_CONFIG_SIZE DDB_PCI_MEM_SIZE /* PCI intr ack share PCIW0 with PCI IO */ #define DDB_PCI_IACK_BASE DDB_PCI_IO_BASE /* * Interrupt mapping * * We have three interrupt controllers: * * . CPU itself - 8 sources * . i8259 - 16 sources * . vrc5476 - 16 sources * * They connected as follows: * all vrc5476 interrupts are routed to cpu IP2 (by software setting) * all i2869 are routed to INTC in vrc5476 (by hardware connection) * * All VRC5476 PCI interrupts are level-triggered (no ack needed). * All PCI irq but INTC are active low. */ /* * irq number block assignment */ #define NUM_CPU_IRQ 8 #define NUM_I8259_IRQ 16 #define NUM_VRC5476_IRQ 16 #define DDB_IRQ_BASE 0 #define I8259_IRQ_BASE DDB_IRQ_BASE #define VRC5476_IRQ_BASE (I8259_IRQ_BASE + NUM_I8259_IRQ) #define CPU_IRQ_BASE (VRC5476_IRQ_BASE + NUM_VRC5476_IRQ) /* * vrc5476 irq defs, see page 52-64 of Vrc5074 system controller manual */ #define VRC5476_IRQ_CPCE 0 /* cpu parity error */ #define VRC5476_IRQ_CNTD 1 /* cpu no target */ #define VRC5476_IRQ_MCE 2 /* memory check error */ #define VRC5476_IRQ_DMA 3 /* DMA */ #define VRC5476_IRQ_UART 4 /* vrc5476 builtin UART, not used */ #define VRC5476_IRQ_WDOG 5 /* watchdog timer */ #define VRC5476_IRQ_GPT 6 /* general purpose timer */ #define VRC5476_IRQ_LBRT 7 /* local bus read timeout */ #define VRC5476_IRQ_INTA 8 /* PCI INT #A */ #define VRC5476_IRQ_INTB 9 /* PCI INT #B */ #define VRC5476_IRQ_INTC 10 /* PCI INT #C */ #define VRC5476_IRQ_INTD 11 /* PCI INT #D */ #define VRC5476_IRQ_INTE 12 /* PCI INT #E */ #define VRC5476_IRQ_RESERVED_13 13 /* reserved */ #define VRC5476_IRQ_PCIS 14 /* PCI SERR # */ #define VRC5476_IRQ_PCI 15 /* PCI internal error */ /* * i2859 irq assignment */ #define I8259_IRQ_RESERVED_0 0 #define I8259_IRQ_KEYBOARD 1 /* M1543 default */ #define I8259_IRQ_CASCADE 2 #define I8259_IRQ_UART_B 3 /* M1543 default, may conflict with RTC according to schematic diagram */ #define I8259_IRQ_UART_A 4 /* M1543 default */ #define I8259_IRQ_PARALLEL 5 /* M1543 default */ #define I8259_IRQ_RESERVED_6 6 #define I8259_IRQ_RESERVED_7 7 #define I8259_IRQ_RTC 8 /* who set this? */ #define I8259_IRQ_USB 9 /* ddb_setup */ #define I8259_IRQ_PMU 10 /* ddb_setup */ #define I8259_IRQ_RESERVED_11 11 #define I8259_IRQ_RESERVED_12 12 /* m1543_irq_setup */ #define I8259_IRQ_RESERVED_13 13 #define I8259_IRQ_HDC1 14 /* default and ddb_setup */ #define I8259_IRQ_HDC2 15 /* default */ /* * misc */ #define VRC5476_I8259_CASCADE VRC5476_IRQ_INTC #define CPU_VRC5476_CASCADE 2 #define is_i8259_irq(irq) ((irq) < NUM_I8259_IRQ) #define nile4_to_irq(n) ((n)+NUM_I8259_IRQ) #define irq_to_nile4(n) ((n)-NUM_I8259_IRQ) /* * low-level irq functions */ #ifndef _LANGUAGE_ASSEMBLY extern void nile4_map_irq(int nile4_irq, int cpu_irq); extern void nile4_map_irq_all(int cpu_irq); extern void nile4_enable_irq(int nile4_irq); extern void nile4_disable_irq(int nile4_irq); extern void nile4_disable_irq_all(void); extern u16 nile4_get_irq_stat(int cpu_irq); extern void nile4_enable_irq_output(int cpu_irq); extern void nile4_disable_irq_output(int cpu_irq); extern void nile4_set_pci_irq_polarity(int pci_irq, int high); extern void nile4_set_pci_irq_level_or_edge(int pci_irq, int level); extern void nile4_clear_irq(int nile4_irq); extern void nile4_clear_irq_mask(u32 mask); extern u8 nile4_i8259_iack(void); extern void nile4_dump_irq_status(void); /* Debug */ #endif Index: ddb5477.h =================================================================== RCS file: /cvsroot/linux-mips/linux/include/asm-mips/ddb5xxx/ddb5477.h,v retrieving revision 1.2 retrieving revision 1.3 diff -u -d -r1.2 -r1.3 --- ddb5477.h 2001/08/22 14:42:24 1.2 +++ ddb5477.h 2001/10/07 05:40:22 1.3 @@ -18,7 +18,6 @@ #define __ASM_DDB5XXX_DDB5477_H #include <linux/config.h> -#include <asm/ddb5xxx/ddb5xxx.h> /* * This contains macros that are specific to DDB5477 or renamed from @@ -28,9 +27,9 @@ /* * renamed PADRs */ -#define DDB_LCS0 DDB_LDCS0 -#define DDB_LCS1 DDB_LDCS1 -#define DDB_LCS2 DDB_LDCS2 +#define DDB_LCS0 DDB_DCS2 +#define DDB_LCS1 DDB_DCS3 +#define DDB_LCS2 DDB_DCS4 #define DDB_VRC5477 DDB_INTCS /* Index: ddb5xxx.h =================================================================== RCS file: /cvsroot/linux-mips/linux/include/asm-mips/ddb5xxx/ddb5xxx.h,v retrieving revision 1.1.1.1 retrieving revision 1.2 diff -u -d -r1.1.1.1 -r1.2 --- ddb5xxx.h 2001/06/22 02:29:33 1.1.1.1 +++ ddb5xxx.h 2001/10/07 05:40:22 1.2 @@ -1,5 +1,4 @@ -/*********************************************************************** - * +/* * Copyright 2001 MontaVista Software Inc. * Author: js...@mv... or js...@ju... * @@ -14,7 +13,6 @@ * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. * - *********************************************************************** */ #ifndef __ASM_DDB5XXX_DDB5XXX_H @@ -49,12 +47,13 @@ #define DDB_SDRAM0 0x0000 /* SDRAM Bank 0 [R/W] */ #define DDB_SDRAM1 0x0008 /* SDRAM Bank 1 [R/W] */ -#define DDB_LDCS0 0x0010 /* Device Chip-Select 0 [R/W] */ -#define DDB_LDCS1 0x0018 /* Device Chip-Select 1 [R/W] */ -#define DDB_LDCS2 0x0020 /* Device Chip-Select 2 [R/W] */ -#define DDB_LDCS3 0x0028 /* Device Chip-Select 3 [R/W] */ -#define DDB_LDCS4 0x0030 /* Device Chip-Select 4 [R/W] */ -#define DDB_LDCS5 0x0038 /* Device Chip-Select 5 [R/W] */ +#define DDB_DCS2 0x0010 /* Device Chip-Select 2 [R/W] */ +#define DDB_DCS3 0x0018 /* Device Chip-Select 3 [R/W] */ +#define DDB_DCS4 0x0020 /* Device Chip-Select 4 [R/W] */ +#define DDB_DCS5 0x0028 /* Device Chip-Select 5 [R/W] */ +#define DDB_DCS6 0x0030 /* Device Chip-Select 6 [R/W] */ +#define DDB_DCS7 0x0038 /* Device Chip-Select 7 [R/W] */ +#define DDB_DCS8 0x0040 /* Device Chip-Select 8 [R/W] */ #define DDB_PCIW0 0x0060 /* PCI Address Window 0 [R/W] */ #define DDB_PCIW1 0x0068 /* PCI Address Window 1 [R/W] */ #define DDB_INTCS 0x0070 /* Controller Internal Registers and Devices */ |
