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[Linux-mips-commits]CVS: linux/arch/mips/vr4181/common irq.c,1.4,1.5 time.c,1.1,1.2 int_handler.S,1.1,1.2
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From: Jun S. <ju...@us...> - 2001-09-29 00:42:28
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Update of /cvsroot/linux-mips/linux/arch/mips/vr4181/common
In directory usw-pr-cvs1:/tmp/cvs-serv20317/arch/mips/vr4181/common
Modified Files:
irq.c time.c int_handler.S
Log Message:
Woohoo! Finally get rid of the ugly old irq code. How smooth ...
Index: irq.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/vr4181/common/irq.c,v
retrieving revision 1.4
retrieving revision 1.5
diff -u -d -r1.4 -r1.5
--- irq.c 2001/09/27 23:59:15 1.4
+++ irq.c 2001/09/29 00:42:25 1.5
@@ -1,19 +1,20 @@
/*
- * linux/arch/mips/vr41xx/irq.c
- *
- * Code to handle VR4181 IRQs plus some generic interrupt stuff.
+ * Copyright (C) 2001 MontaVista Software Inc.
+ * Author: Jun Sun, js...@mv... or js...@ju...
*
- * Copyright (C) 1992 Linus Torvalds
- * Copyright (C) 1994, 1995, 1996, 1997 Ralf Baechle
- * Copyright (C) 1999 Bradley D. LaRonde
- * Copyright (C) 1999, 2000 Michael Klar
+ * linux/arch/mips/vr4181/common/irq.c
+ * Completely re-written to use the new irq.c
*
+ * Credits to Bradley D. LaRonde and Michael Klar for writing the original
+ * irq.c file which was derived from the common irq.c file.
+ *
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
*/
+#include <linux/types.h>
#include <linux/init.h>
#include <linux/kernel_stat.h>
#include <linux/signal.h>
@@ -21,517 +22,211 @@
#include <linux/interrupt.h>
#include <linux/malloc.h>
#include <linux/random.h>
-#include <linux/pm.h>
#include <asm/irq.h>
#include <asm/mipsregs.h>
#include <asm/gdb-stub.h>
#include <asm/vr4181/vr4181.h>
-
-/* [jsun] HACK */
-#define CONFIG_CPU_VR4181 y
-#define DEVICE_IRQ_MASKL 0xffff
-extern asmlinkage void vr4181_handle_irq(void);
-extern void breakpoint(void);
-
-// This is used elsewhere
-unsigned long spurious_count = 0;
-
-static unsigned short irq_mask_probe[(VR4181_IRQ_MAX + 9)/16];
+/*
+ * Strategy:
+ *
+ * We essentially have three irq controllers, CPU, system, and gpio.
+ *
+ * CPU irq controller is taken care by arch/mips/kernel/irq_cpu.c and
+ * CONFIG_IRQ_CPU config option.
+ *
+ * We here provide sys_irq and gpio_irq controller code.
+ */
-#define BIT_MASK(bit) ( 1 << (bit) )
-#define MAKE_CP0_STATUS_IRQ_MASK(irq) ( BIT_MASK( (irq) + 8))
+static int sys_irq_base;
+static int gpio_irq_base;
-static inline void mask_irq(unsigned int irq)
+/* ---------------------- sys irq ------------------------ */
+static void
+sys_irq_enable(unsigned int irq)
{
- if (irq < 8) {
- // it's a cpu interrupt
- unsigned short newstatus = read_32bit_cp0_register(CP0_STATUS);
- newstatus &= ~((unsigned short)1 << (irq + 8));
- change_cp0_status(ST0_IM, newstatus);
+ irq -= sys_irq_base;
+ if (irq < 16) {
+ *VR4181_MSYSINT1REG |= (u16)(1 << irq);
} else {
- if (irq < 40) {
- // it's an ICU interrupt
- if (irq < 24) {
- *VR4181_MSYSINT1REG &= ~((unsigned short)1 << (irq - 8));
- } else {
- *VR4181_MSYSINT2REG &= ~((unsigned short)1 << (irq - 24));
- }
- } else {
- // it's a GPIO interrupt
-#ifdef CONFIG_CPU_VR4181
- *VR4181_GPINTMSK |= (unsigned short)1 << (irq - 40);
-#else
- if (irq < 56) {
- *VR4181_MGIUINTLREG &= ~((unsigned short)1 << (irq - 40));
- } else {
- *VR4181_MGIUINTHREG &= ~((unsigned short)1 << (irq - 56));
- }
-#endif
- }
+ irq -= 16;
+ *VR4181_MSYSINT2REG |= (u16)(1 << irq);
}
}
-static inline void unmask_irq(unsigned int irq)
+static void
+sys_irq_disable(unsigned int irq)
{
- if (irq < 8) {
- // it's a cpu interrupt
- unsigned short newstatus = read_32bit_cp0_register(CP0_STATUS);
- newstatus |= ((unsigned short)1 << (irq + 8));
- change_cp0_status(ST0_IM, newstatus);
+ irq -= sys_irq_base;
+ if (irq < 16) {
+ *VR4181_MSYSINT1REG &= ~((u16)(1 << irq));
} else {
- if (irq < 40) {
- // it's an ICU interrupt
- if (irq < 24) {
- *VR4181_MSYSINT1REG |= (unsigned short)1 << (irq - 8);
- } else {
- *VR4181_MSYSINT2REG |= (unsigned short)1 << (irq - 24);
- }
- } else {
- // it's a GPIO interrupt (also ack edge-triggered or hold ints)
-#ifdef CONFIG_CPU_VR4181
- if (!((irq < 48 ? *VR4181_GPINTTYPL : *VR4181_GPINTTYPH) &
- ((unsigned short)2 << ((irq & 0x7) * 2))))
- *VR4181_GPINTSTAT = (unsigned short)1 << (irq - 40);
- *VR4181_GPINTMSK &= ~((unsigned short)1 << (irq - 40));
-#else
- if (irq < 56) {
- if (*VR4181_GIUINTHTSELL & ((unsigned short)1 << (irq - 40)))
- *VR4181_GIUINTSTATL = (unsigned short)1 << (irq - 40);
- *VR4181_MGIUINTLREG |= (unsigned short)1 << (irq - 40);
- } else {
- if (*VR4181_GIUINTHTSELH & ((unsigned short)1 << (irq - 56)))
- *VR4181_GIUINTSTATH = (unsigned short)1 << (irq - 56);
- *VR4181_MGIUINTHREG |= (unsigned short)1 << (irq - 56);
- }
-#endif
- }
+ irq -= 16;
+ *VR4181_MSYSINT2REG &= ~((u16)(1 << irq));
}
-}
-/*
- * Per-IRQ information, by not initializing, this gets filled with NULLs:
- */
-typedef struct {
- struct irqaction* irq_action; // info on low-level handler
- int depth; // < 0: enabled, >= 0: disabled
-} irq_info_t;
-
-static irq_info_t irq_info[VR4181_IRQ_MAX + 1];
-
-void disable_irq(unsigned int irq_nr)
-{
- unsigned long flags;
-
- if (++irq_info[irq_nr].depth >= 0) {
- save_and_cli(flags);
- mask_irq(irq_nr);
- restore_flags(flags);
- }
}
-void enable_irq(unsigned int irq_nr)
+static unsigned int
+sys_irq_startup(unsigned int irq)
{
- unsigned long flags;
-
-#ifdef CONFIG_CPU_VR4122
- if (irq_nr == VR4181_IRQ_GPIO14)
- return;
-#endif
-
- if (--irq_info[irq_nr].depth < 0) {
- save_and_cli(flags);
- unmask_irq(irq_nr);
- restore_flags(flags);
- }
+ sys_irq_enable(irq);
+ return 0;
}
-int get_irq_list(char *buf)
-{
- // make a human-readable list of irq actions
- // used by /proc/interrupts
+#define sys_irq_shutdown sys_irq_disable
+#define sys_irq_ack sys_irq_disable
+#define sys_irq_end sys_irq_enable
- int i, len = 0;
- struct irqaction *action;
+static hw_irq_controller sys_irq_controller = {
+ "vr4181_sys_irq",
+ sys_irq_startup,
+ sys_irq_shutdown,
+ sys_irq_enable,
+ sys_irq_disable,
+ sys_irq_ack,
+ sys_irq_end,
+ NULL /* no affinity stuff for UP */
+};
- for (i = 0; i <= VR4181_IRQ_MAX; i++) {
- action = irq_info[i].irq_action;
- if (!action)
- continue;
- len += sprintf(buf + len, "%2d: %8d %c %s",
- i, kstat.irqs[0][i],
- (action->flags & SA_INTERRUPT) ? '+' : ' ',
- action->name);
- for (action = action->next; action; action = action->next) {
- len += sprintf(buf + len, ",%s %s",
- (action->flags & SA_INTERRUPT) ? " +" : "",
- action->name);
- }
- len += sprintf(buf + len, "\n");
- }
- return len;
+/* ---------------------- gpio irq ------------------------ */
+/* gpio irq lines use reverse logic */
+static void
+gpio_irq_enable(unsigned int irq)
+{
+ irq -= gpio_irq_base;
+ *VR4181_GPINTMSK &= ~((u16)(1 << irq));
}
-
-atomic_t __mips_bh_counter;
-asmlinkage void do_IRQ(int irq, struct pt_regs *regs)
+static void
+gpio_irq_disable(unsigned int irq)
{
- // This handles all IRQ's that have been installed.
- // It is called from int-handler.S.
- // Actions without SA_INTERRUPT run with interrupts enabled
- // and use the full signal-handling return.
- // Actions with SA_INTERRUPT run with interrupts disabled.
-
- struct irqaction *action;
- int cpu = smp_processor_id();
-
- irq_enter(cpu, irq);
-
- kstat.irqs[cpu][irq]++;
-
- // don't interrupt on this same irq again until we're finished
- // also, it gets left masked if there is no action (see below)
- mask_irq(irq);
-
- action = irq_info[irq].irq_action;
-
- if (action != 0) {
- unsigned long flags = 0;
-
- if (!(action->flags & SA_INTERRUPT))
- __sti();
-
- do {
- // handle it
- action->handler(irq, action->dev_id, regs);
-
- flags |= action->flags;
- action = action->next;
- } while (action);
-
- if (flags & SA_SAMPLE_RANDOM)
- add_interrupt_randomness(irq);
-
- __cli();
-
- unmask_irq(irq);
- }
-
- irq_exit(cpu, irq);
-
- if (softirq_pending(cpu))
- do_softirq();
-
- // Unmasking and softirq handling is done for us
- // currently by ret_from_irq in entry.S.
+ irq -= gpio_irq_base;
+ *VR4181_GPINTMSK |= (u16)(1 << irq);
}
-int add_irq_action(int irq, struct irqaction *new)
+static unsigned int
+gpio_irq_startup(unsigned int irq)
{
- // put the specified action (new) at the end of the list of actions for this irq
-
- int shared = 0;
- struct irqaction *old, **p;
- unsigned long flags;
-
- p = &irq_info[irq].irq_action;
-
- if ((old = *p) != NULL) {
- if (!(old->flags & new->flags & SA_SHIRQ))
- return -EBUSY;
-
- // Shared interrupts must be all same type
- if ((old->flags ^ new->flags) & SA_INTERRUPT)
- return -EBUSY;
-
- do {
- p = &old->next;
- old = *p;
- } while (old);
-
- shared = 1;
- }
-
- if (new->flags & SA_SAMPLE_RANDOM)
- rand_initialize_irq(irq);
-
- save_and_cli(flags);
-
- *p = new;
-
- if (!shared) {
- irq_info[irq].depth = -1;
- unmask_irq(irq);
- }
+ gpio_irq_enable(irq);
- restore_flags(flags);
+ irq -= gpio_irq_base;
+ *VR4181_GPINTEN |= (u16)(1 << irq );
return 0;
}
-int request_irq(unsigned int irq,
- void (*handler)(int, void *, struct pt_regs *),
- unsigned long irqflags,
- const char *devname,
- void *dev_id)
+static void
+gpio_irq_shutdown(unsigned int irq)
{
- int retval;
- struct irqaction *action;
-
- // some assertiveness
- if (irq > VR4181_IRQ_MAX)
- return -EINVAL;
-
- if (!handler)
- return -EINVAL;
-
- // allocate a new action struct
- action = (struct irqaction *) kmalloc(sizeof(struct irqaction), GFP_KERNEL);
- if (!action)
- return -ENOMEM;
-
- // initialize it
- action->handler = handler;
- action->flags = irqflags;
- action->mask = 0;
- action->name = devname;
- action->next = NULL;
- action->dev_id = dev_id;
-
- // add it to the list of actions for this irq
- retval = add_irq_action(irq, action);
- if (retval)
- kfree(action);
+ gpio_irq_disable(irq);
- return retval;
+ irq -= gpio_irq_base;
+ *VR4181_GPINTEN &= ~((u16)(1 << irq ));
}
-void free_irq(unsigned int irq, void *dev_id)
+static void
+gpio_irq_ack(unsigned int irq)
{
- struct irqaction *action, **p;
- unsigned long flags;
-
- if (irq > VR4181_IRQ_MAX) {
- printk("Error - trying to free invalid IRQ %d\n", irq);
- return;
- }
+ u16 irqtype;
+ u16 irqshift;
- for (p = &irq_info[irq].irq_action; (action = *p) != NULL; p = &action->next) {
- if (action->dev_id != dev_id)
- continue;
+ gpio_irq_disable(irq);
- // Found it - now free it
- save_and_cli(flags);
- *p = action->next;
- if (!irq_info[irq].irq_action) {
- irq_info[irq].depth = 0;
- mask_irq(irq);
- }
- restore_flags(flags);
- kfree(action);
- return;
+ /* we clear interrupt if it is edge triggered */
+ irq -= gpio_irq_base;
+ if (irq < 8) {
+ irqtype = *VR4181_GPINTTYPL;
+ irqshift = 2 << (irq*2);
+ } else {
+ irqtype = *VR4181_GPINTTYPH;
+ irqshift = 2 << ((irq-8)*2);
}
+ if ( ! (irqtype & irqshift) ) {
+ *VR4181_GPINTSTAT = (u16) (1 << irq);
+ }
}
-
-unsigned long probe_irq_on(void)
-{
- int i;
- unsigned long delay;
- // Note the lower 8 bits of irq_mask_probe[0] are not used. Also,
- // we don't probe for IRQ 0, since no way to report (0 = no IRQ found)
- irq_mask_probe[0] = read_32bit_cp0_register(CP0_STATUS);
- irq_mask_probe[1] = *VR4181_MSYSINT1REG;
- irq_mask_probe[2] = *VR4181_MSYSINT2REG;
-#ifdef CONFIG_CPU_VR4181
- irq_mask_probe[3] = ~*VR4181_GPINTMSK;
-#else
- irq_mask_probe[3] = *VR4181_MGIUINTLREG;
- irq_mask_probe[4] = *VR4181_MGIUINTHREG;
-#endif
+#define gpio_irq_end gpio_irq_enable
- for (i = VR4181_IRQ_MAX; i > 0; i--)
- if (!irq_info[i].irq_action && i != VR4181_IRQ_TIMER)
- enable_irq(i);
+static hw_irq_controller gpio_irq_controller = {
+ "vr4181_gpio_irq",
+ gpio_irq_startup,
+ gpio_irq_shutdown,
+ gpio_irq_enable,
+ gpio_irq_disable,
+ gpio_irq_ack,
+ gpio_irq_end,
+ NULL /* no affinity stuff for UP */
+};
- // Wait for spurious interrupts to mask themselves out again...
- for (delay = jiffies + HZ/10; time_before(jiffies, delay); )
- barrier(); // about 100ms of delay
+/* --------------------- IRQ init stuff ---------------------- */
- irq_mask_probe[0] |= ~read_32bit_cp0_register(CP0_STATUS);
- irq_mask_probe[1] |= ~*VR4181_MSYSINT1REG;
- irq_mask_probe[2] |= ~*VR4181_MSYSINT2REG;
-#ifdef CONFIG_CPU_VR4181
- irq_mask_probe[3] |= *VR4181_GPINTMSK;
-#else
- irq_mask_probe[3] |= ~*VR4181_MGIUINTLREG;
- irq_mask_probe[4] |= ~*VR4181_MGIUINTHREG;
-#endif
+extern asmlinkage void vr4181_handle_irq(void);
+extern void breakpoint(void);
+extern int setup_irq(unsigned int irq, struct irqaction *irqaction);
+extern void mips_cpu_irq_init(u32 irq_base);
- return 0x12345678;
-}
+static struct irqaction cascade =
+ { no_action, SA_INTERRUPT, 0, "cascade", NULL, NULL };
+static struct irqaction reserved =
+ { no_action, SA_INTERRUPT, 0, "cascade", NULL, NULL };
-int probe_irq_off(unsigned long unused)
+void __init init_IRQ(void)
{
- int i, irq_found, nr_irqs;
- unsigned short tmp;
- unsigned long flags;
-
- if (unused != 0x12345678)
- printk("Bad IRQ probe detected\n");
-
- // The following mess unmasks the interrupts we enabled to autoprobe
- // and finishes bit-processing irq_mask_probe at the same time
- save_and_cli(flags);
- tmp = read_32bit_cp0_register(CP0_STATUS);
- change_cp0_status(ST0_IM, tmp & irq_mask_probe[0]);
- irq_mask_probe[0] |= tmp;
- tmp = *VR4181_MSYSINT1REG;
- *VR4181_MSYSINT1REG = tmp & irq_mask_probe[1];
- irq_mask_probe[1] |= tmp;
- tmp = *VR4181_MSYSINT2REG;
- *VR4181_MSYSINT2REG = tmp & irq_mask_probe[2];
- irq_mask_probe[2] |= tmp;
-#ifdef CONFIG_CPU_VR4181
- tmp = ~*VR4181_GPINTMSK;
- *VR4181_GPINTMSK = ~(tmp & irq_mask_probe[3]);
- irq_mask_probe[3] |= tmp;
-#else
- tmp = *VR4181_MGIUINTLREG;
- *VR4181_MGIUINTLREG = tmp & irq_mask_probe[3];
- irq_mask_probe[3] |= tmp;
- tmp = *VR4181_MGIUINTHREG;
- *VR4181_MGIUINTHREG = tmp & irq_mask_probe[4];
- irq_mask_probe[4] |= tmp;
-#endif
- restore_flags(flags);
-
- nr_irqs = 0;
- irq_found = 0;
-
- for (i = VR4181_IRQ_MAX; i > 0; i--)
- if (!(irq_mask_probe[(i + 8)/16] & ((unsigned short)1 << ((i + 8) & 15)))) {
- irq_found = i;
- nr_irqs++;
- }
-
- if (nr_irqs > 1)
- irq_found = -irq_found;
- return irq_found;
-}
+ int i;
+ extern irq_desc_t irq_desc[];
-#ifdef CONFIG_PM
-//
-// Unlike the real pm_request callbacks, this one doesn't get registered
-// with PM, and only gets called from do_hibernate and do_wakeup, because
-// it has to happen in a certain order. It also assumes ints disabled.
-//
-void do_pm_irq_request(pm_request_t rqst)
-{
- static unsigned short irq_mask[(VR4181_IRQ_MAX + 9)/16];
- unsigned int status;
+ set_except_vector(0, vr4181_handle_irq);
- switch (rqst) {
- case PM_RESUME:
- status = read_32bit_cp0_register(CP0_STATUS) & 0xffff00ff;
- write_32bit_cp0_register(CP0_STATUS, status | irq_mask[0]);
- *VR4181_MSYSINT1REG = irq_mask[1];
- *VR4181_MSYSINT2REG = irq_mask[2];
-#ifdef CONFIG_CPU_VR4181
- *VR4181_GPINTMSK = irq_mask[3];
-#else
- *VR4181_MGIUINTLREG = irq_mask[3];
- *VR4181_MGIUINTHREG = irq_mask[4];
-#endif
- break;
- case PM_SUSPEND:
- irq_mask[0] = read_32bit_cp0_register(CP0_STATUS) & 0xff00;
- irq_mask[1] = *VR4181_MSYSINT1REG;
- irq_mask[2] = *VR4181_MSYSINT2REG;
-#ifdef CONFIG_CPU_VR4181
- irq_mask[3] = *VR4181_GPINTMSK;
-#else
- irq_mask[3] = *VR4181_MGIUINTLREG;
- irq_mask[4] = *VR4181_MGIUINTHREG;
-#endif
- break;
- }
-}
-#endif // CONFIG_PM
+ /* init CPU irqs */
+ mips_cpu_irq_init(VR4181_CPU_IRQ_BASE);
-static struct irqaction cascade = { NULL, SA_INTERRUPT, 0, "cascade", NULL, NULL };
-static struct irqaction reserved = { NULL, SA_INTERRUPT, 0, "reserved", NULL, NULL };
+ /* init sys irqs */
+ sys_irq_base = VR4181_SYS_IRQ_BASE;
+ for (i=sys_irq_base; i < sys_irq_base + VR4181_NUM_SYS_IRQ; i++) {
+ irq_desc[i].status = IRQ_DISABLED;
+ irq_desc[i].action = NULL;
+ irq_desc[i].depth = 1;
+ irq_desc[i].handler = &sys_irq_controller;
+ }
-void __init init_IRQ(void)
-{
- set_except_vector(0, vr4181_handle_irq);
+ /* init gpio irqs */
+ gpio_irq_base = VR4181_GPIO_IRQ_BASE;
+ for (i=gpio_irq_base; i < gpio_irq_base + VR4181_NUM_GPIO_IRQ; i++) {
+ irq_desc[i].status = IRQ_DISABLED;
+ irq_desc[i].action = NULL;
+ irq_desc[i].depth = 1;
+ irq_desc[i].handler = &gpio_irq_controller;
+ }
- // Default all ICU IRQs to off ...
+ /* Default all ICU IRQs to off ... */
*VR4181_MSYSINT1REG = 0;
*VR4181_MSYSINT2REG = 0;
- // We initialize the level 2 ICU registers to all bits disabled.
- // After this, these registers are the resposibility of whatever
- // driver requests the IRQ of the corresponding level 1 ICU bit.
- // (except GIU, where each level 2 bit has its own IRQ)
-#ifdef CONFIG_CPU_VR4122
- *VR4181_MPCIINTREG = 0;
- *VR4181_MSCUINTREG = 0;
- *VR4181_MCSIINTREG = 0;
-#else
- *VR4181_MPIUINTREG = 0;
- *VR4181_MAIUINTREG = 0;
- *VR4181_MKIUINTREG = 0;
-#endif
-#ifdef CONFIG_CPU_VR4181
- *VR4181_GPINTMSK = 0xffff;
-#else
- *VR4181_MGIUINTLREG = 0;
- *VR4181_MDSIUINTREG = 0;
- *VR4181_MGIUINTHREG = 0;
- *VR4181_MFIRINTREG = 0;
-#endif
- barrier();
+ /* We initialize the level 2 ICU registers to all bits disabled. */
+ *VR4181_MPIUINTREG = 0;
+ *VR4181_MAIUINTREG = 0;
+ *VR4181_MKIUINTREG = 0;
-//
-// NOTE: This may break autodetection on some devices. If so, an IRQ mask needs
-// to be defined in vr41xx-platdep.h to disable some GPIO lines from interrupting,
-// or the broken autodetect IRQ needs to be defined explicitly. This define is
-// for documentation purposes, only turn it off for test/debug:
-//
-#define LET_ALL_GPIO_INPUTS_CAUSE_INTERRUPTS
-#ifdef LET_ALL_GPIO_INPUTS_CAUSE_INTERRUPTS
- // Initialize secondary IRQ mask to enable any GPIO line configured as an input.
- // Note that the int won't be active until enabled in the primary mask, too.
-#ifdef CONFIG_CPU_VR4181
- {
- unsigned int bits;
+ /* disable all GPIO intrs */
+ *VR4181_GPINTMSK = 0xffff;
- bits = (unsigned int)(*VR4181_GPMD1REG | 0xaaaa) << 16;
- bits |= *VR4181_GPMD0REG | 0xaaaa;
- bits &= bits >> 1;
- bits |= 0xcccccccc;
- bits &= bits >> 2;
- bits |= 0xf0f0f0f0;
- bits &= bits >> 4;
- bits |= 0xff00;
- bits &= bits >> 8;
- *VR4181_SECIRQMASKL = ~bits & DEVICE_IRQ_MASKL;
- }
-#else
- *VR4181_SECIRQMASKL = ~*VR4181_GIUIOSELL & DEVICE_IRQ_MASKL;
- *VR4181_SECIRQMASKH = ~*VR4181_GIUIOSELH & DEVICE_IRQ_MASKH;
-#endif
-#endif // LET_ALL_GPIO_INPUTS_CAUSE_INTERRUPTS
+ /* vector handler. What these do is register the IRQ as non-sharable */
+ setup_irq(VR4181_IRQ_INT0, &cascade);
+ setup_irq(VR4181_IRQ_GIU, &cascade);
- // These don't really add handlers, these IRQs are never reported by the int
- // vector handler. What these do is register the IRQ as non-sharable
- add_irq_action(VR4181_IRQ_INT0, &cascade);
- add_irq_action(VR4181_IRQ_GIU, &cascade);
- add_irq_action(VR4181_IRQ_RTCL1, &reserved);
- add_irq_action(VR4181_IRQ_RTCL2, &reserved);
+ /*
+ * RTC interrupts are interesting. They have two destinations.
+ * One is at sys irq controller, and the other is at CPU IP3 and IP4.
+ * RTC timer is used as system timer.
+ * We enable them here, but timer routine will register later
+ * with CPU IP3/IP4.
+ */
+ setup_irq(VR4181_IRQ_RTCL1, &reserved);
+ setup_irq(VR4181_IRQ_RTCL2, &reserved);
#ifdef CONFIG_REMOTE_DEBUG
printk("Setting debug traps - please connect the remote debugger.\n");
@@ -543,30 +238,3 @@
#endif
}
-#ifdef CONFIG_PCMCIA
-/*
- * dummy functions needed for PCMCIA support for non-ISA systems (vr4122) - mikemac
- *
- */
-
-/*
- * Return a mask of triggered interrupts (this
- * can handle only legacy ISA interrupts).
- */
-unsigned int
-probe_irq_mask(unsigned long val)
-{
- return val;
-}
-
-#ifndef CONFIG_ISA
-
-#define CS_IN_USE 0x1e
-
-int try_irq(u_int Attributes, int irq, int specific)
-{
- return CS_IN_USE;
-}
-#endif /* CONFIG_ISA */
-
-#endif /* CONFIG_PCMCIA */
Index: time.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/vr4181/common/time.c,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- time.c 2001/09/22 04:27:15 1.1
+++ time.c 2001/09/29 00:42:25 1.2
@@ -21,7 +21,7 @@
#include <linux/pm.h>
#include <asm/vr4181/vr4181.h>
-extern int add_irq_action(int irq, struct irqaction *new);
+extern int setup_irq(unsigned int irq, struct irqaction *irqaction);
extern volatile unsigned long wall_jiffies;
extern rwlock_t xtime_lock;
@@ -224,5 +224,5 @@
// Grab the IRQ for the cpu interrupt, not the ICU interrupt
// The RTCLong1 ICU interrupt is always left unmasked
// This can't use request_irq() because it's too early for kmalloc
- add_irq_action(VR4181_IRQ_INT1, &timer_action);
+ setup_irq(VR4181_IRQ_INT1, &timer_action);
}
Index: int_handler.S
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/vr4181/common/int_handler.S,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- int_handler.S 2001/09/27 23:59:15 1.1
+++ int_handler.S 2001/09/29 00:42:25 1.2
@@ -52,15 +52,13 @@
and t0, t2
- /* we check IP2 first; it happens most frequently */
+ /* we check IP3 first; it happens most frequently */
+ andi t1, t0, STATUSF_IP3
+ bnez t1, ll_cpu_ip3
andi t1, t0, STATUSF_IP2
bnez t1, ll_cpu_ip2
-
andi t1, t0, STATUSF_IP7 /* cpu timer */
bnez t1, ll_cputimer_irq
-
- andi t1, t0, STATUSF_IP3
- bnez t1, ll_cpu_ip3
andi t1, t0, STATUSF_IP4
bnez t1, ll_cpu_ip4
andi t1, t0, STATUSF_IP5
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