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[Linux-mips-commits]CVS: linux/include/asm-mips au1000.h,1.6,1.7 au1000_dma.h,1.2,1.3 au1000_pcmcia.h,1.1,1.2 io.h,1.5,1.6 keyboard.h,1.3,1.4 pb1000.h,1.2,1.3
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From: Paul M. <le...@us...> - 2001-09-25 03:36:40
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Update of /cvsroot/linux-mips/linux/include/asm-mips
In directory usw-pr-cvs1:/tmp/cvs-serv5739/include/asm-mips
Modified Files:
au1000.h au1000_dma.h au1000_pcmcia.h io.h keyboard.h pb1000.h
Log Message:
Sync with OSS 2.4.9.
Index: au1000.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/au1000.h,v
retrieving revision 1.6
retrieving revision 1.7
diff -u -d -r1.6 -r1.7
--- au1000.h 2001/09/12 21:31:06 1.6
+++ au1000.h 2001/09/25 03:36:35 1.7
@@ -28,7 +28,6 @@
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
-
#ifndef _AU1000_H_
#define _AU1000_H_
Index: au1000_dma.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/au1000_dma.h,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -d -r1.2 -r1.3
--- au1000_dma.h 2001/08/23 17:10:44 1.2
+++ au1000_dma.h 2001/09/25 03:36:35 1.3
@@ -1,5 +1,4 @@
/*
- *
* BRIEF MODULE DESCRIPTION
* Defines for using and allocating dma channels on the Alchemy
* Au1000 mips processor.
@@ -29,9 +28,8 @@
* 675 Mass Ave, Cambridge, MA 02139, USA.
*
*/
-
-#ifndef __ASM_MIPS_AU1000_DMA_H
-#define __ASM_MIPS_AU1000_DMA_H
+#ifndef __ASM_AU1000_DMA_H
+#define __ASM_AU1000_DMA_H
#include <linux/config.h>
#include <asm/io.h> /* need byte IO */
@@ -49,36 +47,36 @@
#define DMA_MODE_SET 0x00000000
#define DMA_MODE_CLEAR 0x00000004
/* DMA Mode register bits follow */
- #define DMA_DAH_MASK (0x0f << 20)
- #define DMA_DID_BIT 16
- #define DMA_DID_MASK (0x0f << DMA_DID_BIT)
- #define DMA_BE (1<<13)
- #define DMA_DR (1<<12)
- #define DMA_TS8 (1<<11)
- #define DMA_DW_BIT 9
- #define DMA_DW_MASK (0x03 << DMA_DW_BIT)
- #define DMA_DW8 (0 << DMA_DW_BIT)
- #define DMA_DW16 (1 << DMA_DW_BIT)
- #define DMA_DW32 (2 << DMA_DW_BIT)
- #define DMA_NC (1<<8)
- #define DMA_IE (1<<7)
- #define DMA_HALT (1<<6)
- #define DMA_GO (1<<5)
- #define DMA_AB (1<<4)
- #define DMA_D1 (1<<3)
- #define DMA_BE1 (1<<2)
- #define DMA_D0 (1<<1)
- #define DMA_BE0 (1<<0)
+#define DMA_DAH_MASK (0x0f << 20)
+#define DMA_DID_BIT 16
+#define DMA_DID_MASK (0x0f << DMA_DID_BIT)
+#define DMA_BE (1<<13)
+#define DMA_DR (1<<12)
+#define DMA_TS8 (1<<11)
+#define DMA_DW_BIT 9
+#define DMA_DW_MASK (0x03 << DMA_DW_BIT)
+#define DMA_DW8 (0 << DMA_DW_BIT)
+#define DMA_DW16 (1 << DMA_DW_BIT)
+#define DMA_DW32 (2 << DMA_DW_BIT)
+#define DMA_NC (1<<8)
+#define DMA_IE (1<<7)
+#define DMA_HALT (1<<6)
+#define DMA_GO (1<<5)
+#define DMA_AB (1<<4)
+#define DMA_D1 (1<<3)
+#define DMA_BE1 (1<<2)
+#define DMA_D0 (1<<1)
+#define DMA_BE0 (1<<0)
#define DMA_PERIPHERAL_ADDR 0x00000008
#define DMA_BUFFER0_START 0x0000000C
#define DMA_BUFFER1_START 0x00000014
#define DMA_BUFFER0_COUNT 0x00000010
#define DMA_BUFFER1_COUNT 0x00000018
- #define DMA_BAH_BIT 16
- #define DMA_BAH_MASK (0x0f << DMA_BAH_BIT)
- #define DMA_COUNT_BIT 0
- #define DMA_COUNT_MASK (0xffff << DMA_COUNT_BIT)
+#define DMA_BAH_BIT 16
+#define DMA_BAH_MASK (0x0f << DMA_BAH_BIT)
+#define DMA_COUNT_BIT 0
+#define DMA_COUNT_MASK (0xffff << DMA_COUNT_BIT)
/* DMA Device ID's follow */
enum {
@@ -105,26 +103,25 @@
int dev_id; // this channel is allocated if >=0, free otherwise
unsigned int io;
int irq;
- const char* dev_str;
+ const char *dev_str;
unsigned int fifo_addr;
unsigned int mode;
};
-
/* These are in arch/mips/au1000/common/dma.c */
extern struct dma_chan au1000_dma_table[];
-extern int request_au1000_dma(int dev_id, const char * dev_str);
+extern int request_au1000_dma(int dev_id, const char *dev_str);
extern void free_au1000_dma(unsigned int dmanr);
-extern int au1000_dma_read_proc (char *buf, char **start, off_t fpos,
+extern int au1000_dma_read_proc(char *buf, char **start, off_t fpos,
int length, int *eof, void *data);
extern void dump_au1000_dma_channel(unsigned int dmanr);
extern spinlock_t au1000_dma_spin_lock;
-static __inline__ struct dma_chan *
-get_dma_chan (unsigned int dmanr)
+static __inline__ struct dma_chan *get_dma_chan(unsigned int dmanr)
{
- if (dmanr > NUM_AU1000_DMA_CHANNELS || au1000_dma_table[dmanr].dev_id < 0)
+ if (dmanr > NUM_AU1000_DMA_CHANNELS
+ || au1000_dma_table[dmanr].dev_id < 0)
return NULL;
return &au1000_dma_table[dmanr];
}
@@ -146,38 +143,39 @@
*/
static __inline__ void enable_dma_buffer0(unsigned int dmanr)
{
- struct dma_chan * chan = get_dma_chan(dmanr);
+ struct dma_chan *chan = get_dma_chan(dmanr);
if (!chan)
return;
outl_sync(DMA_BE0, chan->io + DMA_MODE_SET);
}
static __inline__ void enable_dma_buffer1(unsigned int dmanr)
{
- struct dma_chan * chan = get_dma_chan(dmanr);
+ struct dma_chan *chan = get_dma_chan(dmanr);
if (!chan)
return;
outl_sync(DMA_BE1, chan->io + DMA_MODE_SET);
}
static __inline__ void enable_dma_buffers(unsigned int dmanr)
{
- struct dma_chan * chan = get_dma_chan(dmanr);
+ struct dma_chan *chan = get_dma_chan(dmanr);
if (!chan)
return;
- outl_sync(DMA_BE0|DMA_BE1, chan->io + DMA_MODE_SET);
+ outl_sync(DMA_BE0 | DMA_BE1, chan->io + DMA_MODE_SET);
}
/* enable/disable a specific DMA channel */
static __inline__ void enable_dma(unsigned int dmanr)
{
- struct dma_chan * chan = get_dma_chan(dmanr);
+ struct dma_chan *chan = get_dma_chan(dmanr);
if (!chan)
return;
// set device FIFO address
- outl_sync(virt_to_phys((void*)chan->fifo_addr),
- chan->io+DMA_PERIPHERAL_ADDR);
+ outl_sync(virt_to_phys((void *) chan->fifo_addr),
+ chan->io + DMA_PERIPHERAL_ADDR);
- outl_sync(chan->mode | (chan->dev_id << DMA_DID_BIT) | DMA_IE | DMA_GO,
+ outl_sync(chan->
+ mode | (chan->dev_id << DMA_DID_BIT) | DMA_IE | DMA_GO,
chan->io + DMA_MODE_SET);
}
@@ -186,21 +184,21 @@
static __inline__ void disable_dma(unsigned int dmanr)
{
int i;
- struct dma_chan * chan = get_dma_chan(dmanr);
+ struct dma_chan *chan = get_dma_chan(dmanr);
if (!chan)
return;
- outl_sync(DMA_D1 | DMA_D0 | DMA_GO, chan->io+DMA_MODE_CLEAR);
+ outl_sync(DMA_D1 | DMA_D0 | DMA_GO, chan->io + DMA_MODE_CLEAR);
// poll the halt bit
for (i = 0; i < DMA_HALT_POLL; i++)
- if (inl(chan->io+DMA_MODE_SET) & DMA_HALT)
+ if (inl(chan->io + DMA_MODE_SET) & DMA_HALT)
break;
if (i == DMA_HALT_POLL) {
printk(KERN_INFO "disable_dma: HALT poll expired!\n");
} else {
// now we can disable the buffers
- outl_sync(~DMA_GO, chan->io+DMA_MODE_CLEAR);
+ outl_sync(~DMA_GO, chan->io + DMA_MODE_CLEAR);
}
}
@@ -210,7 +208,7 @@
*/
static __inline__ void set_dma_mode(unsigned int dmanr, unsigned int mode)
{
- struct dma_chan * chan = get_dma_chan(dmanr);
+ struct dma_chan *chan = get_dma_chan(dmanr);
if (!chan)
return;
/*
@@ -218,16 +216,16 @@
* FIFO width, and cacheability info for the channel. Make sure
* anything else is masked off.
*/
- mode &= (DMA_BE|DMA_DR|DMA_TS8|DMA_DW_MASK|DMA_NC);
+ mode &= (DMA_BE | DMA_DR | DMA_TS8 | DMA_DW_MASK | DMA_NC);
chan->mode = mode;
}
static __inline__ int get_dma_active_buffer(unsigned int dmanr)
{
- struct dma_chan * chan = get_dma_chan(dmanr);
+ struct dma_chan *chan = get_dma_chan(dmanr);
if (!chan)
return -1;
- return (inl(chan->io+DMA_MODE_SET) & DMA_AB) ? 1 : 0;
+ return (inl(chan->io + DMA_MODE_SET) & DMA_AB) ? 1 : 0;
}
@@ -236,16 +234,18 @@
* applicable to GPO4 and GPO5. All the other devices have fixed
* FIFO addresses.
*/
-static __inline__ void set_dma_fifo_addr(unsigned int dmanr, unsigned int a)
+static __inline__ void set_dma_fifo_addr(unsigned int dmanr,
+ unsigned int a)
{
- struct dma_chan * chan = get_dma_chan(dmanr);
+ struct dma_chan *chan = get_dma_chan(dmanr);
if (!chan)
return;
if (chan->dev_id != DMA_ID_GP04 && chan->dev_id != DMA_ID_GP05)
return;
- outl_sync(virt_to_phys((void*)a), chan->io+DMA_PERIPHERAL_ADDR);
+ outl_sync(virt_to_phys((void *) a),
+ chan->io + DMA_PERIPHERAL_ADDR);
}
/*
@@ -253,17 +253,17 @@
*/
static __inline__ void clear_dma_done0(unsigned int dmanr)
{
- struct dma_chan * chan = get_dma_chan(dmanr);
+ struct dma_chan *chan = get_dma_chan(dmanr);
if (!chan)
return;
- outl_sync(DMA_D0, chan->io+DMA_MODE_CLEAR);
+ outl_sync(DMA_D0, chan->io + DMA_MODE_CLEAR);
}
static __inline__ void clear_dma_done1(unsigned int dmanr)
{
- struct dma_chan * chan = get_dma_chan(dmanr);
+ struct dma_chan *chan = get_dma_chan(dmanr);
if (!chan)
return;
- outl_sync(DMA_D1, chan->io+DMA_MODE_CLEAR);
+ outl_sync(DMA_D1, chan->io + DMA_MODE_CLEAR);
}
/*
@@ -278,57 +278,62 @@
*/
static __inline__ void set_dma_addr0(unsigned int dmanr, unsigned int a)
{
- struct dma_chan * chan = get_dma_chan(dmanr);
+ struct dma_chan *chan = get_dma_chan(dmanr);
if (!chan)
return;
- outl_sync(a, chan->io+DMA_BUFFER0_START);
+ outl_sync(a, chan->io + DMA_BUFFER0_START);
}
+
/*
* Set Buffer 1 transfer address for specific DMA channel.
*/
static __inline__ void set_dma_addr1(unsigned int dmanr, unsigned int a)
{
- struct dma_chan * chan = get_dma_chan(dmanr);
+ struct dma_chan *chan = get_dma_chan(dmanr);
if (!chan)
return;
- outl_sync(a, chan->io+DMA_BUFFER1_START);
+ outl_sync(a, chan->io + DMA_BUFFER1_START);
}
/*
* Set Buffer 0 transfer size (max 64k) for a specific DMA channel.
*/
-static __inline__ void set_dma_count0(unsigned int dmanr, unsigned int count)
+static __inline__ void set_dma_count0(unsigned int dmanr,
+ unsigned int count)
{
- struct dma_chan * chan = get_dma_chan(dmanr);
+ struct dma_chan *chan = get_dma_chan(dmanr);
if (!chan)
return;
count &= DMA_COUNT_MASK;
- outl_sync(count, chan->io+DMA_BUFFER0_COUNT);
+ outl_sync(count, chan->io + DMA_BUFFER0_COUNT);
}
+
/*
* Set Buffer 1 transfer size (max 64k) for a specific DMA channel.
*/
-static __inline__ void set_dma_count1(unsigned int dmanr, unsigned int count)
+static __inline__ void set_dma_count1(unsigned int dmanr,
+ unsigned int count)
{
- struct dma_chan * chan = get_dma_chan(dmanr);
+ struct dma_chan *chan = get_dma_chan(dmanr);
if (!chan)
return;
count &= DMA_COUNT_MASK;
- outl_sync(count, chan->io+DMA_BUFFER1_COUNT);
+ outl_sync(count, chan->io + DMA_BUFFER1_COUNT);
}
/*
* Set both buffer transfer sizes (max 64k) for a specific DMA channel.
*/
-static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
+static __inline__ void set_dma_count(unsigned int dmanr,
+ unsigned int count)
{
- struct dma_chan * chan = get_dma_chan(dmanr);
+ struct dma_chan *chan = get_dma_chan(dmanr);
if (!chan)
return;
count &= DMA_COUNT_MASK;
- outl_sync(count, chan->io+DMA_BUFFER0_COUNT);
- outl_sync(count, chan->io+DMA_BUFFER1_COUNT);
+ outl_sync(count, chan->io + DMA_BUFFER0_COUNT);
+ outl_sync(count, chan->io + DMA_BUFFER1_COUNT);
}
/*
@@ -338,11 +343,11 @@
static __inline__ int get_dma_buffer_done(unsigned int dmanr)
{
unsigned int mode;
- struct dma_chan * chan = get_dma_chan(dmanr);
+ struct dma_chan *chan = get_dma_chan(dmanr);
if (!chan)
return 0;
- mode = inl(chan->io+DMA_MODE_SET);
+ mode = inl(chan->io + DMA_MODE_SET);
if (!(mode & (DMA_D0 | DMA_D1)) ||
(mode & (DMA_D0 | DMA_D1)) == (DMA_D0 | DMA_D1))
return -1;
@@ -356,7 +361,7 @@
*/
static __inline__ int get_dma_done_irq(unsigned int dmanr)
{
- struct dma_chan * chan = get_dma_chan(dmanr);
+ struct dma_chan *chan = get_dma_chan(dmanr);
if (!chan)
return -1;
@@ -369,7 +374,7 @@
static __inline__ int get_dma_residue(unsigned int dmanr)
{
int curBufCntReg, count;
- struct dma_chan * chan = get_dma_chan(dmanr);
+ struct dma_chan *chan = get_dma_chan(dmanr);
if (!chan)
return 0;
@@ -385,6 +390,5 @@
return count;
}
-
-#endif /* __ASM_MIPS_AU1000_DMA_H */
+#endif /* __ASM_AU1000_DMA_H */
Index: au1000_pcmcia.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/au1000_pcmcia.h,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- au1000_pcmcia.h 2001/06/26 04:14:40 1.1
+++ au1000_pcmcia.h 2001/09/25 03:36:35 1.2
@@ -1,5 +1,4 @@
/*
- *
* Alchemy Semi Au1000 pcmcia driver include file
*
* Copyright 2001 MontaVista Software Inc.
@@ -25,9 +24,8 @@
*
*
*/
-
-#if !defined(_PCMCIA_AU1000_H)
-#define _PCMCIA_AU1000_H
+#ifndef __ASM_AU1000_PCMCIA_H
+#define __ASM_AU1000_PCMCIA_H
#define AU1000_PCMCIA_POLL_PERIOD (4*HZ)
@@ -86,4 +84,4 @@
extern struct pcmcia_low_level pb1000_pcmcia_ops;
-#endif
+#endif /* __ASM_AU1000_PCMCIA_H */
Index: io.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/io.h,v
retrieving revision 1.5
retrieving revision 1.6
diff -u -d -r1.5 -r1.6
--- io.h 2001/09/15 20:04:08 1.5
+++ io.h 2001/09/25 03:36:35 1.6
@@ -112,7 +112,6 @@
return (void *)KSEG0ADDR(address);
}
-
/*
* IO bus memory addresses are also 1:1 with the physical address
*/
@@ -126,11 +125,18 @@
return (void *)KSEG0ADDR(address);
}
+#define page_to_bus page_to_phys
+
/*
* isa_slot_offset is the address where E(ISA) busaddress 0 is mapped
* for the processor.
*/
extern unsigned long isa_slot_offset;
+
+/*
+ * Change "struct page" to physical address.
+ */
+#define page_to_phys(page) ((page - mem_map) << PAGE_SHIFT)
extern void * __ioremap(unsigned long offset, unsigned long size, unsigned long flags);
Index: keyboard.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/keyboard.h,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- keyboard.h 2001/09/06 17:02:03 1.3
+++ keyboard.h 2001/09/25 03:36:36 1.4
@@ -10,9 +10,10 @@
#ifdef __KERNEL__
+#include <linux/config.h>
#include <linux/delay.h>
#include <linux/ioport.h>
-#include <linux/config.h>
+#include <linux/kd.h>
#include <asm/bootinfo.h>
#define DISABLE_KBD_DURING_INTERRUPTS 0
@@ -25,7 +26,9 @@
char raw_mode);
extern char pckbd_unexpected_up(unsigned char keycode);
extern void pckbd_leds(unsigned char leds);
+extern int pckbd_rate(struct kbd_repeat *rep);
extern void pckbd_init_hw(void);
+extern void pckbd_pm_resume(void);
extern unsigned char pckbd_sysrq_xlate[128];
extern void kbd_forward_char (int ch);
@@ -34,6 +37,7 @@
#define kbd_translate pckbd_translate
#define kbd_unexpected_up pckbd_unexpected_up
#define kbd_leds pckbd_leds
+#define kbd_rate pckbd_rate
#define kbd_init_hw pckbd_init_hw
#define kbd_sysrq_xlate pckbd_sysrq_xlate
Index: pb1000.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/pb1000.h,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -d -r1.2 -r1.3
--- pb1000.h 2001/08/17 22:53:26 1.2
+++ pb1000.h 2001/09/25 03:36:36 1.3
@@ -1,5 +1,4 @@
/*
- *
* Alchemy Semi PB1000 Referrence Board
*
* Copyright 2001 MontaVista Software Inc.
@@ -25,10 +24,8 @@
*
*
*/
-
-#if !defined(_PB1000_H)
-#define _PB1000_H
-
+#ifndef __ASM_PB1000_H
+#define __ASM_PB1000_H
/* PCMCIA PB1000 specific defines */
#define PCMCIA_MAX_SOCK 0 /* the second socket, 1, is not supported at this time */
@@ -163,4 +160,4 @@
{
writel((readl(PCI_BRIDGE_CONFIG) & 0xffffbf00) | 0x18, PCI_BRIDGE_CONFIG);
}
-#endif
+#endif /* __ASM_PB1000_H */
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