[Linux-mips-commits]CVS: linux/include/asm-mips64/ip32 crime.h,NONE,1.1 io.h,NONE,1.1 ip32_ints.h,NONE,1.1 mace.h,NONE,1.1 machine.h,NONE,1.1

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/include/asm-mips64/ip32
In directory usw-pr-cvs1:/tmp/cvs-serv18698

Added Files:
	crime.h io.h ip32_ints.h mace.h machine.h 
Log Message:
O2 header files.

--- NEW FILE: crime.h ---
/*
 * Definitions for the SGI O2 Crime chip.
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 2000 Harald Koerfgen
 */

#ifndef __ASM_CRIME_H__
#define __ASM_CRIME_H__

#include <asm/addrspace.h>

/*
 * Address map
 */
#ifndef _LANGUAGE_ASSEMBLY
#define CRIME_BASE	KSEG1ADDR(0x14000000)
#else
#define CRIME_BASE	0xffffffffb4000000
#endif

#ifndef _LANGUAGE_ASSEMBLY
extern inline u64 crime_read_64 (unsigned long __offset) {
        return *((volatile u64 *) (CRIME_BASE + __offset));
}
extern inline void crime_write_64 (unsigned long __offset, u64 __val) {
        *((volatile u64 *) (CRIME_BASE + __offset)) = __val;
}
#endif

#undef BIT
#define BIT(x) (1UL << (x))

/* All CRIME registers are 64 bits */
#define CRIME_ID		0

#define CRIME_ID_MASK		0xff
#define CRIME_ID_IDBITS		0xf0
#define CRIME_ID_IDVALUE	0xa0
#define CRIME_ID_REV		0x0f

#define CRIME_REV_PETTY		0x00
#define CRIME_REV_11		0x11
#define CRIME_REV_13		0x13
#define CRIME_REV_14		0x14

#define CRIME_CONTROL		(0x00000008)
#define CRIME_CONTROL_MASK	0x3fff		/* 14-bit registers */

/* CRIME_CONTROL register bits */
#define CRIME_CONTROL_TRITON_SYSADC	0x2000
#define CRIME_CONTROL_CRIME_SYSADC	0x1000
#define CRIME_CONTROL_HARD_RESET	0x0800
#define CRIME_CONTROL_SOFT_RESET	0x0400
#define CRIME_CONTROL_DOG_ENA		0x0200
#define CRIME_CONTROL_ENDIANESS		0x0100

#define CRIME_CONTROL_ENDIAN_BIG	0x0100
#define CRIME_CONTROL_ENDIAN_LITTLE	0x0000

#define CRIME_CONTROL_CQUEUE_HWM	0x000f
#define CRIME_CONTROL_CQUEUE_SHFT	0
#define CRIME_CONTROL_WBUF_HWM		0x00f0
#define CRIME_CONTROL_WBUF_SHFT		8

#define CRIME_INT_STAT			(0x00000010)
#define CRIME_INT_MASK			(0x00000018)
#define CRIME_SOFT_INT			(0x00000020)
#define CRIME_HARD_INT			(0x00000028)

/* Bits in CRIME_INT_XXX and CRIME_HARD_INT */
#define MACE_VID_IN1_INT		BIT (0)
#define MACE_VID_IN2_INT		BIT (1)
#define MACE_VID_OUT_INT		BIT (2)
#define MACE_ETHERNET_INT		BIT (3)
#define MACE_SUPERIO_INT		BIT (4)
#define MACE_MISC_INT			BIT (5)
#define MACE_AUDIO_INT			BIT (6)
#define MACE_PCI_BRIDGE_INT		BIT (7)
#define MACEPCI_SCSI0_INT		BIT (8)
#define MACEPCI_SCSI1_INT		BIT (9)
#define MACEPCI_SLOT0_INT		BIT (10)
#define MACEPCI_SLOT1_INT		BIT (11)
#define MACEPCI_SLOT2_INT		BIT (12)
#define MACEPCI_SHARED0_INT		BIT (13)
#define MACEPCI_SHARED1_INT		BIT (14)
#define MACEPCI_SHARED2_INT		BIT (15)
#define CRIME_GBE0_INT			BIT (16)
#define CRIME_GBE1_INT			BIT (17)
#define CRIME_GBE2_INT			BIT (18)
#define CRIME_GBE3_INT			BIT (19)
#define CRIME_CPUERR_INT		BIT (20)
#define CRIME_MEMERR_INT		BIT (21)
#define CRIME_RE_EMPTY_E_INT		BIT (22)
#define CRIME_RE_FULL_E_INT		BIT (23)
#define CRIME_RE_IDLE_E_INT		BIT (24)
#define CRIME_RE_EMPTY_L_INT		BIT (25)
#define CRIME_RE_FULL_L_INT		BIT (26)
#define CRIME_RE_IDLE_L_INT    		BIT (27)
#define CRIME_SOFT0_INT			BIT (28)
#define CRIME_SOFT1_INT			BIT (29)
#define CRIME_SOFT2_INT			BIT (30)
#define CRIME_SYSCORERR_INT		CRIME_SOFT2_INT
#define CRIME_VICE_INT			BIT (31)

/* Masks for deciding who handles the interrupt */
#define CRIME_MACE_INT_MASK		0x8f
#define CRIME_MACEISA_INT_MASK		0x70
#define CRIME_MACEPCI_INT_MASK		0xff00
#define CRIME_CRIME_INT_MASK		0xffff0000

/*
 * XXX Todo
 */
#define CRIME_DOG			(0x00000030)
/* We are word-play compatible but not misspelling compatible */
#define MC_GRUFF			CRIME_DOG
#define CRIME_DOG_MASK			(0x001fffff)

/* CRIME_DOG register bits */
#define CRIME_DOG_POWER_ON_RESET	(0x00010000)
#define CRIME_DOG_WARM_RESET		(0x00080000)
#define CRIME_DOG_TIMEOUT		(CRIME_DOG_POWER_ON_RESET|CRIME_DOG_WARM_RESET)
#define CRIME_DOG_VALUE			(0x00007fff)	/* ??? */

#define CRIME_TIME			(0x00000038)
#define CRIME_TIME_MASK			(0x0000ffffffffffff)

#ifdef MASTER_FREQ
#undef MASTER_FREQ
#endif
#define CRIME_MASTER_FREQ		66666500	/* Crime upcounter frequency */
#define CRIME_NS_PER_TICK		15	/* for delay_calibrate */

#define CRIME_CPU_ERROR_ADDR		(0x00000040)
#define CRIME_CPU_ERROR_ADDR_MASK	(0x3ffffffff)

#define CRIME_CPU_ERROR_STAT		(0x00000048)
/* REV_PETTY only! */
#define CRIME_CPU_ERROR_ENA		(0x00000050)

/*
 * bit definitions for CRIME/VICE error status and enable registers
 */
#define CRIME_CPU_ERROR_MASK           0x7UL   /* cpu error stat is 3 bits */
#define CRIME_CPU_ERROR_CPU_ILL_ADDR   0x4
#define CRIME_CPU_ERROR_VICE_WRT_PRTY  0x2
#define CRIME_CPU_ERROR_CPU_WRT_PRTY   0x1

/*
 * these are the definitions for the error status/enable  register in
 * petty crime.  Note that the enable register does not exist in crime
 * rev 1 and above.
 */
#define CRIME_CPU_ERROR_MASK_REV0		0x3ff	/* cpu error stat is 9 bits */
#define CRIME_CPU_ERROR_CPU_INV_ADDR_RD		0x200
#define CRIME_CPU_ERROR_VICE_II			0x100
#define CRIME_CPU_ERROR_VICE_SYSAD		0x80
#define CRIME_CPU_ERROR_VICE_SYSCMD		0x40
#define CRIME_CPU_ERROR_VICE_INV_ADDR		0x20
#define CRIME_CPU_ERROR_CPU_II			0x10
#define CRIME_CPU_ERROR_CPU_SYSAD		0x8
#define CRIME_CPU_ERROR_CPU_SYSCMD		0x4
#define CRIME_CPU_ERROR_CPU_INV_ADDR_WR		0x2
#define CRIME_CPU_ERROR_CPU_INV_REG_ADDR	0x1

#define CRIME_VICE_ERROR_ADDR		(0x00000058)
#define CRIME_VICE_ERROR_ADDR_MASK	(0x3fffffff)

#define CRIME_MEM_CONTROL		(0x00000200)
#define CRIME_MEM_CONTROL_MASK		0x3	/* 25 cent register */
#define CRIME_MEM_CONTROL_ECC_ENA	0x1
#define CRIME_MEM_CONTROL_USE_ECC_REPL	0x2

/*
 * macros for CRIME memory bank control registers.
 */
#define CRIME_MEM_BANK_CONTROL(__bank)		(0x00000208 + ((__bank) << 3))
#define CRIME_MEM_BANK_CONTROL_MSK		0x11f /* 9 bits 7:5 reserved */
#define CRIME_MEM_BANK_CONTROL_ADDR		0x01f
#define CRIME_MEM_BANK_CONTROL_SDRAM_SIZE	0x100
#define CRIME_MEM_BANK_CONTROL_BANK_TO_ADDR(__bank) \
	(((__bank) & CRIME_MEM_BANK_CONTROL_ADDR) << 25)

#define CRIME_MEM_REFRESH_COUNTER	(0x00000248)
#define CRIME_MEM_REFRESH_COUNTER_MASK	0x7ff	/* 11-bit register */

#define CRIME_MAXBANKS                 8

/*
 * CRIME Memory error status register bit definitions
 */
#define CRIME_MEM_ERROR_STAT		(0x00000250)
#define CRIME_MEM_ERROR_STAT_MASK       0x0ff7ffff    /* 28-bit register */
#define CRIME_MEM_ERROR_MACE_ID		0x0000007f
#define CRIME_MEM_ERROR_MACE_ACCESS	0x00000080
#define CRIME_MEM_ERROR_RE_ID		0x00007f00
#define CRIME_MEM_ERROR_RE_ACCESS	0x00008000
#define CRIME_MEM_ERROR_GBE_ACCESS	0x00010000
#define CRIME_MEM_ERROR_VICE_ACCESS	0x00020000
#define CRIME_MEM_ERROR_CPU_ACCESS	0x00040000
#define CRIME_MEM_ERROR_RESERVED	0x00080000
#define CRIME_MEM_ERROR_SOFT_ERR	0x00100000
#define CRIME_MEM_ERROR_HARD_ERR	0x00200000
#define CRIME_MEM_ERROR_MULTIPLE	0x00400000
#define CRIME_MEM_ERROR_MEM_ECC_RD	0x00800000
#define CRIME_MEM_ERROR_MEM_ECC_RMW	0x01000000
#define CRIME_MEM_ERROR_INV_MEM_ADDR_RD	0x02000000
#define CRIME_MEM_ERROR_INV_MEM_ADDR_WR	0x04000000
#define CRIME_MEM_ERROR_INV_MEM_ADDR_RMW	0x08000000

#define CRIME_MEM_ERROR_ADDR		(0x00000258)
#define CRIME_MEM_ERROR_ADDR_MASK	0x3fffffff

#define CRIME_MEM_ERROR_ECC_SYN		(0x00000260)
#define CRIME_MEM_ERROR_ECC_SYN_MASK	0xffffffff

#define CRIME_MEM_ERROR_ECC_CHK		(0x00000268)
#define CRIME_MEM_ERROR_ECC_CHK_MASK    0xffffffff

#define CRIME_MEM_ERROR_ECC_REPL	(0x00000270)
#define CRIME_MEM_ERROR_ECC_REPL_MASK	0xffffffff

#endif /* __ASM_CRIME_H__ */

--- NEW FILE: io.h ---
#ifndef __ASM_IP32_IO_H__
#define __ASM_IP32_IO_H__

#include <asm/ip32/mace.h>

#define UNCACHEDADDR(x) (0x9000000000000000UL | (x))
#define IO_SPACE_BASE UNCACHEDADDR (MACEPCI_HI_MEMORY)
#define IO_SPACE_LIMIT 0xffffffffUL

#endif

--- NEW FILE: ip32_ints.h ---
/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 2000 Harald Koerfgen
 */

#ifndef __ASM_IP32_INTS_H
#define __ASM_IP32_INTS_H

/*
 * This list reflects the assignment of interrupt numbers to
 * interrupting events.  Order is fairly irrelevant to handling
 * priority.  This differs from irix.
 */

/* CPU */
#define CLOCK_IRQ			0

/* MACE */
#define MACE_VID_IN1_IRQ		1
#define MACE_VID_IN2_IRQ		2
#define MACE_VID_OUT_IRQ		3
#define MACE_ETHERNET_IRQ		4
/* SUPERIO, MISC, and AUDIO are MACEISA */
#define MACE_PCI_BRIDGE_IRQ		8

/* MACEPCI */
#define MACEPCI_SCSI0_IRQ		9
#define MACEPCI_SCSI1_IRQ		10
#define MACEPCI_SLOT0_IRQ		11
#define MACEPCI_SLOT1_IRQ		12
#define MACEPCI_SLOT2_IRQ		13
#define MACEPCI_SHARED0_IRQ		14
#define MACEPCI_SHARED1_IRQ		15
#define MACEPCI_SHARED2_IRQ		16

/* CRIME */
#define CRIME_GBE0_IRQ			17
#define CRIME_GBE1_IRQ			18
#define CRIME_GBE2_IRQ			19
#define CRIME_GBE3_IRQ			20
#define CRIME_CPUERR_IRQ		21
#define CRIME_MEMERR_IRQ		22
#define CRIME_RE_EMPTY_E_IRQ		23
#define CRIME_RE_FULL_E_IRQ		24
#define CRIME_RE_IDLE_E_IRQ		25
#define CRIME_RE_EMPTY_L_IRQ		26
#define CRIME_RE_FULL_L_IRQ		27
#define CRIME_RE_IDLE_L_IRQ		28
#define CRIME_SOFT0_IRQ			29
#define CRIME_SOFT1_IRQ			30
#define CRIME_SOFT2_IRQ			31
#define CRIME_SYSCORERR_IRQ		CRIME_SOFT2_IRQ
#define CRIME_VICE_IRQ			32

/* MACEISA */
#define MACEISA_AUDIO_SW_IRQ		33
#define MACEISA_AUDIO_SC_IRQ		34
#define MACEISA_AUDIO1_DMAT_IRQ		35
#define MACEISA_AUDIO1_OF_IRQ		36
#define MACEISA_AUDIO2_DMAT_IRQ		37
#define MACEISA_AUDIO2_MERR_IRQ		38
#define MACEISA_AUDIO3_DMAT_IRQ		39
#define MACEISA_AUDIO3_MERR_IRQ		40
#define MACEISA_RTC_IRQ			41
#define MACEISA_KEYB_IRQ		42
/* MACEISA_KEYB_POLL is not an IRQ */
#define MACEISA_MOUSE_IRQ		44
/* MACEISA_MOUSE_POLL is not an IRQ */
#define MACEISA_TIMER0_IRQ		46
#define MACEISA_TIMER1_IRQ		47
#define MACEISA_TIMER2_IRQ		48
#define MACEISA_PARALLEL_IRQ		49
#define MACEISA_PAR_CTXA_IRQ		50
#define MACEISA_PAR_CTXB_IRQ		51
#define MACEISA_PAR_MERR_IRQ		52
#define MACEISA_SERIAL1_IRQ		53
#define MACEISA_SERIAL1_TDMAT_IRQ	54
#define MACEISA_SERIAL1_TDMAPR_IRQ	55
#define MACEISA_SERIAL1_TDMAME_IRQ	56
#define MACEISA_SERIAL1_RDMAT_IRQ	57
#define MACEISA_SERIAL1_RDMAOR_IRQ	58
#define MACEISA_SERIAL2_IRQ		59
#define MACEISA_SERIAL2_TDMAT_IRQ	60
#define MACEISA_SERIAL2_TDMAPR_IRQ	61
#define MACEISA_SERIAL2_TDMAME_IRQ	62
#define MACEISA_SERIAL2_RDMAT_IRQ	63
#define MACEISA_SERIAL2_RDMAOR_IRQ	64

#define IP32_IRQ_MAX			MACEISA_SERIAL2_RDMAOR_IRQ

#endif /* __ASM_IP32_INTS_H */

--- NEW FILE: mace.h ---
/*
 * Definitions for the SGI O2 Mace chip.
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 2000 Harald Koerfgen
 */

#ifndef __ASM_MACE_H__
#define __ASM_MACE_H__

#include <asm/addrspace.h>

/*
 * Address map
 */
#define MACE_BASE		KSEG1ADDR(0x1f000000)
#define MACE_PCI		(0x00080000)
#define MACE_VIN1		(0x00100000)
#define MACE_VIN2		(0x00180000)
#define MACE_VOUT		(0x00200000)
#define MACE_ENET		(0x00280000)
#define MACE_PERIF		(0x00300000)
#define MACE_ISA_EXT		(0x00380000)

#define MACE_AUDIO_BASE		(MACE_PERIF		)
#define MACE_ISA_BASE		(MACE_PERIF + 0x00010000)
#define MACE_KBDMS_BASE		(MACE_PERIF + 0x00020000)
#define MACE_I2C_BASE		(MACE_PERIF + 0x00030000)
#define MACE_UST_BASE		(MACE_PERIF + 0x00040000)

#ifndef _LANGUAGE_ASSEMBLY
#include <asm/types.h>

/*
 * XXX Some of these are probably not needed (or even legal?)
 */
extern inline u8 mace_read_8 (unsigned long __offset) {
	return *((volatile u8 *) (MACE_BASE + __offset));
}
extern inline u16 mace_read_16 (unsigned long __offset) {
	return *((volatile u16 *) (MACE_BASE + __offset));
}
extern inline u32 mace_read_32 (unsigned long __offset) {
	return *((volatile u32 *) (MACE_BASE + __offset));
}
extern inline u64 mace_read_64 (unsigned long __offset) {
	return *((volatile u64 *) (MACE_BASE + __offset));
}
extern inline void mace_write_8 (unsigned long __offset, u8 __val) {
	*((volatile u8 *) (MACE_BASE + __offset)) = __val;
}
extern inline void mace_write_16 (unsigned long __offset, u16 __val) {
	*((volatile u16 *) (MACE_BASE + __offset)) = __val;
}
extern inline void mace_write_32 (unsigned long __offset, u32 __val) {
	*((volatile u32 *) (MACE_BASE + __offset)) = __val;
}
extern inline void mace_write_64 (unsigned long __offset, u64 __val) {
	*((volatile u64 *) (MACE_BASE + __offset)) = __val;
}
#endif

#undef BIT
#define BIT(__bit_offset) (1UL << (__bit_offset))

/*
 * Mace MACEPCI interface, 32 bit regs
 */
#define MACEPCI_ERROR_ADDR		(MACE_PCI	      )
#define MACEPCI_ERROR_FLAGS		(MACE_PCI + 0x00000004)
#define MACEPCI_CONTROL			(MACE_PCI + 0x00000008)
#define MACEPCI_REV			(MACE_PCI + 0x0000000c)
#define MACEPCI_WFLUSH			(MACE_PCI + 0x0000000c) /* ??? */
#define MACEPCI_CONFIG_ADDR		(MACE_PCI + 0x00000cf8)
#define MACEPCI_CONFIG_DATA		(MACE_PCI + 0x00000cfc)
#define MACEPCI_LOW_MEMORY		0x1a000000
#define MACEPCI_LOW_IO			0x18000000
#define MACEPCI_SWAPPED_VIEW		0
#define MACEPCI_NATIVE_VIEW		0x40000000
#define MACEPCI_IO			0x80000000
#define MACEPCI_HI_MEMORY		0x0000000280000000UL
#define MACEPCI_HI_IO			0x0000000100000000UL

/*
 * Bits in the MACEPCI_CONTROL register
 */
#define MACEPCI_CONTROL_INT(x)		BIT(x)
#define MACEPCI_CONTROL_INT_MASK	0xff
#define MACEPCI_CONTROL_SERR_ENA	BIT(8)
#define MACEPCI_CONTROL_ARB_N6		BIT(9)
#define MACEPCI_CONTROL_PARITY_ERR	BIT(10)
#define MACEPCI_CONTROL_MRMRA_ENA	BIT(11)
#define MACEPCI_CONTROL_ARB_N3		BIT(12)
#define MACEPCI_CONTROL_ARB_N4		BIT(13)
#define MACEPCI_CONTROL_ARB_N5		BIT(14)
#define MACEPCI_CONTROL_PARK_LIU	BIT(15)
#define MACEPCI_CONTROL_INV_INT(x)	BIT(16+x)
#define MACEPCI_CONTROL_INV_INT_MASK	0x00ff0000
#define MACEPCI_CONTROL_OVERRUN_INT	BIT(24)
#define MACEPCI_CONTROL_PARITY_INT	BIT(25)
#define MACEPCI_CONTROL_SERR_INT	BIT(26)
#define MACEPCI_CONTROL_IT_INT		BIT(27)
#define MACEPCI_CONTROL_RE_INT		BIT(28)
#define MACEPCI_CONTROL_DPED_INT	BIT(29)
#define MACEPCI_CONTROL_TAR_INT		BIT(30)
#define MACEPCI_CONTROL_MAR_INT		BIT(31)

/*
 * Bits in the MACE_PCI error register
 */
#define MACEPCI_ERROR_MASTER_ABORT		BIT(31)
#define MACEPCI_ERROR_TARGET_ABORT		BIT(30)
#define MACEPCI_ERROR_DATA_PARITY_ERR		BIT(29)
#define MACEPCI_ERROR_RETRY_ERR		BIT(28)
#define MACEPCI_ERROR_ILLEGAL_CMD		BIT(27)
#define MACEPCI_ERROR_SYSTEM_ERR		BIT(26)
#define MACEPCI_ERROR_INTERRUPT_TEST		BIT(25)
#define MACEPCI_ERROR_PARITY_ERR		BIT(24)
#define MACEPCI_ERROR_OVERRUN			BIT(23)
#define MACEPCI_ERROR_RSVD			BIT(22)
#define MACEPCI_ERROR_MEMORY_ADDR		BIT(21)
#define MACEPCI_ERROR_CONFIG_ADDR		BIT(20)
#define MACEPCI_ERROR_MASTER_ABORT_ADDR_VALID	BIT(19)
#define MACEPCI_ERROR_TARGET_ABORT_ADDR_VALID	BIT(18)
#define MACEPCI_ERROR_DATA_PARITY_ADDR_VALID	BIT(17)
#define MACEPCI_ERROR_RETRY_ADDR_VALID		BIT(16)
#define MACEPCI_ERROR_SIG_TABORT		BIT(4)
#define MACEPCI_ERROR_DEVSEL_MASK		0xc0
#define MACEPCI_ERROR_DEVSEL_FAST		0
#define MACEPCI_ERROR_DEVSEL_MED		0x40
#define MACEPCI_ERROR_DEVSEL_SLOW		0x80
#define MACEPCI_ERROR_FBB			BIT(1)
#define MACEPCI_ERROR_66MHZ			BIT(0)

/*
 * Mace timer registers - 64 bit regs (63:32 are UST, 31:0 are MSC)
 */
#define MSC_PART(__reg) ((__reg) & 0x00000000ffffffff)
#define UST_PART(__reg) (((__reg) & 0xffffffff00000000) >> 32)

#define MACE_UST_UST		(MACE_UST_BASE		   ) /* Universial system time */
#define MACE_UST_COMPARE1	(MACE_UST_BASE + 0x00000008) /* Interrupt compare reg 1 */
#define MACE_UST_COMPARE2	(MACE_UST_BASE + 0x00000010) /* Interrupt compare reg 2 */
#define MACE_UST_COMPARE3	(MACE_UST_BASE + 0x00000018) /* Interrupt compare reg 3 */
#define MACE_UST_PERIOD_NS	960	/* UST Period in ns  */

#define MACE_UST_AIN_MSC	(MACE_UST_BASE + 0x00000020) /* Audio in MSC/UST pair */
#define MACE_UST_AOUT1_MSC	(MACE_UST_BASE + 0x00000028) /* Audio out 1 MSC/UST pair */
#define MACE_UST_AOUT2_MSC	(MACE_UST_BASE + 0x00000030) /* Audio out 2 MSC/UST pair */
#define MACE_VIN1_MSC_UST	(MACE_UST_BASE + 0x00000038) /* Video In 1 MSC/UST pair */
#define MACE_VIN2_MSC_UST	(MACE_UST_BASE + 0x00000040) /* Video In 2 MSC/UST pair */
#define MACE_VOUT_MSC_UST	(MACE_UST_BASE + 0x00000048) /* Video out MSC/UST pair */

/*
 * Mace "ISA" peripherals
 */
#define MACEISA_EPP_BASE   	(MACE_ISA_EXT		  )
#define MACEISA_ECP_BASE   	(MACE_ISA_EXT + 0x00008000)
#define MACEISA_SER1_BASE	(MACE_ISA_EXT + 0x00010000)
#define MACEISA_SER2_BASE	(MACE_ISA_EXT + 0x00018000)
#define MACEISA_RTC_BASE	(MACE_ISA_EXT + 0x00020000)
#define MACEISA_GAME_BASE	(MACE_ISA_EXT + 0x00030000)

/*
 * Ringbase address and reset register - 64 bits
 */
#define MACEISA_RINGBASE	MACE_ISA_BASE

/*
 * Flash-ROM/LED/DP-RAM/NIC Controller Register - 64 bits (?)
 */
#define MACEISA_FLASH_NIC_REG	(MACE_ISA_BASE + 0x00000008)

/*
 * Bit definitions for that
 */
#define MACEISA_FLASH_WE       BIT(0) /* 1=> Enable FLASH writes */
#define MACEISA_PWD_CLEAR      BIT(1) /* 1=> PWD CLEAR jumper detected */
#define MACEISA_NIC_DEASSERT   BIT(2)
#define MACEISA_NIC_DATA       BIT(3)
#define MACEISA_LED_RED        BIT(4) /* 1=> Illuminate RED LED */
#define MACEISA_LED_GREEN      BIT(5) /* 1=> Illuminate GREEN LED */
#define MACEISA_DP_RAM_ENABLE  BIT(6)

/*
 * ISA interrupt and status registers - 32 bit
 */
#define MACEISA_INT_STAT	(MACE_ISA_BASE + 0x00000014)
#define MACEISA_INT_MASK	(MACE_ISA_BASE + 0x0000001c)

/*
 * Bits in the status/mask registers
 */
#define MACEISA_AUDIO_SW_INT		BIT (0)
#define MACEISA_AUDIO_SC_INT		BIT (1)
#define MACEISA_AUDIO1_DMAT_INT		BIT (2)
#define MACEISA_AUDIO1_OF_INT		BIT (3)
#define MACEISA_AUDIO2_DMAT_INT		BIT (4)
#define MACEISA_AUDIO2_MERR_INT		BIT (5)
#define MACEISA_AUDIO3_DMAT_INT		BIT (6)
#define MACEISA_AUDIO3_MERR_INT		BIT (7)
#define MACEISA_RTC_INT			BIT (8)
#define MACEISA_KEYB_INT		BIT (9)
#define MACEISA_KEYB_POLL_INT		BIT (10)
#define MACEISA_MOUSE_INT		BIT (11)
#define MACEISA_MOUSE_POLL_INT		BIT (12)
#define MACEISA_TIMER0_INT		BIT (13)
#define MACEISA_TIMER1_INT		BIT (14)
#define MACEISA_TIMER2_INT		BIT (15)
#define MACEISA_PARALLEL_INT		BIT (16)
#define MACEISA_PAR_CTXA_INT		BIT (17)
#define MACEISA_PAR_CTXB_INT		BIT (18)
#define MACEISA_PAR_MERR_INT		BIT (19)
#define MACEISA_SERIAL1_INT		BIT (20)
#define MACEISA_SERIAL1_TDMAT_INT	BIT (21)
#define MACEISA_SERIAL1_TDMAPR_INT	BIT (22)
#define MACEISA_SERIAL1_TDMAME_INT	BIT (23)
#define MACEISA_SERIAL1_RDMAT_INT	BIT (24)
#define MACEISA_SERIAL1_RDMAOR_INT	BIT (25)
#define MACEISA_SERIAL2_INT		BIT (26)
#define MACEISA_SERIAL2_TDMAT_INT	BIT (27)
#define MACEISA_SERIAL2_TDMAPR_INT	BIT (28)
#define MACEISA_SERIAL2_TDMAME_INT	BIT (29)
#define MACEISA_SERIAL2_RDMAT_INT	BIT (30)
#define MACEISA_SERIAL2_RDMAOR_INT	BIT (31)

#endif /* __ASM_MACE_H__ */

--- NEW FILE: machine.h ---
/*
 * machine.h -- Machine/group probing for ip32
 *
 * Copyright (C) 2001 Keith M Wesolowski
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file COPYING in the main directory of this archive
 * for more details.
 */
#ifndef _ASM_IP32_MACHINE_H
#define _ASM_IP32_MACHINE_H
#ifdef CONFIG_SGI_IP32

#define SGI_MACH_O2		0x3201

#endif /* CONFIG_SGI_IP32 */
#endif /* _ASM_SGI_MACHINE_H */