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[Linux-mips-commits]CVS: linux/include/asm-mips atomic.h,1.2,1.3 au1000.h,1.3,1.4 cpu.h,1.6,1.7 hardirq.h,1.4,1.5 irq.h,1.2,1.3
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From: Paul M. <le...@us...> - 2001-08-25 02:19:33
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Update of /cvsroot/linux-mips/linux/include/asm-mips
In directory usw-pr-cvs1:/tmp/cvs-serv13548/include/asm-mips
Modified Files:
atomic.h au1000.h cpu.h hardirq.h irq.h
Log Message:
Sync to 2.4.7
Index: atomic.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/atomic.h,v
retrieving revision 1.2
retrieving revision 1.3
diff -C2 -d -r1.2 -r1.3
*** atomic.h 2001/07/26 21:55:39 1.2
--- atomic.h 2001/08/25 02:19:28 1.3
***************
*** 273,276 ****
--- 273,282 ----
*/
+ /* Atomic operations are already serializing */
+ #define smp_mb__before_atomic_dec() barrier()
+ #define smp_mb__after_atomic_dec() barrier()
+ #define smp_mb__before_atomic_inc() barrier()
+ #define smp_mb__after_atomic_inc() barrier()
+
#endif /* defined(__KERNEL__) */
Index: au1000.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/au1000.h,v
retrieving revision 1.3
retrieving revision 1.4
diff -C2 -d -r1.3 -r1.4
*** au1000.h 2001/08/17 22:53:26 1.3
--- au1000.h 2001/08/25 02:19:28 1.4
***************
*** 70,182 ****
/* SDRAM Controller */
! #define CS_MODE_0 0xB4000000
! #define CS_MODE_1 0xB4000004
! #define CS_MODE_2 0xB4000008
! #define CS_CONFIG_0 0xB400000C
! #define CS_CONFIG_1 0xB4000010
! #define CS_CONFIG_2 0xB4000014
! #define REFRESH_CONFIG 0xB4000018
! #define PRECHARGE_CMD 0xB400001C
! #define AUTO_REFRESH_CMD 0xB4000020
! #define WRITE_EXTERN_0 0xB4000024
! #define WRITE_EXTERN_1 0xB4000028
! #define WRITE_EXTERN_2 0xB400002C
! #define SDRAM_SLEEP 0xB4000030
! #define TOGGLE_CKE 0xB4000034
/* Static Bus Controller */
! #define STATIC_CONFIG_0 0xB4001000
! #define STATIC_TIMING_0 0xB4001004
! #define STATIC_ADDRESS_0 0xB4001008
! #define STATIC_CONFIG_1 0xB4001010
! #define STATIC_TIMING_1 0xB4001014
! #define STATIC_ADDRESS_1 0xB4001018
! #define STATIC_CONFIG_2 0xB4001020
! #define STATIC_TIMING_2 0xB4001024
! #define STATIC_ADDRESS_2 0xB4001028
! #define STATIC_CONFIG_3 0xB4001030
! #define STATIC_TIMING_3 0xB4001034
! #define STATIC_ADDRESS_3 0xB4001038
/* Interrupt Controller 0 */
! #define INTC0_CONFIG0_READ 0xB0400040
! #define INTC0_CONFIG0_SET 0xB0400040
! #define INTC0_CONFIG0_CLEAR 0xB0400044
! #define INTC0_CONFIG1_READ 0xB0400048
! #define INTC0_CONFIG1_SET 0xB0400048
! #define INTC0_CONFIG1_CLEAR 0xB040004C
! #define INTC0_CONFIG2_READ 0xB0400050
! #define INTC0_CONFIG2_SET 0xB0400050
! #define INTC0_CONFIG2_CLEAR 0xB0400054
! #define INTC0_REQ0_INT 0xB0400054
! #define INTC0_SOURCE_READ 0xB0400058
! #define INTC0_SOURCE_SET 0xB0400058
! #define INTC0_SOURCE_CLEAR 0xB040005C
! #define INTC0_REQ1_INT 0xB040005C
! #define INTC0_ASSIGN_REQ_READ 0xB0400060
! #define INTC0_ASSIGN_REQ_SET 0xB0400060
! #define INTC0_ASSIGN_REQ_CLEAR 0xB0400064
! #define INTC0_WAKEUP_READ 0xB0400068
! #define INTC0_WAKEUP_SET 0xB0400068
! #define INTC0_WAKEUP_CLEAR 0xB040006C
! #define INTC0_MASK_READ 0xB0400070
! #define INTC0_MASK_SET 0xB0400070
! #define INTC0_MASK_CLEAR 0xB0400074
! #define INTC0_R_EDGE_DETECT 0xB0400078
! #define INTC0_R_EDGE_DETECT_CLEAR 0xB0400078
! #define INTC0_F_EDGE_DETECT_CLEAR 0xB040007C
! #define INTC0_TEST_BIT 0xB0400080
/* Interrupt Controller 1 */
! #define INTC1_CONFIG0_READ 0xB1800040
! #define INTC1_CONFIG0_SET 0xB1800040
! #define INTC1_CONFIG0_CLEAR 0xB1800044
! #define INTC1_CONFIG1_READ 0xB1800048
! #define INTC1_CONFIG1_SET 0xB1800048
! #define INTC1_CONFIG1_CLEAR 0xB180004C
! #define INTC1_CONFIG2_READ 0xB1800050
! #define INTC1_CONFIG2_SET 0xB1800050
! #define INTC1_CONFIG2_CLEAR 0xB1800054
! #define INTC1_REQ0_INT 0xB1800054
! #define INTC1_SOURCE_READ 0xB1800058
! #define INTC1_SOURCE_SET 0xB1800058
! #define INTC1_SOURCE_CLEAR 0xB180005C
! #define INTC1_REQ1_INT 0xB180005C
! #define INTC1_ASSIGN_REQ_READ 0xB1800060
! #define INTC1_ASSIGN_REQ_SET 0xB1800060
! #define INTC1_ASSIGN_REQ_CLEAR 0xB1800064
! #define INTC1_WAKEUP_READ 0xB1800068
! #define INTC1_WAKEUP_SET 0xB1800068
! #define INTC1_WAKEUP_CLEAR 0xB180006C
! #define INTC1_MASK_READ 0xB1800070
! #define INTC1_MASK_SET 0xB1800070
! #define INTC1_MASK_CLEAR 0xB1800074
! #define INTC1_R_EDGE_DETECT 0xB1800078
! #define INTC1_R_EDGE_DETECT_CLEAR 0xB1800078
! #define INTC1_F_EDGE_DETECT_CLEAR 0xB180007C
! #define INTC1_TEST_BIT 0xB1800080
/* Interrupt Configuration Modes */
--- 70,254 ----
/* SDRAM Controller */
! #define CS_MODE_0 0x14000000
! #define CS_MODE_1 0x14000004
! #define CS_MODE_2 0x14000008
! #define CS_CONFIG_0 0x1400000C
! #define CS_CONFIG_1 0x14000010
! #define CS_CONFIG_2 0x14000014
! #define REFRESH_CONFIG 0x14000018
! #define PRECHARGE_CMD 0x1400001C
! #define AUTO_REFRESH_CMD 0x14000020
! #define WRITE_EXTERN_0 0x14000024
! #define WRITE_EXTERN_1 0x14000028
! #define WRITE_EXTERN_2 0x1400002C
! #define SDRAM_SLEEP 0x14000030
! #define TOGGLE_CKE 0x14000034
/* Static Bus Controller */
! #define STATIC_CONFIG_0 0x14001000
! #define STATIC_TIMING_0 0x14001004
! #define STATIC_ADDRESS_0 0x14001008
! #define STATIC_CONFIG_1 0x14001010
! #define STATIC_TIMING_1 0x14001014
! #define STATIC_ADDRESS_1 0x14001018
! #define STATIC_CONFIG_2 0x14001020
! #define STATIC_TIMING_2 0x14001024
! #define STATIC_ADDRESS_2 0x14001028
! #define STATIC_CONFIG_3 0x14001030
! #define STATIC_TIMING_3 0x14001034
! #define STATIC_ADDRESS_3 0x14001038
!
! /* DMA Controller 0 */
! #define DMA0_MODE_SET 0x14002000
! #define DMA0_MODE_CLEAR 0x14002004
! #define DMA0_PERIPHERAL_ADDR 0x14002008
! #define DMA0_BUFFER0_START 0x1400200C
! #define DMA0_BUFFER0_COUNT 0x14002010
! #define DMA0_BUFFER1_START 0x14002014
! #define DMA0_BUFFER1_COUNT 0x14002018
!
! /* DMA Controller 1 */
! #define DMA1_MODE_SET 0x14002100
! #define DMA1_MODE_CLEAR 0x14002104
! #define DMA1_PERIPHERAL_ADDR 0x14002108
! #define DMA1_BUFFER0_START 0x1400210C
! #define DMA1_BUFFER0_COUNT 0x14002110
! #define DMA1_BUFFER1_START 0x14002114
! #define DMA1_BUFFER1_COUNT 0x14002118
!
! /* DMA Controller 2 */
! #define DMA2_MODE_SET 0x14002200
! #define DMA2_MODE_CLEAR 0x14002204
! #define DMA2_PERIPHERAL_ADDR 0x14002208
! #define DMA2_BUFFER0_START 0x1400220C
! #define DMA2_BUFFER0_COUNT 0x14002210
! #define DMA2_BUFFER1_START 0x14002214
! #define DMA2_BUFFER1_COUNT 0x14002218
!
! /* DMA Controller 3 */
! #define DMA3_MODE_SET 0x14002300
! #define DMA3_MODE_CLEAR 0x14002304
! #define DMA3_PERIPHERAL_ADDR 0x14002308
! #define DMA3_BUFFER0_START 0x1400230C
! #define DMA3_BUFFER0_COUNT 0x14002310
! #define DMA3_BUFFER1_START 0x14002314
! #define DMA3_BUFFER1_COUNT 0x14002318
+ /* DMA Controller 4 */
+ #define DMA4_MODE_SET 0x14002400
+ #define DMA4_MODE_CLEAR 0x14002404
+ #define DMA4_PERIPHERAL_ADDR 0x14002408
+ #define DMA4_BUFFER0_START 0x1400240C
+ #define DMA4_BUFFER0_COUNT 0x14002410
+ #define DMA4_BUFFER1_START 0x14002414
+ #define DMA4_BUFFER1_COUNT 0x14002418
+
+ /* DMA Controller 5 */
+ #define DMA5_MODE_SET 0x14002500
+ #define DMA5_MODE_CLEAR 0x14002504
+ #define DMA5_PERIPHERAL_ADDR 0x14002508
+ #define DMA5_BUFFER0_START 0x1400250C
+ #define DMA5_BUFFER0_COUNT 0x14002510
+ #define DMA5_BUFFER1_START 0x14002514
+ #define DMA5_BUFFER1_COUNT 0x14002518
+
+ /* DMA Controller 6 */
+ #define DMA6_MODE_SET 0x14002600
+ #define DMA6_MODE_CLEAR 0x14002604
+ #define DMA6_PERIPHERAL_ADDR 0x14002608
+ #define DMA6_BUFFER0_START 0x1400260C
+ #define DMA6_BUFFER0_COUNT 0x14002610
+ #define DMA6_BUFFER1_START 0x14002614
+ #define DMA6_BUFFER1_COUNT 0x14002618
+
+ /* DMA Controller 7 */
+ #define DMA7_MODE_SET 0x14002700
+ #define DMA7_MODE_CLEAR 0x14002704
+ #define DMA7_PERIPHERAL_ADDR 0x14002708
+ #define DMA7_BUFFER0_START 0x1400270C
+ #define DMA7_BUFFER0_COUNT 0x14002710
+ #define DMA7_BUFFER1_START 0x14002714
+ #define DMA7_BUFFER1_COUNT 0x14002718
+
/* Interrupt Controller 0 */
! #define INTC0_CONFIG0_READ 0x10400040
! #define INTC0_CONFIG0_SET 0x10400040
! #define INTC0_CONFIG0_CLEAR 0x10400044
! #define INTC0_CONFIG1_READ 0x10400048
! #define INTC0_CONFIG1_SET 0x10400048
! #define INTC0_CONFIG1_CLEAR 0x1040004C
! #define INTC0_CONFIG2_READ 0x10400050
! #define INTC0_CONFIG2_SET 0x10400050
! #define INTC0_CONFIG2_CLEAR 0x10400054
! #define INTC0_REQ0_INT 0x10400054
! #define INTC0_SOURCE_READ 0x10400058
! #define INTC0_SOURCE_SET 0x10400058
! #define INTC0_SOURCE_CLEAR 0x1040005C
! #define INTC0_REQ1_INT 0x1040005C
! #define INTC0_ASSIGN_REQ_READ 0x10400060
! #define INTC0_ASSIGN_REQ_SET 0x10400060
! #define INTC0_ASSIGN_REQ_CLEAR 0x10400064
! #define INTC0_WAKEUP_READ 0x10400068
! #define INTC0_WAKEUP_SET 0x10400068
! #define INTC0_WAKEUP_CLEAR 0x1040006C
! #define INTC0_MASK_READ 0x10400070
! #define INTC0_MASK_SET 0x10400070
! #define INTC0_MASK_CLEAR 0x10400074
! #define INTC0_R_EDGE_DETECT 0x10400078
! #define INTC0_R_EDGE_DETECT_CLEAR 0x10400078
! #define INTC0_F_EDGE_DETECT_CLEAR 0x1040007C
! #define INTC0_TEST_BIT 0x10400080
/* Interrupt Controller 1 */
! #define INTC1_CONFIG0_READ 0x11800040
! #define INTC1_CONFIG0_SET 0x11800040
! #define INTC1_CONFIG0_CLEAR 0x11800044
! #define INTC1_CONFIG1_READ 0x11800048
! #define INTC1_CONFIG1_SET 0x11800048
! #define INTC1_CONFIG1_CLEAR 0x1180004C
! #define INTC1_CONFIG2_READ 0x11800050
! #define INTC1_CONFIG2_SET 0x11800050
! #define INTC1_CONFIG2_CLEAR 0x11800054
! #define INTC1_REQ0_INT 0x11800054
! #define INTC1_SOURCE_READ 0x11800058
! #define INTC1_SOURCE_SET 0x11800058
! #define INTC1_SOURCE_CLEAR 0x1180005C
! #define INTC1_REQ1_INT 0x1180005C
! #define INTC1_ASSIGN_REQ_READ 0x11800060
! #define INTC1_ASSIGN_REQ_SET 0x11800060
! #define INTC1_ASSIGN_REQ_CLEAR 0x11800064
! #define INTC1_WAKEUP_READ 0x11800068
! #define INTC1_WAKEUP_SET 0x11800068
! #define INTC1_WAKEUP_CLEAR 0x1180006C
! #define INTC1_MASK_READ 0x11800070
! #define INTC1_MASK_SET 0x11800070
! #define INTC1_MASK_CLEAR 0x11800074
! #define INTC1_R_EDGE_DETECT 0x11800078
! #define INTC1_R_EDGE_DETECT_CLEAR 0x11800078
! #define INTC1_F_EDGE_DETECT_CLEAR 0x1180007C
! #define INTC1_TEST_BIT 0x11800080
/* Interrupt Configuration Modes */
***************
*** 196,200 ****
#define AU1000_SSI0_INT 4
#define AU1000_SSI1_INT 5
! #define AU1000_DMA_INT_BASE 6
#define AU1000_PC0_INT 14
#define AU1000_PC0_MATCH0_INT 15
--- 268,279 ----
#define AU1000_SSI0_INT 4
#define AU1000_SSI1_INT 5
! #define AU1000_DMA0_INT 6
! #define AU1000_DMA1_INT 7
! #define AU1000_DMA2_INT 8
! #define AU1000_DMA3_INT 9
! #define AU1000_DMA4_INT 10
! #define AU1000_DMA5_INT 11
! #define AU1000_DMA6_INT 12
! #define AU1000_DMA7_INT 13
#define AU1000_PC0_INT 14
#define AU1000_PC0_MATCH0_INT 15
***************
*** 252,256 ****
/* Programmable Counters 0 and 1 */
! #define PC_BASE 0xB1900000
#define PC_COUNTER_CNTRL (PC_BASE + 0x14)
#define PC_CNTRL_E1S (1<<23)
--- 331,335 ----
/* Programmable Counters 0 and 1 */
! #define PC_BASE 0x11900000
#define PC_COUNTER_CNTRL (PC_BASE + 0x14)
#define PC_CNTRL_E1S (1<<23)
***************
*** 292,298 ****
/* I2S Controller */
! #define I2S_DATA 0xB1000000
! #define I2S_CONFIG_STATUS 0xB1000001
! #define I2S_CONTROL 0xB1000002
/* USB Host Controller */
--- 371,377 ----
/* I2S Controller */
! #define I2S_DATA 0x11000000
! #define I2S_CONFIG_STATUS 0x11000001
! #define I2S_CONTROL 0x11000002
/* USB Host Controller */
***************
*** 345,350 ****
/* Ethernet Controllers */
! #define AU1000_ETH0_BASE 0xB0500000
! #define AU1000_ETH1_BASE 0xB0510000
/* 4 byte offsets from AU1000_ETH_BASE */
--- 424,429 ----
/* Ethernet Controllers */
! #define AU1000_ETH0_BASE 0x10500000
! #define AU1000_ETH1_BASE 0x10510000
/* 4 byte offsets from AU1000_ETH_BASE */
***************
*** 391,399 ****
/* Ethernet Controller Enable */
! #define MAC0_ENABLE 0xB0520000
! #define MAC1_ENABLE 0xB0520004
#define MAC_EN_CLOCK_ENABLE (1<<0)
#define MAC_EN_RESET0 (1<<1)
! #define MAC_EN_TOSS (0<<2)
#define MAC_EN_CACHEABLE (1<<3)
#define MAC_EN_RESET1 (1<<4)
--- 470,478 ----
/* Ethernet Controller Enable */
! #define MAC0_ENABLE 0x10520000
! #define MAC1_ENABLE 0x10520004
#define MAC_EN_CLOCK_ENABLE (1<<0)
#define MAC_EN_RESET0 (1<<1)
! #define MAC_EN_TOSS (1<<2)
#define MAC_EN_CACHEABLE (1<<3)
#define MAC_EN_RESET1 (1<<4)
***************
*** 403,408 ****
/* Ethernet Controller DMA Channels */
! #define MAC0_TX_DMA_ADDR 0xB4004000
! #define MAC1_TX_DMA_ADDR 0xB4004200
/* offsets from MAC_TX_RING_ADDR address */
#define MAC_TX_BUFF0_STATUS 0x0
--- 482,487 ----
/* Ethernet Controller DMA Channels */
! #define MAC0_TX_DMA_ADDR 0x14004000
! #define MAC1_TX_DMA_ADDR 0x14004200
/* offsets from MAC_TX_RING_ADDR address */
#define MAC_TX_BUFF0_STATUS 0x0
***************
*** 434,439 ****
#define MAC_TX_BUFF3_LEN 0x38
! #define MAC0_RX_DMA_ADDR 0xB4004100
! #define MAC1_RX_DMA_ADDR 0xB4004300
/* offsets from MAC_RX_RING_ADDR */
#define MAC_RX_BUFF0_STATUS 0x0
--- 513,518 ----
#define MAC_TX_BUFF3_LEN 0x38
! #define MAC0_RX_DMA_ADDR 0x14004100
! #define MAC1_RX_DMA_ADDR 0x14004300
/* offsets from MAC_RX_RING_ADDR */
#define MAC_RX_BUFF0_STATUS 0x0
***************
*** 475,482 ****
/* UARTS 0-3 */
! #define UART0_ADDR 0xB1100000
! #define UART1_ADDR 0xB1200000
! #define UART2_ADDR 0xB1300000
! #define UART3_ADDR 0xB1400000
#define UART_RX 0 /* Receive buffer */
--- 554,561 ----
/* UARTS 0-3 */
! #define UART0_ADDR 0x11100000
! #define UART1_ADDR 0x11200000
! #define UART2_ADDR 0x11300000
! #define UART3_ADDR 0x11400000
#define UART_RX 0 /* Receive buffer */
***************
*** 573,638 ****
/* SSIO */
! #define SSI0_STATUS 0xB1600000
! #define SSI0_INT 0xB1600004
! #define SSI0_INT_ENABLE 0xB1600008
! #define SSI0_CONFIG 0xB1600020
! #define SSI0_ADATA 0xB1600024
! #define SSI0_CLKDIV 0xB1600028
! #define SSI0_CONTROL 0xB1600100
/* SSI1 */
! #define SSI1_STATUS 0xB1680000
! #define SSI1_INT 0xB1680004
! #define SSI1_INT_ENABLE 0xB1680008
! #define SSI1_CONFIG 0xB1680020
! #define SSI1_ADATA 0xB1680024
! #define SSI1_CLKDIV 0xB1680028
! #define SSI1_CONTROL 0xB1680100
/* IrDA Controller */
! #define IR_RING_PTR_STATUS 0xB1500000
! #define IR_RING_BASE_ADDR_H 0xB1500004
! #define IR_RING_BASE_ADDR_L 0xB1500008
! #define IR_RING_SIZE 0xB150000C
! #define IR_RING_PROMPT 0xB1500010
! #define IR_RING_ADDR_CMPR 0xB1500014
! #define IR_CONFIG_1 0xB1500020
! #define IR_SIR_FLAGS 0xB1500024
! #define IR_ENABLE 0xB1500028
! #define IR_READ_PHY_CONFIG 0xB150002C
! #define IR_WRITE_PHY_CONFIG 0xB1500030
! #define IR_MAX_PKT_LEN 0xB1500034
! #define IR_RX_BYTE_CNT 0xB1500038
! #define IR_CONFIG_2 0xB150003C
! #define IR_INTERFACE_CONFIG 0xB1500040
/* GPIO */
! #define PIN_FUNCTION 0xB190002C
! #define TSTATE_STATE_READ 0xB1900100
! #define TSTATE_STATE_SET 0xB1900100
! #define OUTPUT_STATE_READ 0xB1900108
! #define OUTPUT_STATE_SET 0xB1900108
! #define OUTPUT_STATE_CLEAR 0xB190010C
! #define PIN_STATE 0xB1900110
/* Power Management */
! #define PM_SCRATCH_0 0xB1900018
! #define PM_SCRATCH_1 0xB190001C
! #define PM_WAKEUP_SOURCE_MASK 0xB1900034
! #define PM_ENDIANESS 0xB1900038
! #define PM_POWERUP_CONTROL 0xB190003C
! #define PM_WAKEUP_CAUSE 0xB190005C
! #define PM_SLEEP_POWER 0xB1900078
! #define PM_SLEEP 0xB190007C
/* Clock Controller */
! #define FQ_CNTRL_1 0xB1900020
! #define FQ_CNTRL_2 0xB1900024
! #define CLOCK_SOURCE_CNTRL 0xB1900028
! #define CPU_PLL_CNTRL 0xB1900060
! #define AUX_PLL_CNTRL 0xB1900064
/* AC97 Controller */
! #define AC97C_CONFIG 0xB0000000
#define AC97C_RECV_SLOTS_BIT 13
#define AC97C_RECV_SLOTS_MASK (0x3ff << AC97C_RECV_SLOTS_BIT)
--- 652,716 ----
/* SSIO */
! #define SSI0_STATUS 0x11600000
! #define SSI0_INT 0x11600004
! #define SSI0_INT_ENABLE 0x11600008
! #define SSI0_CONFIG 0x11600020
! #define SSI0_ADATA 0x11600024
! #define SSI0_CLKDIV 0x11600028
! #define SSI0_CONTROL 0x11600100
/* SSI1 */
! #define SSI1_STATUS 0x11680000
! #define SSI1_INT 0x11680004
! #define SSI1_INT_ENABLE 0x11680008
! #define SSI1_CONFIG 0x11680020
! #define SSI1_ADATA 0x11680024
! #define SSI1_CLKDIV 0x11680028
! #define SSI1_CONTROL 0x11680100
/* IrDA Controller */
! #define IR_RING_PTR_STATUS 0x11500000
! #define IR_RING_BASE_ADDR_H 0x11500004
! #define IR_RING_BASE_ADDR_L 0x11500008
! #define IR_RING_SIZE 0x1150000C
! #define IR_RING_PROMPT 0x11500010
! #define IR_RING_ADDR_CMPR 0x11500014
! #define IR_CONFIG_1 0x11500020
! #define IR_SIR_FLAGS 0x11500024
! #define IR_ENABLE 0x11500028
! #define IR_READ_PHY_CONFIG 0x1150002C
! #define IR_WRITE_PHY_CONFIG 0x11500030
! #define IR_MAX_PKT_LEN 0x11500034
! #define IR_RX_BYTE_CNT 0x11500038
! #define IR_CONFIG_2 0x1150003C
! #define IR_INTERFACE_CONFIG 0x11500040
/* GPIO */
! #define TSTATE_STATE_READ 0x11900100
! #define TSTATE_STATE_SET 0x11900100
! #define OUTPUT_STATE_READ 0x11900108
! #define OUTPUT_STATE_SET 0x11900108
! #define OUTPUT_STATE_CLEAR 0x1190010C
! #define PIN_STATE 0x11900110
/* Power Management */
! #define PM_SCRATCH_0 0x11900018
! #define PM_SCRATCH_1 0x1190001C
! #define PM_WAKEUP_SOURCE_MASK 0x11900034
! #define PM_ENDIANESS 0x11900038
! #define PM_POWERUP_CONTROL 0x1190003C
! #define PM_WAKEUP_CAUSE 0x1190005C
! #define PM_SLEEP_POWER 0x11900078
! #define PM_SLEEP 0x1190007C
/* Clock Controller */
! #define FQ_CNTRL_1 0x11900020
! #define FQ_CNTRL_2 0x11900024
! #define CLOCK_SOURCE_CNTRL 0x11900028
! #define CPU_PLL_CNTRL 0x11900060
! #define AUX_PLL_CNTRL 0x11900064
/* AC97 Controller */
! #define AC97C_CONFIG 0x10000000
#define AC97C_RECV_SLOTS_BIT 13
#define AC97C_RECV_SLOTS_MASK (0x3ff << AC97C_RECV_SLOTS_BIT)
***************
*** 642,646 ****
#define AC97C_SYNC (1<<1)
#define AC97C_RESET (1<<0)
! #define AC97C_STATUS 0xB0000004
#define AC97C_XU (1<<11)
#define AC97C_XO (1<<10)
--- 720,724 ----
#define AC97C_SYNC (1<<1)
#define AC97C_RESET (1<<0)
! #define AC97C_STATUS 0x10000004
#define AC97C_XU (1<<11)
#define AC97C_XO (1<<10)
***************
*** 655,664 ****
#define AC97C_RE (1<<1)
#define AC97C_RF (1<<0)
! #define AC97C_DATA 0xB0000008
! #define AC97C_CMD 0xB000000C
#define AC97C_WD_BIT 16
#define AC97C_READ (1<<7)
#define AC97C_INDEX_MASK 0x7f
! #define AC97C_CNTRL 0xB0000010
#define AC97C_RS (1<<1)
#define AC97C_CE (1<<0)
--- 733,742 ----
#define AC97C_RE (1<<1)
#define AC97C_RF (1<<0)
! #define AC97C_DATA 0x10000008
! #define AC97C_CMD 0x1000000C
#define AC97C_WD_BIT 16
#define AC97C_READ (1<<7)
#define AC97C_INDEX_MASK 0x7f
! #define AC97C_CNTRL 0x10000010
#define AC97C_RS (1<<1)
#define AC97C_CE (1<<0)
Index: cpu.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/cpu.h,v
retrieving revision 1.6
retrieving revision 1.7
diff -C2 -d -r1.6 -r1.7
*** cpu.h 2001/08/17 22:53:26 1.6
--- cpu.h 2001/08/25 02:19:28 1.7
***************
*** 9,12 ****
--- 9,13 ----
#include <asm/cache.h>
+
/* Assigned Company values for bits 23:16 of the PRId Register
(CP0 register 15, select 0). As of the MIPS32 and MIPS64 specs from
***************
*** 38,43 ****
*/
#define PRID_IMP_R2000 0x0100
! #define PRID_IMP_AU1_REV1 0x0100
! #define PRID_IMP_AU1_REV2 0x0200
#define PRID_IMP_R3000 0x0200 /* Same as R2000A */
#define PRID_IMP_R6000 0x0300 /* Same as R3000A */
--- 39,43 ----
*/
#define PRID_IMP_R2000 0x0100
! #define PRID_IMP_AU1000 0x0100
#define PRID_IMP_R3000 0x0200 /* Same as R2000A */
#define PRID_IMP_R6000 0x0300 /* Same as R3000A */
Index: hardirq.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/hardirq.h,v
retrieving revision 1.4
retrieving revision 1.5
diff -C2 -d -r1.4 -r1.5
*** hardirq.h 2001/08/22 18:18:14 1.4
--- hardirq.h 2001/08/25 02:19:28 1.5
***************
*** 21,24 ****
--- 21,25 ----
unsigned int __local_bh_count;
unsigned int __syscall_count;
+ struct task_struct * __ksoftirqd_task; /* waitqueue is too large */
} ____cacheline_aligned irq_cpustat_t;
Index: irq.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/irq.h,v
retrieving revision 1.2
retrieving revision 1.3
diff -C2 -d -r1.2 -r1.3
*** irq.h 2001/07/09 21:50:55 1.2
--- irq.h 2001/08/25 02:19:28 1.3
***************
*** 29,33 ****
extern void disable_irq(unsigned int);
! #if defined(CONFIG_ROTTEN_IRQ) || defined(CONFIG_COBALT_MICRO_SERVER)
#define disable_irq_nosync disable_irq
#else
--- 29,33 ----
extern void disable_irq(unsigned int);
! #if !defined(CONFIG_NEW_IRQ) || defined(CONFIG_COBALT_MICRO_SERVER)
#define disable_irq_nosync disable_irq
#else
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