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[Linux-mips-commits]CVS: linux/drivers/net Config.in,1.6,1.7 Makefile,1.4,1.5 au1000_eth.c,1.2,1.3 declance.c,1.3,1.4 gt96100eth.c,1.2,1.3 gt96100eth.h,1.2,1.3
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From: Paul M. <le...@us...> - 2001-08-25 02:19:32
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Update of /cvsroot/linux-mips/linux/drivers/net
In directory usw-pr-cvs1:/tmp/cvs-serv13548/drivers/net
Modified Files:
Config.in Makefile au1000_eth.c declance.c gt96100eth.c
gt96100eth.h
Log Message:
Sync to 2.4.7
Index: Config.in
===================================================================
RCS file: /cvsroot/linux-mips/linux/drivers/net/Config.in,v
retrieving revision 1.6
retrieving revision 1.7
diff -C2 -d -r1.6 -r1.7
*** Config.in 2001/08/23 19:13:56 1.6
--- Config.in 2001/08/25 02:19:27 1.7
***************
*** 186,190 ****
dep_bool ' Zenith Z-Note support (EXPERIMENTAL)' CONFIG_ZNET $CONFIG_ISA
fi
! if [ "$CONFIG_EXPERIMENTAL" = "y" -a "$CONFIG_ORION" = "y" ]; then
bool ' Philips SAA9730 Ethernet support (EXPERIMENTAL)' CONFIG_LAN_SAA9730
fi
--- 186,190 ----
dep_bool ' Zenith Z-Note support (EXPERIMENTAL)' CONFIG_ZNET $CONFIG_ISA
fi
! if [ "$CONFIG_EXPERIMENTAL" = "y" ]; then
bool ' Philips SAA9730 Ethernet support (EXPERIMENTAL)' CONFIG_LAN_SAA9730
fi
***************
*** 223,226 ****
--- 223,227 ----
dep_tristate 'Alteon AceNIC/3Com 3C985/NetGear GA620 Gigabit support' CONFIG_ACENIC $CONFIG_PCI
dep_mbool ' Omit support for old Tigon I based AceNICs' CONFIG_ACENIC_OMIT_TIGON_I $CONFIG_ACENIC
+ dep_tristate 'D-Link DL2000-based Gigabit Ethernet support' CONFIG_DL2K $CONFIG_PCI
dep_tristate 'MyriCOM Gigabit Ethernet support' CONFIG_MYRI_SBUS $CONFIG_SBUS
dep_tristate 'Packet Engines Hamachi GNIC-II support' CONFIG_HAMACHI $CONFIG_PCI
Index: Makefile
===================================================================
RCS file: /cvsroot/linux-mips/linux/drivers/net/Makefile,v
retrieving revision 1.4
retrieving revision 1.5
diff -C2 -d -r1.4 -r1.5
*** Makefile 2001/08/23 19:13:56 1.4
--- Makefile 2001/08/25 02:19:28 1.5
***************
*** 31,35 ****
subdir-$(CONFIG_NET_PCMCIA) += pcmcia
! subdir-$(CONFIG_NET_RADIO) += wireless
subdir-$(CONFIG_TULIP) += tulip
subdir-$(CONFIG_IRDA) += irda
--- 31,35 ----
subdir-$(CONFIG_NET_PCMCIA) += pcmcia
! subdir-$(CONFIG_NET_WIRELESS) += wireless
subdir-$(CONFIG_TULIP) += tulip
subdir-$(CONFIG_IRDA) += irda
***************
*** 210,213 ****
--- 210,214 ----
obj-$(CONFIG_TUN) += tun.o
obj-$(CONFIG_NEC_CANDY) += nec_candy.o
+ obj-$(CONFIG_DL2K) += dl2k.o
ifeq ($(CONFIG_ARCH_ACORN),y)
Index: au1000_eth.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/drivers/net/au1000_eth.c,v
retrieving revision 1.2
retrieving revision 1.3
diff -C2 -d -r1.2 -r1.3
*** au1000_eth.c 2001/06/26 04:26:42 1.2
--- au1000_eth.c 2001/08/25 02:19:28 1.3
***************
*** 79,82 ****
--- 79,83 ----
static inline void update_rx_stats(struct net_device *, u32);
static void au1000_timer(unsigned long);
+ static void cleanup_buffers(struct net_device *);
static int au1000_ioctl(struct net_device *, struct ifreq *, int);
static int mdio_read(struct net_device *, int, int);
***************
*** 485,488 ****
--- 486,509 ----
}
+ static void cleanup_buffers(struct net_device *dev)
+ {
+ int i;
+ struct au1000_private *aup = (struct au1000_private *) dev->priv;
+
+ for (i=0; i<NUM_RX_DMA; i++) {
+ if (aup->rx_db_inuse[i]) {
+ ReleaseDB(aup, aup->rx_db_inuse[i]);
+ aup->rx_db_inuse[i] = 0;
+ }
+ }
+
+ for (i=0; i<NUM_TX_DMA; i++) {
+ if (aup->tx_db_inuse[i]) {
+ ReleaseDB(aup, aup->tx_db_inuse[i]);
+ aup->tx_db_inuse[i] = 0;
+ }
+ }
+ }
+
/*
***************
*** 497,504 ****
for (i=0; i<NUM_RX_DMA; i++) {
! aup->rx_dma_ring[i] = (volatile rx_dma_t *) (rx_base + sizeof(rx_dma_t)*i);
}
for (i=0; i<NUM_TX_DMA; i++) {
! aup->tx_dma_ring[i] = (volatile tx_dma_t *) (tx_base + sizeof(tx_dma_t)*i);
}
}
--- 518,527 ----
for (i=0; i<NUM_RX_DMA; i++) {
! aup->rx_dma_ring[i] = (volatile rx_dma_t *) ioremap_nocache((unsigned long)
! (rx_base + sizeof(rx_dma_t)*i), sizeof(rx_dma_t));
}
for (i=0; i<NUM_TX_DMA; i++) {
! aup->tx_dma_ring[i] = (volatile tx_dma_t *)ioremap_nocache((unsigned long)
! (tx_base + sizeof(tx_dma_t)*i), sizeof(tx_dma_t));
}
}
***************
*** 586,598 ****
/* aup->mac is the base address of the MAC's registers */
! aup->mac = (volatile mac_reg_t *)((unsigned long)ioaddr);
/* Setup some variables for quick register address access */
if (ioaddr == AU1000_ETH0_BASE) {
! aup->enable = (volatile u32 *) ((unsigned long)MAC0_ENABLE);
memcpy(dev->dev_addr, au1000_mac_addr[0], sizeof(dev->dev_addr));
setup_hw_rings(aup, MAC0_RX_DMA_ADDR, MAC0_TX_DMA_ADDR);
}
else if (ioaddr == AU1000_ETH1_BASE) {
! aup->enable = (volatile u32 *) ((unsigned long)MAC1_ENABLE);
memcpy(dev->dev_addr, au1000_mac_addr[1], sizeof(dev->dev_addr));
setup_hw_rings(aup, MAC1_RX_DMA_ADDR, MAC1_TX_DMA_ADDR);
--- 609,623 ----
/* aup->mac is the base address of the MAC's registers */
! aup->mac = (volatile mac_reg_t *)ioremap_nocache((unsigned long)ioaddr, sizeof(*aup->mac));
/* Setup some variables for quick register address access */
if (ioaddr == AU1000_ETH0_BASE) {
! aup->enable = (volatile u32 *)
! ioremap_nocache((unsigned long)MAC0_ENABLE, sizeof(*aup->enable));
memcpy(dev->dev_addr, au1000_mac_addr[0], sizeof(dev->dev_addr));
setup_hw_rings(aup, MAC0_RX_DMA_ADDR, MAC0_TX_DMA_ADDR);
}
else if (ioaddr == AU1000_ETH1_BASE) {
! aup->enable = (volatile u32 *)
! ioremap_nocache((unsigned long)MAC1_ENABLE, sizeof(*aup->enable));
memcpy(dev->dev_addr, au1000_mac_addr[1], sizeof(dev->dev_addr));
setup_hw_rings(aup, MAC1_RX_DMA_ADDR, MAC1_TX_DMA_ADDR);
***************
*** 744,748 ****
struct net_device *dev = (struct net_device *)data;
struct au1000_private *aup = (struct au1000_private *) dev->priv;
! u16 link, speed;
if (!dev) {
--- 769,773 ----
struct net_device *dev = (struct net_device *)data;
struct au1000_private *aup = (struct au1000_private *) dev->priv;
! u16 mii_data, link, speed;
if (!dev) {
***************
*** 850,867 ****
if (status & TX_FRAME_ABORTED) {
! if (dev->if_port == IF_PORT_100BASEFX) {
! if (status & (TX_JAB_TIMEOUT | TX_UNDERRUN)) {
! /* any other tx errors are only valid
! * in half duplex mode */
! ps->tx_errors++;
! ps->tx_aborted_errors++;
! }
! }
! else {
! ps->tx_errors++;
! ps->tx_aborted_errors++;
! if (status & (TX_NO_CARRIER | TX_LOSS_CARRIER))
! ps->tx_carrier_errors++;
! }
}
}
--- 875,882 ----
if (status & TX_FRAME_ABORTED) {
! ps->tx_errors++;
! ps->tx_aborted_errors++;
! if (status & (TX_NO_CARRIER | TX_LOSS_CARRIER))
! ps->tx_carrier_errors++;
}
}
Index: declance.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/drivers/net/declance.c,v
retrieving revision 1.3
retrieving revision 1.4
diff -C2 -d -r1.3 -r1.4
*** declance.c 2001/08/10 03:04:58 1.3
--- declance.c 2001/08/25 02:19:28 1.4
***************
*** 84,88 ****
#ifndef CONFIG_TC
! unsigned long system_base = 0;
unsigned long dmaptr;
#endif
--- 84,88 ----
#ifndef CONFIG_TC
! unsigned long system_base;
unsigned long dmaptr;
#endif
Index: gt96100eth.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/drivers/net/gt96100eth.c,v
retrieving revision 1.2
retrieving revision 1.3
diff -C2 -d -r1.2 -r1.3
*** gt96100eth.c 2001/08/22 00:33:54 1.2
--- gt96100eth.c 2001/08/25 02:19:28 1.3
***************
*** 25,34 ****
*/
- #ifndef __OPTIMIZE__
- #error You must compile this file with the correct options!
- #error See the last lines of the source file.
- #error You must compile this driver with "-O".
- #endif
-
#ifndef __mips__
#error This driver only works with MIPS architectures!
[...2737 lines suppressed...]
}
! static struct net_device_stats *gt96100_get_stats(struct net_device *dev)
{
! struct gt96100_private *gp = (struct gt96100_private *) dev->priv;
! unsigned long flags;
! if (gt96100_debug > 2)
! printk("%s: gt96100_get_stats: dev=%p\n", dev->name, dev);
! if (netif_device_present(dev)) {
! spin_lock_irqsave(&gp->lock, flags);
! update_stats(gp);
! spin_unlock_irqrestore(&gp->lock, flags);
! }
! return &gp->stats;
}
+
+ module_init(gt96100_probe);
Index: gt96100eth.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/drivers/net/gt96100eth.h,v
retrieving revision 1.2
retrieving revision 1.3
diff -C2 -d -r1.2 -r1.3
*** gt96100eth.h 2001/08/22 00:33:54 1.2
--- gt96100eth.h 2001/08/25 02:19:28 1.3
***************
*** 33,37 ****
#define TX_RING_SIZE 16
#define RX_RING_SIZE 32
! #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
#define RX_HASH_TABLE_SIZE 16384
--- 33,37 ----
#define TX_RING_SIZE 16
#define RX_RING_SIZE 32
! #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer. */
#define RX_HASH_TABLE_SIZE 16384
***************
*** 40,44 ****
#define NUM_INTERFACES 2
! #define GT96100ETH_TX_TIMEOUT HZ/4
#define GT96100_ETH0_BASE (MIPS_GT96100_BASE + GT96100_ETH_PORT_CONFIG)
--- 40,44 ----
#define NUM_INTERFACES 2
! #define GT96100ETH_TX_TIMEOUT HZ
#define GT96100_ETH0_BASE (MIPS_GT96100_BASE + GT96100_ETH_PORT_CONFIG)
***************
*** 53,59 ****
#endif
- #define REV_GT96100 1
- #define REV_GT96100A 3
-
#define GT96100ETH_READ(gp, offset) \
GT96100_READ((gp->port_offset + offset))
--- 53,56 ----
***************
*** 73,130 ****
/* Bit definitions of the SMI Reg */
enum {
! smirDataMask = 0xffff,
! smirPhyAdMask = 0x1f<<16,
! smirPhyAdBit = 16,
! smirRegAdMask = 0x1f<<21,
! smirRegAdBit = 21,
! smirOpCode = 1<<26,
! smirReadValid = 1<<27,
! smirBusy = 1<<28
};
/* Bit definitions of the Port Config Reg */
enum pcr_bits {
! pcrPM = 1,
! pcrRBM = 2,
! pcrPBF = 4,
! pcrEN = 1<<7,
! pcrLPBKMask = 0x3<<8,
! pcrLPBKBit = 8,
! pcrFC = 1<<10,
! pcrHS = 1<<12,
! pcrHM = 1<<13,
! pcrHDM = 1<<14,
! pcrHD = 1<<15,
! pcrISLMask = 0x7<<28,
! pcrISLBit = 28,
! pcrACCS = 1<<31
};
/* Bit definitions of the Port Config Extend Reg */
enum pcxr_bits {
! pcxrIGMP = 1,
! pcxrSPAN = 2,
! pcxrPAR = 4,
! pcxrPRIOtxMask = 0x7<<3,
! pcxrPRIOtxBit = 3,
! pcxrPRIOrxMask = 0x3<<6,
! pcxrPRIOrxBit = 6,
! pcxrPRIOrxOverride = 1<<8,
! pcxrDPLXen = 1<<9,
! pcxrFCTLen = 1<<10,
! pcxrFLP = 1<<11,
! pcxrFCTL = 1<<12,
! pcxrMFLMask = 0x3<<14,
! pcxrMFLBit = 14,
! pcxrMIBclrMode = 1<<16,
! pcxrSpeed = 1<<18,
! pcxrSpeeden = 1<<19,
! pcxrRMIIen = 1<<20,
! pcxrDSCPen = 1<<21
};
/* Bit definitions of the Port Command Reg */
enum pcmr_bits {
! pcmrFJ = 1<<15
};
--- 70,127 ----
/* Bit definitions of the SMI Reg */
enum {
! smirDataMask = 0xffff,
! smirPhyAdMask = 0x1f << 16,
! smirPhyAdBit = 16,
! smirRegAdMask = 0x1f << 21,
! smirRegAdBit = 21,
! smirOpCode = 1 << 26,
! smirReadValid = 1 << 27,
! smirBusy = 1 << 28
};
/* Bit definitions of the Port Config Reg */
enum pcr_bits {
! pcrPM = 1,
! pcrRBM = 2,
! pcrPBF = 4,
! pcrEN = 1 << 7,
! pcrLPBKMask = 0x3 << 8,
! pcrLPBKBit = 8,
! pcrFC = 1 << 10,
! pcrHS = 1 << 12,
! pcrHM = 1 << 13,
! pcrHDM = 1 << 14,
! pcrHD = 1 << 15,
! pcrISLMask = 0x7 << 28,
! pcrISLBit = 28,
! pcrACCS = 1 << 31
};
/* Bit definitions of the Port Config Extend Reg */
enum pcxr_bits {
! pcxrIGMP = 1,
! pcxrSPAN = 2,
! pcxrPAR = 4,
! pcxrPRIOtxMask = 0x7 << 3,
! pcxrPRIOtxBit = 3,
! pcxrPRIOrxMask = 0x3 << 6,
! pcxrPRIOrxBit = 6,
! pcxrPRIOrxOverride = 1 << 8,
! pcxrDPLXen = 1 << 9,
! pcxrFCTLen = 1 << 10,
! pcxrFLP = 1 << 11,
! pcxrFCTL = 1 << 12,
! pcxrMFLMask = 0x3 << 14,
! pcxrMFLBit = 14,
! pcxrMIBclrMode = 1 << 16,
! pcxrSpeed = 1 << 18,
! pcxrSpeeden = 1 << 19,
! pcxrRMIIen = 1 << 20,
! pcxrDSCPen = 1 << 21
};
/* Bit definitions of the Port Command Reg */
enum pcmr_bits {
! pcmrFJ = 1 << 15
};
***************
*** 132,335 ****
/* Bit definitions of the Port Status Reg */
enum psr_bits {
! psrSpeed = 1,
! psrDuplex = 2,
! psrFctl = 4,
! psrLink = 8,
! psrPause = 1<<4,
! psrTxLow = 1<<5,
! psrTxHigh = 1<<6,
! psrTxInProg = 1<<7
};
/* Bit definitions of the SDMA Config Reg */
enum sdcr_bits {
! sdcrRCMask = 0xf<<2,
! sdcrRCBit = 2,
! sdcrBLMR = 1<<6,
! sdcrBLMT = 1<<7,
! sdcrPOVR = 1<<8,
! sdcrRIFB = 1<<9,
! sdcrBSZMask = 0x3<<12,
! sdcrBSZBit = 12
};
/* Bit definitions of the SDMA Command Reg */
enum sdcmr_bits {
! sdcmrERD = 1<<7,
! sdcmrAR = 1<<15,
! sdcmrSTDH = 1<<16,
! sdcmrSTDL = 1<<17,
! sdcmrTXDH = 1<<23,
! sdcmrTXDL = 1<<24,
! sdcmrAT = 1<<31
};
/* Bit definitions of the Interrupt Cause Reg */
enum icr_bits {
! icrRxBuffer = 1,
! icrTxBufferHigh = 1<<2,
! icrTxBufferLow = 1<<3,
! icrTxEndHigh = 1<<6,
! icrTxEndLow = 1<<7,
! icrRxError = 1<<8,
! icrTxErrorHigh = 1<<10,
! icrTxErrorLow = 1<<11,
! icrRxOVR = 1<<12,
! icrTxUdr = 1<<13,
! icrRxBufferQ0 = 1<<16,
! icrRxBufferQ1 = 1<<17,
! icrRxBufferQ2 = 1<<18,
! icrRxBufferQ3 = 1<<19,
! icrRxErrorQ0 = 1<<20,
! icrRxErrorQ1 = 1<<21,
! icrRxErrorQ2 = 1<<22,
! icrRxErrorQ3 = 1<<23,
! icrMIIPhySTC = 1<<28,
! icrSMIdone = 1<<29,
! icrEtherIntSum = 1<<31
};
/* The Rx and Tx descriptor lists. */
typedef struct {
! #ifdef DESC_BE
! u16 byte_cnt;
! u16 reserved;
! #else
! u16 reserved;
! u16 byte_cnt;
! #endif
! u32 cmdstat;
! u32 next;
! u32 buff_ptr;
! } gt96100_td_t __attribute__ ((packed));
typedef struct {
! #ifdef DESC_BE
! u16 buff_sz;
! u16 byte_cnt;
! #else
! u16 byte_cnt;
! u16 buff_sz;
! #endif
! u32 cmdstat;
! u32 next;
! u32 buff_ptr;
! } gt96100_rd_t __attribute__ ((packed));
/* Values for the Tx command-status descriptor entry. */
enum td_cmdstat {
! txOwn = 1<<31,
! txAutoMode = 1<<30,
! txEI = 1<<23,
! txGenCRC = 1<<22,
! txPad = 1<<18,
! txFirst = 1<<17,
! txLast = 1<<16,
! txErrorSummary = 1<<15,
! txReTxCntMask = 0x0f<<10,
! txReTxCntBit = 10,
! txCollision = 1<<9,
! txReTxLimit = 1<<8,
! txUnderrun = 1<<6,
! txLateCollision = 1<<5
};
/* Values for the Rx command-status descriptor entry. */
enum rd_cmdstat {
! rxOwn = 1<<31,
! rxAutoMode = 1<<30,
! rxEI = 1<<23,
! rxFirst = 1<<17,
! rxLast = 1<<16,
! rxErrorSummary = 1<<15,
! rxIGMP = 1<<14,
! rxHashExpired = 1<<13,
! rxMissedFrame = 1<<12,
! rxFrameType = 1<<11,
! rxShortFrame = 1<<8,
! rxMaxFrameLen = 1<<7,
! rxOverrun = 1<<6,
! rxCollision = 1<<4,
! rxCRCError = 1
};
/* Bit fields of a Hash Table Entry */
enum hash_table_entry {
! hteValid = 1,
! hteSkip = 2,
! hteRD = 4
};
// The MIB counters
typedef struct {
! u32 byteReceived;
! u32 byteSent;
! u32 framesReceived;
! u32 framesSent;
! u32 totalByteReceived;
! u32 totalFramesReceived;
! u32 broadcastFramesReceived;
! u32 multicastFramesReceived;
! u32 cRCError;
! u32 oversizeFrames;
! u32 fragments;
! u32 jabber;
! u32 collision;
! u32 lateCollision;
! u32 frames64;
! u32 frames65_127;
! u32 frames128_255;
! u32 frames256_511;
! u32 frames512_1023;
! u32 frames1024_MaxSize;
! u32 macRxError;
! u32 droppedFrames;
! u32 outMulticastFrames;
! u32 outBroadcastFrames;
! u32 undersizeFrames;
} mib_counters_t;
struct gt96100_private {
! gt96100_rd_t* rx_ring;
! gt96100_td_t* tx_ring;
! // The Rx and Tx rings must be 16-byte aligned
! dma_addr_t rx_ring_dma;
! dma_addr_t tx_ring_dma;
! char* hash_table;
! // The Hash Table must be 8-byte aligned
! dma_addr_t hash_table_dma;
! int hash_mode;
!
! // The Rx buffers must be 8-byte aligned
! char* rx_buff;
! dma_addr_t rx_buff_dma;
! // Tx buffers (tx_skbuff[i]->data) with less than 8 bytes
! // of payload must be 8-byte aligned
! struct sk_buff* tx_skbuff[TX_RING_SIZE];
! int rx_next_out; /* The next free ring entry to receive */
! int tx_next_in; /* The next free ring entry to send */
! int tx_next_out; /* The last ring entry the ISR processed */
! int tx_count; /* current # of pkts waiting to be sent in Tx ring */
! int intr_work_done; /* number of Rx and Tx pkts processed in the isr */
! int tx_full; /* Tx ring is full */
!
! mib_counters_t mib;
! struct net_device_stats stats;
! int io_size;
! int port_num; // 0 or 1
! int chip_rev;
! u32 port_offset;
!
! int phy_addr; // PHY address
! u32 last_psr; // last value of the port status register
! int options; /* User-settable misc. driver options. */
! int drv_flags;
! spinlock_t lock; /* Serialise access to device */
};
--- 129,324 ----
/* Bit definitions of the Port Status Reg */
enum psr_bits {
! psrSpeed = 1,
! psrDuplex = 2,
! psrFctl = 4,
! psrLink = 8,
! psrPause = 1 << 4,
! psrTxLow = 1 << 5,
! psrTxHigh = 1 << 6,
! psrTxInProg = 1 << 7
};
/* Bit definitions of the SDMA Config Reg */
enum sdcr_bits {
! sdcrRCMask = 0xf << 2,
! sdcrRCBit = 2,
! sdcrBLMR = 1 << 6,
! sdcrBLMT = 1 << 7,
! sdcrPOVR = 1 << 8,
! sdcrRIFB = 1 << 9,
! sdcrBSZMask = 0x3 << 12,
! sdcrBSZBit = 12
};
/* Bit definitions of the SDMA Command Reg */
enum sdcmr_bits {
! sdcmrERD = 1 << 7,
! sdcmrAR = 1 << 15,
! sdcmrSTDH = 1 << 16,
! sdcmrSTDL = 1 << 17,
! sdcmrTXDH = 1 << 23,
! sdcmrTXDL = 1 << 24,
! sdcmrAT = 1 << 31
};
/* Bit definitions of the Interrupt Cause Reg */
enum icr_bits {
! icrRxBuffer = 1,
! icrTxBufferHigh = 1 << 2,
! icrTxBufferLow = 1 << 3,
! icrTxEndHigh = 1 << 6,
! icrTxEndLow = 1 << 7,
! icrRxError = 1 << 8,
! icrTxErrorHigh = 1 << 10,
! icrTxErrorLow = 1 << 11,
! icrRxOVR = 1 << 12,
! icrTxUdr = 1 << 13,
! icrRxBufferQ0 = 1 << 16,
! icrRxBufferQ1 = 1 << 17,
! icrRxBufferQ2 = 1 << 18,
! icrRxBufferQ3 = 1 << 19,
! icrRxErrorQ0 = 1 << 20,
! icrRxErrorQ1 = 1 << 21,
! icrRxErrorQ2 = 1 << 22,
! icrRxErrorQ3 = 1 << 23,
! icrMIIPhySTC = 1 << 28,
! icrSMIdone = 1 << 29,
! icrEtherIntSum = 1 << 31
};
/* The Rx and Tx descriptor lists. */
+
typedef struct {
! u32 cmdstat;
! u32 byte_cnt;
! u32 buff_ptr;
! u32 next;
! } gt96100_td_t;
!
! #define tdByteCntBit 16
typedef struct {
! u32 cmdstat;
! u32 buff_cnt_sz;
! u32 buff_ptr;
! u32 next;
! } gt96100_rd_t;
!
! #define rdBuffSzBit 16
! #define rdByteCntMask 0xffff
/* Values for the Tx command-status descriptor entry. */
enum td_cmdstat {
! txOwn = 1 << 31,
! txAutoMode = 1 << 30,
! txEI = 1 << 23,
! txGenCRC = 1 << 22,
! txPad = 1 << 18,
! txFirst = 1 << 17,
! txLast = 1 << 16,
! txErrorSummary = 1 << 15,
! txReTxCntMask = 0x0f << 10,
! txReTxCntBit = 10,
! txCollision = 1 << 9,
! txReTxLimit = 1 << 8,
! txUnderrun = 1 << 6,
! txLateCollision = 1 << 5
};
+ #define TxReTxCntBit 10
/* Values for the Rx command-status descriptor entry. */
enum rd_cmdstat {
! rxOwn = 1 << 31,
! rxAutoMode = 1 << 30,
! rxEI = 1 << 23,
! rxFirst = 1 << 17,
! rxLast = 1 << 16,
! rxErrorSummary = 1 << 15,
! rxIGMP = 1 << 14,
! rxHashExpired = 1 << 13,
! rxMissedFrame = 1 << 12,
! rxFrameType = 1 << 11,
! rxShortFrame = 1 << 8,
! rxMaxFrameLen = 1 << 7,
! rxOverrun = 1 << 6,
! rxCollision = 1 << 4,
! rxCRCError = 1
};
/* Bit fields of a Hash Table Entry */
enum hash_table_entry {
! hteValid = 1,
! hteSkip = 2,
! hteRD = 4
};
// The MIB counters
typedef struct {
! u32 byteReceived;
! u32 byteSent;
! u32 framesReceived;
! u32 framesSent;
! u32 totalByteReceived;
! u32 totalFramesReceived;
! u32 broadcastFramesReceived;
! u32 multicastFramesReceived;
! u32 cRCError;
! u32 oversizeFrames;
! u32 fragments;
! u32 jabber;
! u32 collision;
! u32 lateCollision;
! u32 frames64;
! u32 frames65_127;
! u32 frames128_255;
! u32 frames256_511;
! u32 frames512_1023;
! u32 frames1024_MaxSize;
! u32 macRxError;
! u32 droppedFrames;
! u32 outMulticastFrames;
! u32 outBroadcastFrames;
! u32 undersizeFrames;
} mib_counters_t;
struct gt96100_private {
! gt96100_rd_t *rx_ring;
! gt96100_td_t *tx_ring;
! // The Rx and Tx rings must be 16-byte aligned
! dma_addr_t rx_ring_dma;
! dma_addr_t tx_ring_dma;
! char *hash_table;
! // The Hash Table must be 8-byte aligned
! dma_addr_t hash_table_dma;
! int hash_mode;
! // The Rx buffers must be 8-byte aligned
! char *rx_buff[RX_RING_SIZE];
! // Tx buffers (tx_skbuff[i]->data) with less than 8 bytes
! // of payload must be 8-byte aligned
! struct sk_buff *tx_skbuff[TX_RING_SIZE];
! int rx_next_out; /* The next free ring entry to receive */
! int tx_next_in; /* The next free ring entry to send */
! int tx_next_out; /* The last ring entry the ISR processed */
! int tx_count; /* current # of pkts waiting to be sent in Tx ring */
! mib_counters_t mib;
! struct net_device_stats stats;
!
! int io_size;
! int port_num; // 0 or 1
! u32 port_offset;
!
! int phy_addr; // PHY address
! u32 last_psr; // last value of the port status register
!
! int options; /* User-settable misc. driver options. */
! int drv_flags;
! unsigned char phys[2]; /* MII device addresses. */
! spinlock_t lock; /* Serialise access to device */
};
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