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[Linux-mips-commits]CVS: linux/arch/mips/kernel pci_auto.c,1.1,1.2 proc.c,1.5,1.6 ptrace.c,1.3,1.4 setup.c,1.9,1.10 time.c,1.6,1.7 unaligned.c,1.3,1.4
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From: Paul M. <le...@us...> - 2001-08-25 02:19:31
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Update of /cvsroot/linux-mips/linux/arch/mips/kernel
In directory usw-pr-cvs1:/tmp/cvs-serv13548/arch/mips/kernel
Modified Files:
pci_auto.c proc.c ptrace.c setup.c time.c unaligned.c
Log Message:
Sync to 2.4.7
Index: pci_auto.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/kernel/pci_auto.c,v
retrieving revision 1.1
retrieving revision 1.2
diff -C2 -d -r1.1 -r1.2
*** pci_auto.c 2001/07/07 19:37:24 1.1
--- pci_auto.c 2001/08/25 02:19:27 1.2
***************
*** 1,5 ****
/*
- * arch/mips/kernel/pci_auto.c
- *
* PCI autoconfiguration library
*
--- 1,3 ----
***************
*** 38,43 ****
#endif
! /* These are used for config access before all the PCI probing
! has been done. */
int early_read_config_byte(struct pci_channel *hose, int bus, int dev_fn, int where, u8 *val);
int early_read_config_word(struct pci_channel *hose, int bus, int dev_fn, int where, u16 *val);
--- 36,40 ----
#endif
! /* These are used for config access before all the PCI probing has been done. */
int early_read_config_byte(struct pci_channel *hose, int bus, int dev_fn, int where, u8 *val);
int early_read_config_word(struct pci_channel *hose, int bus, int dev_fn, int where, u16 *val);
***************
*** 67,72 ****
current_bus, PCI_SLOT(pci_devfn), PCI_FUNC(pci_devfn) );
! for (bar = PCI_BASE_ADDRESS_0; bar <= PCI_BASE_ADDRESS_5; bar+=4)
! {
/* Tickle the BAR and get the response */
early_write_config_dword(hose,
--- 64,68 ----
current_bus, PCI_SLOT(pci_devfn), PCI_FUNC(pci_devfn) );
! for (bar = PCI_BASE_ADDRESS_0; bar <= PCI_BASE_ADDRESS_5; bar+=4) {
/* Tickle the BAR and get the response */
early_write_config_dword(hose,
***************
*** 86,100 ****
/* Check the BAR type and set our address mask */
! if (bar_response & PCI_BASE_ADDRESS_SPACE)
! {
addr_mask = PCI_BASE_ADDRESS_IO_MASK;
upper_limit = &pciauto_upper_iospc;
lower_limit = &pciauto_lower_iospc;
DBG("PCI Autoconfig: BAR %d, I/O, ", bar_nr);
! }
! else
! {
! if ( (bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
! PCI_BASE_ADDRESS_MEM_TYPE_64)
found_mem64 = 1;
--- 82,93 ----
/* Check the BAR type and set our address mask */
! if (bar_response & PCI_BASE_ADDRESS_SPACE) {
addr_mask = PCI_BASE_ADDRESS_IO_MASK;
upper_limit = &pciauto_upper_iospc;
lower_limit = &pciauto_lower_iospc;
DBG("PCI Autoconfig: BAR %d, I/O, ", bar_nr);
! } else {
! if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
! PCI_BASE_ADDRESS_MEM_TYPE_64)
found_mem64 = 1;
***************
*** 110,121 ****
/* Allocate a base address */
bar_value = ((*lower_limit - 1) & ~(bar_size - 1)) + bar_size;
- MIPS_ASSERT(bar_value + bar_size <= *upper_limit);
/* Write it out and update our limit */
! early_write_config_dword(hose,
! current_bus,
! pci_devfn,
! bar,
! bar_value);
*lower_limit = bar_value + bar_size;
--- 103,110 ----
/* Allocate a base address */
bar_value = ((*lower_limit - 1) & ~(bar_size - 1)) + bar_size;
/* Write it out and update our limit */
! early_write_config_dword(hose, current_bus, pci_devfn,
! bar, bar_value);
*lower_limit = bar_value + bar_size;
***************
*** 126,131 ****
* in the lower 4GB of memory.
*/
! if (found_mem64)
! {
bar += 4;
early_write_config_dword(hose,
--- 115,119 ----
* in the lower 4GB of memory.
*/
! if (found_mem64) {
bar += 4;
early_write_config_dword(hose,
***************
*** 153,171 ****
/* Configure bus number registers */
! early_write_config_byte(hose,
! current_bus,
! pci_devfn,
! PCI_PRIMARY_BUS,
! current_bus);
! early_write_config_byte(hose,
! current_bus,
! pci_devfn,
! PCI_SECONDARY_BUS,
! sub_bus + 1);
! early_write_config_byte(hose,
! current_bus,
! pci_devfn,
! PCI_SUBORDINATE_BUS,
! 0xff);
/* Round memory allocator to 1MB boundary */
--- 141,150 ----
/* Configure bus number registers */
! early_write_config_byte(hose, current_bus, pci_devfn,
! PCI_PRIMARY_BUS, current_bus);
! early_write_config_byte(hose, current_bus, pci_devfn,
! PCI_SECONDARY_BUS, sub_bus + 1);
! early_write_config_byte(hose, current_bus, pci_devfn,
! PCI_SUBORDINATE_BUS, 0xff);
/* Round memory allocator to 1MB boundary */
***************
*** 176,220 ****
/* Set up memory and I/O filter limits, assume 32-bit I/O space */
! early_write_config_word(hose,
! current_bus,
! pci_devfn,
! PCI_MEMORY_LIMIT,
((pciauto_upper_memspc - 1) & 0xfff00000) >> 16);
! early_write_config_byte(hose,
! current_bus,
! pci_devfn,
! PCI_IO_LIMIT,
((pciauto_upper_iospc - 1) & 0x0000f000) >> 8);
! early_write_config_word(hose,
! current_bus,
! pci_devfn,
PCI_IO_LIMIT_UPPER16,
((pciauto_upper_iospc - 1) & 0xffff0000) >> 16);
/* We don't support prefetchable memory for now, so disable */
! early_write_config_word(hose,
! current_bus,
! pci_devfn,
! PCI_PREF_MEMORY_BASE,
! 0x1000);
! early_write_config_word(hose,
! current_bus,
! pci_devfn,
! PCI_PREF_MEMORY_LIMIT,
! 0x1000);
/* Enable memory and I/O accesses, enable bus master */
! early_read_config_dword(hose,
! current_bus,
! pci_devfn,
! PCI_COMMAND,
&cmdstat);
! early_write_config_dword(hose,
! current_bus,
! pci_devfn,
! PCI_COMMAND,
! cmdstat |
! PCI_COMMAND_IO |
! PCI_COMMAND_MEMORY |
PCI_COMMAND_MASTER);
}
--- 155,177 ----
/* Set up memory and I/O filter limits, assume 32-bit I/O space */
! early_write_config_word(hose, current_bus, pci_devfn, PCI_MEMORY_LIMIT,
((pciauto_upper_memspc - 1) & 0xfff00000) >> 16);
! early_write_config_byte(hose, current_bus, pci_devfn, PCI_IO_LIMIT,
((pciauto_upper_iospc - 1) & 0x0000f000) >> 8);
! early_write_config_word(hose, current_bus, pci_devfn,
PCI_IO_LIMIT_UPPER16,
((pciauto_upper_iospc - 1) & 0xffff0000) >> 16);
/* We don't support prefetchable memory for now, so disable */
! early_write_config_word(hose, current_bus, pci_devfn,
! PCI_PREF_MEMORY_BASE, 0x1000);
! early_write_config_word(hose, current_bus, pci_devfn,
! PCI_PREF_MEMORY_LIMIT, 0x1000);
/* Enable memory and I/O accesses, enable bus master */
! early_read_config_dword(hose, current_bus, pci_devfn, PCI_COMMAND,
&cmdstat);
! early_write_config_dword(hose, current_bus, pci_devfn, PCI_COMMAND,
! cmdstat | PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
PCI_COMMAND_MASTER);
}
***************
*** 227,256 ****
{
/* Configure bus number registers */
! early_write_config_byte(hose,
! current_bus,
! pci_devfn,
! PCI_SUBORDINATE_BUS,
! sub_bus);
/* Round memory allocator to 1MB boundary */
pciauto_upper_memspc &= ~(0x100000 - 1);
! early_write_config_word(hose,
! current_bus,
! pci_devfn,
! PCI_MEMORY_BASE,
pciauto_upper_memspc >> 16);
/* Round I/O allocator to 4KB boundary */
pciauto_upper_iospc &= ~(0x1000 - 1);
! early_write_config_byte(hose,
! current_bus,
! pci_devfn,
! PCI_IO_BASE,
(pciauto_upper_iospc & 0x0000f000) >> 8);
! early_write_config_word(hose,
! current_bus,
! pci_devfn,
! PCI_IO_BASE_UPPER16,
! pciauto_upper_iospc >> 16);
}
--- 184,201 ----
{
/* Configure bus number registers */
! early_write_config_byte(hose, current_bus, pci_devfn,
! PCI_SUBORDINATE_BUS, sub_bus);
/* Round memory allocator to 1MB boundary */
pciauto_upper_memspc &= ~(0x100000 - 1);
! early_write_config_word(hose, current_bus, pci_devfn, PCI_MEMORY_BASE,
pciauto_upper_memspc >> 16);
/* Round I/O allocator to 4KB boundary */
pciauto_upper_iospc &= ~(0x1000 - 1);
! early_write_config_byte(hose, current_bus, pci_devfn, PCI_IO_BASE,
(pciauto_upper_iospc & 0x0000f000) >> 8);
! early_write_config_word(hose, current_bus, pci_devfn,
! PCI_IO_BASE_UPPER16, pciauto_upper_iospc >> 16);
}
***************
*** 279,314 ****
continue;
! early_read_config_byte(hose,
! current_bus,
! pci_devfn,
! PCI_HEADER_TYPE,
! &header_type);
if (!PCI_FUNC(pci_devfn))
found_multi = header_type & 0x80;
! early_read_config_word(hose,
! current_bus,
! pci_devfn,
! PCI_VENDOR_ID,
! &vid);
if (vid == 0xffff) continue;
! early_read_config_dword(hose,
! current_bus,
! pci_devfn,
PCI_CLASS_REVISION, &pci_class);
! if ( (pci_class >> 16) == PCI_CLASS_BRIDGE_PCI ) {
DBG("PCI Autoconfig: Found P2P bridge, device %d\n", PCI_SLOT(pci_devfn));
! pciauto_prescan_setup_bridge(hose,
! current_bus,
! pci_devfn,
! sub_bus);
sub_bus = pciauto_bus_scan(hose, sub_bus+1);
! pciauto_postscan_setup_bridge(hose,
! current_bus,
! pci_devfn,
! sub_bus);
} else if ((pci_class >> 16) == PCI_CLASS_STORAGE_IDE) {
--- 224,247 ----
continue;
! early_read_config_byte(hose, current_bus, pci_devfn,
! PCI_HEADER_TYPE, &header_type);
if (!PCI_FUNC(pci_devfn))
found_multi = header_type & 0x80;
! early_read_config_word(hose, current_bus, pci_devfn,
! PCI_VENDOR_ID, &vid);
if (vid == 0xffff) continue;
! early_read_config_dword(hose, current_bus, pci_devfn,
PCI_CLASS_REVISION, &pci_class);
! if ((pci_class >> 16) == PCI_CLASS_BRIDGE_PCI) {
DBG("PCI Autoconfig: Found P2P bridge, device %d\n", PCI_SLOT(pci_devfn));
! pciauto_prescan_setup_bridge(hose, current_bus,
! pci_devfn, sub_bus);
sub_bus = pciauto_bus_scan(hose, sub_bus+1);
! pciauto_postscan_setup_bridge(hose, current_bus,
! pci_devfn, sub_bus);
} else if ((pci_class >> 16) == PCI_CLASS_STORAGE_IDE) {
***************
*** 316,324 ****
unsigned char prg_iface;
! early_read_config_byte(hose,
! current_bus,
! pci_devfn,
! PCI_CLASS_PROG,
! &prg_iface);
if (!(prg_iface & PCIAUTO_IDE_MODE_MASK)) {
DBG("PCI Autoconfig: Skipping legacy mode IDE controller\n");
--- 249,254 ----
unsigned char prg_iface;
! early_read_config_byte(hose, current_bus, pci_devfn,
! PCI_CLASS_PROG, &prg_iface);
if (!(prg_iface & PCIAUTO_IDE_MODE_MASK)) {
DBG("PCI Autoconfig: Skipping legacy mode IDE controller\n");
***************
*** 331,357 ****
* settings
*/
! early_read_config_dword(hose,
! current_bus,
! pci_devfn,
! PCI_COMMAND,
! &cmdstat);
! early_write_config_dword(hose,
! current_bus,
! pci_devfn,
! PCI_COMMAND,
! cmdstat |
! PCI_COMMAND_IO |
PCI_COMMAND_MEMORY |
PCI_COMMAND_MASTER);
! early_write_config_byte(hose,
! current_bus,
! pci_devfn,
! PCI_LATENCY_TIMER,
! 0x80);
! /* Allocate PCI I/O and/or memory space */
! pciauto_setup_bars(hose,
! current_bus,
! pci_devfn);
}
return sub_bus;
--- 261,275 ----
* settings
*/
! early_read_config_dword(hose, current_bus, pci_devfn,
! PCI_COMMAND, &cmdstat);
! early_write_config_dword(hose, current_bus, pci_devfn,
! PCI_COMMAND, cmdstat | PCI_COMMAND_IO |
PCI_COMMAND_MEMORY |
PCI_COMMAND_MASTER);
! early_write_config_byte(hose, current_bus, pci_devfn,
! PCI_LATENCY_TIMER, 0x80);
! /* Allocate PCI I/O and/or memory space */
! pciauto_setup_bars(hose, current_bus, pci_devfn);
}
return sub_bus;
***************
*** 375,398 ****
* and all of the pci_dev and pci_bus structures have been created.
*/
! static struct pci_dev *
! fake_pci_dev(struct pci_channel *hose, int busnr, int devfn)
{
! static struct pci_dev dev;
! static struct pci_bus bus;
! dev.bus = &bus;
! dev.sysdata = hose;
! dev.devfn = devfn;
! bus.number = busnr;
! bus.ops = hose->pci_ops;
! return &dev;
}
! #define EARLY_PCI_OP(rw, size, type) \
! int early_##rw##_config_##size(struct pci_channel *hose, int bus, \
! int devfn, int offset, type value) \
! { \
! return pci_##rw##_config_##size(fake_pci_dev(hose, bus, devfn), \
! offset, value); \
}
--- 293,317 ----
* and all of the pci_dev and pci_bus structures have been created.
*/
! static struct pci_dev *fake_pci_dev(struct pci_channel *hose, int busnr,
! int devfn)
{
! static struct pci_dev dev;
! static struct pci_bus bus;
! dev.bus = &bus;
! dev.sysdata = hose;
! dev.devfn = devfn;
! bus.number = busnr;
! bus.ops = hose->pci_ops;
!
! return &dev;
}
! #define EARLY_PCI_OP(rw, size, type) \
! int early_##rw##_config_##size(struct pci_channel *hose, int bus, \
! int devfn, int offset, type value) \
! { \
! return pci_##rw##_config_##size(fake_pci_dev(hose, bus, devfn), \
! offset, value); \
}
Index: proc.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/kernel/proc.c,v
retrieving revision 1.5
retrieving revision 1.6
diff -C2 -d -r1.5 -r1.6
*** proc.c 2001/08/23 19:13:56 1.5
--- proc.c 2001/08/25 02:19:27 1.6
***************
*** 15,19 ****
#include <asm/watch.h>
! unsigned long unaligned_instructions;
unsigned int vced_count, vcei_count;
#ifndef CONFIG_CPU_HAS_LLSC
--- 15,19 ----
#include <asm/watch.h>
! extern unsigned long unaligned_instructions;
unsigned int vced_count, vcei_count;
#ifndef CONFIG_CPU_HAS_LLSC
Index: ptrace.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/kernel/ptrace.c,v
retrieving revision 1.3
retrieving revision 1.4
diff -C2 -d -r1.3 -r1.4
*** ptrace.c 2001/07/16 18:00:30 1.3
--- ptrace.c 2001/08/25 02:19:27 1.4
***************
*** 67,98 ****
if (request == PTRACE_ATTACH) {
! if (child == current)
! goto out_tsk;
! if ((!child->dumpable ||
! (current->uid != child->euid) ||
! (current->uid != child->suid) ||
! (current->uid != child->uid) ||
! (current->gid != child->egid) ||
! (current->gid != child->sgid) ||
! (current->gid != child->gid) ||
! (!cap_issubset(child->cap_permitted,
! current->cap_permitted)) ||
! (current->gid != child->gid)) && !capable(CAP_SYS_PTRACE))
! goto out_tsk;
! /* the same process cannot be attached many times */
! if (child->ptrace & PT_PTRACED)
! goto out_tsk;
! child->ptrace |= PT_PTRACED;
!
! write_lock_irq(&tasklist_lock);
! if (child->p_pptr != current) {
! REMOVE_LINKS(child);
! child->p_pptr = current;
! SET_LINKS(child);
! }
! write_unlock_irq(&tasklist_lock);
!
! send_sig(SIGSTOP, child, 1);
! res = 0;
goto out_tsk;
}
--- 67,71 ----
if (request == PTRACE_ATTACH) {
! res = ptrace_attach(child);
goto out_tsk;
}
Index: setup.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/kernel/setup.c,v
retrieving revision 1.9
retrieving revision 1.10
diff -C2 -d -r1.9 -r1.10
*** setup.c 2001/08/23 19:13:56 1.9
--- setup.c 2001/08/25 02:19:27 1.10
***************
*** 347,354 ****
}
break;
case PRID_COMP_ALCHEMY:
switch (mips_cpu.processor_id & 0xff00) {
! case PRID_IMP_AU1_REV1:
! case PRID_IMP_AU1_REV2:
mips_cpu.cputype = CPU_AU1000;
mips_cpu.isa_level = MIPS_CPU_ISA_M32;
--- 347,355 ----
}
break;
+ #endif
case PRID_COMP_ALCHEMY:
switch (mips_cpu.processor_id & 0xff00) {
! #ifdef CONFIG_CPU_MIPS32
! case PRID_IMP_AU1000:
mips_cpu.cputype = CPU_AU1000;
mips_cpu.isa_level = MIPS_CPU_ISA_M32;
***************
*** 365,368 ****
--- 366,370 ----
mips_cpu.scache.flags = MIPS_CACHE_NOT_PRESENT;
break;
+ #endif
default:
mips_cpu.cputype = CPU_UNKNOWN;
***************
*** 370,374 ****
}
break;
- #endif
case PRID_COMP_SIBYTE:
switch (mips_cpu.processor_id & 0xff00) {
--- 372,375 ----
Index: time.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/kernel/time.c,v
retrieving revision 1.6
retrieving revision 1.7
diff -C2 -d -r1.6 -r1.7
*** time.c 2001/08/23 04:20:15 1.6
--- time.c 2001/08/25 02:19:27 1.7
***************
*** 3,8 ****
* Author: Jun Sun, js...@mv... or js...@ju...
*
! * Common time service routines for MIPS machines. See
! * Documents/MIPS/README.txt.
*
* This program is free software; you can redistribute it and/or modify it
--- 3,7 ----
* Author: Jun Sun, js...@mv... or js...@ju...
*
! * Common time service routines for MIPS machines. See Documents/MIPS/time.txt.
*
* This program is free software; you can redistribute it and/or modify it
Index: unaligned.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/kernel/unaligned.c,v
retrieving revision 1.3
retrieving revision 1.4
diff -C2 -d -r1.3 -r1.4
*** unaligned.c 2001/08/10 18:02:27 1.3
--- unaligned.c 2001/08/25 02:19:27 1.4
***************
*** 73,76 ****
--- 73,77 ----
* Undo the partial store in this case.
*/
+ #include <linux/config.h>
#include <linux/mm.h>
#include <linux/signal.h>
***************
*** 379,400 ****
}
unsigned long unaligned_instructions;
asmlinkage void do_ade(struct pt_regs *regs)
{
unsigned long pc;
! extern int do_dsemulret(struct pt_regs *);
! /*
! * Address errors may be deliberately induced
! * by the FPU emulator to take retake control
! * of the CPU after executing the instruction
! * in the delay slot of an emulated branch.
! */
! if((unsigned long)regs->cp0_epc == current->thread.dsemul_aerpc) {
! (void)do_dsemulret(regs);
! return;
! }
/*
--- 380,403 ----
}
+ #ifdef CONFIG_PROC_FS
unsigned long unaligned_instructions;
+ #endif
asmlinkage void do_ade(struct pt_regs *regs)
{
unsigned long pc;
! extern int do_dsemulret(struct pt_regs *);
! /*
! * Address errors may be deliberately induced
! * by the FPU emulator to take retake control
! * of the CPU after executing the instruction
! * in the delay slot of an emulated branch.
! */
! if ((unsigned long)regs->cp0_epc == current->thread.dsemul_aerpc) {
! do_dsemulret(regs);
! return;
! }
/*
***************
*** 413,417 ****
--- 416,422 ----
emulate_load_store_insn(regs, regs->cp0_badvaddr, pc);
+ #ifdef CONFIG_PROC_FS
unaligned_instructions++;
+ #endif
return;
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