linux-mips-commits

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/include/asm-mips64
In directory usw-pr-cvs1:/tmp/cvs-serv29100/include/asm-mips64

Modified Files:
	asm.h bootinfo.h branch.h cache.h cpu.h fpu_emulator.h 
	mipsregs.h mmu_context.h processor.h serial.h spinlock.h 
Added Files:
	elf.h irq_cpu.h 
Log Message:
Updated Mips 64 to OSS tree.


--- NEW FILE: irq_cpu.h ---
/*
 *	include/asm-mips/irq_cpu.h
 *
 *	MIPS CPU interrupt definitions.
 *
 *	Copyright (C) 2002  Maciej W. Rozycki
 *
 *	This program is free software; you can redistribute it and/or
 *	modify it under the terms of the GNU General Public License
 *	as published by the Free Software Foundation; either version
 *	2 of the License, or (at your option) any later version.
 */
#ifndef __ASM_MIPS64_IRQ_CPU_H
#define __ASM_MIPS64_IRQ_CPU_H

extern void mips_cpu_irq_init(int irq_base);

#endif /* __ASM_MIPS64_IRQ_CPU_H */

Index: asm.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips64/asm.h,v
retrieving revision 1.9
retrieving revision 1.10
diff -u -d -r1.9 -r1.10
--- asm.h	21 Apr 2002 20:06:20 -0000	1.9
+++ asm.h	30 May 2002 20:42:15 -0000	1.10
@@ -174,12 +174,12 @@
 9:
 #endif /* (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3) */
 #if (_MIPS_ISA == _MIPS_ISA_MIPS4 ) || (_MIPS_ISA == _MIPS_ISA_MIPS5) || \
-    (_MIPS_ISA == _MIPS_ISA_MIPS64)
+    (_MIPS_ISA == _MIPS_ISA_MIPS32) || (_MIPS_ISA == _MIPS_ISA_MIPS64)
 #define MOVN(rd,rs,rt)                                  \
 		movn	rd,rs,rt
 #define MOVZ(rd,rs,rt)                                  \
 		movz	rd,rs,rt
-#endif /* MIPS IV, MIPS V or MIPS64 */
+#endif /* MIPS IV, MIPS V, MIPS32 or MIPS64 */
 
 /*
  * Stack alignment

Index: bootinfo.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips64/bootinfo.h,v
retrieving revision 1.10
retrieving revision 1.11
diff -u -d -r1.10 -r1.11
--- bootinfo.h	19 Feb 2002 17:17:53 -0000	1.10
+++ bootinfo.h	30 May 2002 20:42:15 -0000	1.11
@@ -156,6 +156,7 @@
  * Valid machtype for group Alchemy
  */
 #define MACH_PB1000	0	         /* Au1000-based eval board */
+#define MACH_PB1500	1	         /* Au1500-based eval board */
  
 /*
  * Valid machtype for group NEC_VR41XX

Index: branch.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips64/branch.h,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- branch.h	31 Oct 2001 18:26:52 -0000	1.1
+++ branch.h	30 May 2002 20:42:15 -0000	1.2
@@ -3,10 +3,11 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Branch and jump emulation.
- *
- * Copyright (C) 1996, 1997, 1998, 1999 by Ralf Baechle
+ * Copyright (C) 1996, 1997, 1998, 2001 by Ralf Baechle
  */
+#ifndef _ASM_BRANCH_H
+#define _ASM_BRANCH_H
+
 #include <asm/ptrace.h>
 
 static inline int delay_slot(struct pt_regs *regs)
@@ -14,6 +15,14 @@
 	return regs->cp0_cause & CAUSEF_BD;
 }
 
+static inline unsigned long exception_epc(struct pt_regs *regs)
+{
+	if (!delay_slot(regs))
+		return regs->cp0_epc;
+
+	return regs->cp0_epc + 4;
+}
+
 extern int __compute_return_epc(struct pt_regs *regs);
 
 static inline int compute_return_epc(struct pt_regs *regs)
@@ -25,3 +34,5 @@
 
 	return __compute_return_epc(regs);
 }
+
+#endif /* _ASM_BRANCH_H */

Index: cache.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips64/cache.h,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- cache.h	21 Nov 2001 22:10:59 -0000	1.3
+++ cache.h	30 May 2002 20:42:15 -0000	1.4
@@ -9,6 +9,8 @@
 #ifndef _ASM_CACHE_H
 #define _ASM_CACHE_H
 
+#include <linux/config.h>
+
 #ifndef _LANGUAGE_ASSEMBLY
 /*
  * Descriptor for a cache

Index: cpu.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips64/cpu.h,v
retrieving revision 1.7
retrieving revision 1.8
diff -u -d -r1.7 -r1.8
--- cpu.h	4 Jan 2002 18:04:53 -0000	1.7
+++ cpu.h	30 May 2002 20:42:15 -0000	1.8
@@ -62,6 +62,7 @@
 #define PRID_IMP_R5500		0x5500
 #define PRID_IMP_4KC		0x8000
 #define PRID_IMP_5KC		0x8100
+#define PRID_IMP_20KC		0x8200
 #define PRID_IMP_4KEC		0x8400
 #define PRID_IMP_4KSC		0x8600
 
@@ -126,7 +127,7 @@
 	CPU_R5000A, CPU_R4640, CPU_NEVADA, CPU_RM7000, CPU_R5432, CPU_4KC,
 	CPU_5KC, CPU_R4310, CPU_SB1, CPU_TX3912, CPU_TX3922, CPU_TX3927,
 	CPU_AU1000, CPU_4KEC, CPU_4KSC, CPU_VR41XX, CPU_R5500, CPU_TX49XX,
-	CPU_TX39XX, CPU_LAST
+	CPU_TX39XX, CPU_AU1500, CPU_20KC, CPU_LAST
 };
 
 #endif
@@ -159,5 +160,6 @@
 #define MIPS_CPU_CACHE_CDEX	0x00000800 /* Create_Dirty_Exclusive CACHE op */
 #define MIPS_CPU_MCHECK		0x00001000 /* Machine check exception */
 #define MIPS_CPU_EJTAG		0x00002000 /* EJTAG exception */
+#define MIPS_CPU_FPUEX		0x00004000 /* FPU exception */
 
 #endif /* _ASM_CPU_H */

Index: fpu_emulator.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips64/fpu_emulator.h,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- fpu_emulator.h	18 Mar 2002 22:25:08 -0000	1.1
+++ fpu_emulator.h	30 May 2002 20:42:15 -0000	1.2
@@ -1,15 +1,4 @@
 /*
- * Definitiona for the Algorithmics FPU Emulator port into MIPS Linux
- */
-/**************************************************************************
- *
- *  include/asm-mips/fpu_emulator.h
- *
- *  Kevin D. Kissell, ke...@mi... and Carsten Langgaard, car...@mi...
- *  Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
- *
- * ########################################################################
- *
  *  This program is free software; you can distribute it and/or modify it
  *  under the terms of the GNU General Public License (Version 2) as
  *  published by the Free Software Foundation.
@@ -23,13 +12,16 @@
  *  with this program; if not, write to the Free Software Foundation, Inc.,
  *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  *
- *************************************************************************/
-/* 
  * Further private data for which no space exists in mips_fpu_soft_struct.
  * This should be subsumed into the mips_fpu_soft_struct structure as
  * defined in processor.h as soon as the absurd wired absolute assembler
  * offsets become dynamic at compile time.
+ *
+ * Kevin D. Kissell, ke...@mi... and Carsten Langgaard, car...@mi...
+ * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
  */
+#ifndef _ASM_FPU_EMULATOR_H
+#define _ASM_FPU_EMULATOR_H
 
 struct mips_fpu_emulator_private {
 	unsigned int eir;
@@ -42,3 +34,5 @@
 		unsigned int errors;
 	} stats;
 };
+
+#endif /* _ASM_FPU_EMULATOR_H */

Index: mipsregs.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips64/mipsregs.h,v
retrieving revision 1.11
retrieving revision 1.12
diff -u -d -r1.11 -r1.12
--- mipsregs.h	26 Feb 2002 17:08:29 -0000	1.11
+++ mipsregs.h	30 May 2002 20:42:15 -0000	1.12
@@ -52,12 +52,15 @@
 #define CP0_XCONTEXT $20
 #define CP0_FRAMEMASK $21
 #define CP0_DIAGNOSTIC $22
+#define CP0_DEBUG $23
+#define CP0_DEPC $24
 #define CP0_PERFORMANCE $25
 #define CP0_ECC $26
 #define CP0_CACHEERR $27
 #define CP0_TAGLO $28
 #define CP0_TAGHI $29
 #define CP0_ERROREPC $30
+#define CP0_DESAVE $31
 
 /*
  * R4640/R4650 cp0 register names.  These registers are listed

Index: mmu_context.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips64/mmu_context.h,v
retrieving revision 1.4
retrieving revision 1.5
diff -u -d -r1.4 -r1.5
--- mmu_context.h	28 Jan 2002 20:32:05 -0000	1.4
+++ mmu_context.h	30 May 2002 20:42:15 -0000	1.5
@@ -27,7 +27,7 @@
 #define TLBMISS_HANDLER_SETUP_PGD(pgd) \
 	pgd_current[smp_processor_id()] = (unsigned long)(pgd)
 #define TLBMISS_HANDLER_SETUP() \
-	set_context((unsigned long) smp_processor_id() << (23 + 3)); \
+	set_context(((long)(&pgd_current[smp_processor_id()])) << 23); \
 	TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir)
 extern unsigned long pgd_current[];
 

Index: processor.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips64/processor.h,v
retrieving revision 1.9
retrieving revision 1.10
diff -u -d -r1.9 -r1.10
--- processor.h	26 Feb 2002 17:34:15 -0000	1.9
+++ processor.h	30 May 2002 20:42:15 -0000	1.10
@@ -15,35 +15,19 @@
 
 /*
  * Return current * instruction pointer ("program counter").
- *
- * Two implementations.  The ``la'' version results in shorter code for
- * the kernel which we assume to reside in the 32-bit compat address space.
- * The  ``jal'' version is for use by modules which live in outer space.
- * This is just a single instruction unlike the long dla macro expansion.
  */
-#ifdef MODULE
-#define current_text_addr()						\
-({									\
-	void *_a;							\
-									\
-	__asm__ ("jal\t1f, %0\n\t"					\
-		"1:"							\
-		: "=r" (_a));						\
-									\
-	_a;								\
-})
-#else
 #define current_text_addr()						\
 ({									\
 	void *_a;							\
 									\
-	__asm__ ("dla\t%0, 1f\n\t"					\
-		"1:"							\
-		: "=r" (_a));						\
+	__asm__ ("bal\t1f\t\t\t# current_text_addr\n"			\
+		"1:\tmove\t%0, $31"					\
+		: "=r" (_a)						\
+		:							\
+		: "$31");						\
 									\
 	_a;								\
 })
-#endif
 
 #if !defined (_LANGUAGE_ASSEMBLY)
 #include <asm/cachectl.h>

Index: serial.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips64/serial.h,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- serial.h	17 Dec 2001 18:35:15 -0000	1.1
+++ serial.h	30 May 2002 20:42:15 -0000	1.2
@@ -9,6 +9,8 @@
 #ifndef _ASM_SERIAL_H
 #define _ASM_SERIAL_H
 
+#include <linux/config.h>
+
 /*
  * This assumes you have a 1.8432 MHz clock for your UART.
  *

Index: spinlock.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips64/spinlock.h,v
retrieving revision 1.4
retrieving revision 1.5
diff -u -d -r1.4 -r1.5
--- spinlock.h	14 Feb 2002 20:38:59 -0000	1.4
+++ spinlock.h	30 May 2002 20:42:15 -0000	1.5
@@ -22,7 +22,7 @@
 #define spin_lock_init(x)	do { (x)->lock = 0; } while(0)
 
 #define spin_is_locked(x)	((x)->lock != 0)
-#define spin_unlock_wait(x)	do { barrier(); } while ((x)->lock);
+#define spin_unlock_wait(x)	do { barrier(); } while ((x)->lock)
 
 /*
  * Simple spin lock operations.  There are two variants, one clears IRQ's