Update of /cvsroot/linux-mips/linux/arch/mips/mm
In directory usw-pr-cvs1:/tmp/cvs-serv7798/arch/mips/mm
Modified Files:
c-r4k.c
Log Message:
Further OSS syncing.
Index: c-r4k.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/mm/c-r4k.c,v
retrieving revision 1.8
retrieving revision 1.9
diff -u -d -r1.8 -r1.9
--- c-r4k.c 21 Apr 2002 06:43:20 -0000 1.8
+++ c-r4k.c 28 May 2002 21:03:31 -0000 1.9
@@ -27,6 +27,7 @@
#include <asm/pgtable.h>
#include <asm/system.h>
#include <asm/mmu_context.h>
+#include <asm/war.h>
/* Primary cache parameters. */
static int icache_size, dcache_size; /* Size in bytes */
@@ -1001,11 +1002,16 @@
static void r4k_flush_page_to_ram_d32_r4600(struct page *page)
{
+#ifdef R4600_V1_HIT_DCACHE_WAR
unsigned long flags;
- __save_and_cli(flags); /* For R4600 v1.7 bug. */
+ __save_and_cli(flags);
+ __asm__ __volatile__("nop;nop;nop;nop");
+#endif
blast_dcache32_page((unsigned long)page_address(page));
+#ifdef R4600_V1_HIT_DCACHE_WAR
__restore_flags(flags);
+#endif
}
static void
@@ -1057,9 +1063,11 @@
if (size >= dcache_size) {
flush_cache_all();
} else {
- /* Workaround for R4600 bug. See comment above. */
+#ifdef R4600_V2_HIT_CACHEOP_WAR
+ /* Workaround for R4600 bug. See comment in <asm/war>. */
__save_and_cli(flags);
*(volatile unsigned long *)KSEG1;
+#endif
a = addr & ~(dc_lsize - 1);
end = (addr + size) & ~(dc_lsize - 1);
@@ -1068,7 +1076,9 @@
if (a == end) break;
a += dc_lsize;
}
+#ifdef R4600_V2_HIT_CACHEOP_WAR
__restore_flags(flags);
+#endif
}
bc_wback_inv(addr, size);
}
@@ -1101,9 +1111,11 @@
if (size >= dcache_size) {
flush_cache_all();
} else {
+#ifdef R4600_V2_HIT_CACHEOP_WAR
/* Workaround for R4600 bug. See comment above. */
__save_and_cli(flags);
*(volatile unsigned long *)KSEG1;
+#endif
a = addr & ~(dc_lsize - 1);
end = (addr + size) & ~(dc_lsize - 1);
@@ -1112,7 +1124,9 @@
if (a == end) break;
a += dc_lsize;
}
+#ifdef R4600_V2_HIT_CACHEOP_WAR
__restore_flags(flags);
+#endif
}
bc_inv(addr, size);
@@ -1152,24 +1166,36 @@
*/
static void r4k_flush_cache_sigtramp(unsigned long addr)
{
- __asm__ __volatile__("nop;nop;nop;nop"); /* R4600 V1.7 */
+#ifdef R4600_V1_HIT_DCACHE_WAR
+ unsigned long flags;
+
+ __save_and_cli(flags);
+ __asm__ __volatile__("nop;nop;nop;nop");
+#endif
protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
protected_flush_icache_line(addr & ~(ic_lsize - 1));
+#ifdef R4600_V1_HIT_DCACHE_WAR
+ __restore_flags(flags);
+#endif
}
static void r4600v20k_flush_cache_sigtramp(unsigned long addr)
{
unsigned int flags;
+#ifdef R4600_V2_HIT_CACHEOP_WAR
__save_and_cli(flags);
/* Clear internal cache refill buffer */
*(volatile unsigned int *)KSEG1;
+#endif
protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
protected_flush_icache_line(addr & ~(ic_lsize - 1));
+#ifdef R4600_V2_HIT_CACHEOP_WAR
__restore_flags(flags);
+#endif
}
/* Detect and size the various r4k caches. */
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