Update of /cvsroot/linux-mips/linux/include/asm-mips
In directory usw-pr-cvs1:/tmp/cvs-serv2346
Modified Files:
io.h
Log Message:
Provide additinal caching modes for ioremap. Don't use unless you KNOW what you're doing.
Index: io.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/io.h,v
retrieving revision 1.18
retrieving revision 1.19
diff -u -d -r1.18 -r1.19
--- io.h 7 Mar 2002 09:15:17 -0000 1.18
+++ io.h 18 Mar 2002 22:53:34 -0000 1.19
@@ -144,6 +144,16 @@
return __ioremap(offset, size, _CACHE_UNCACHED);
}
+static inline void *ioremap_cacheable_cow(phys_t offset, unsigned long size)
+{
+ return __ioremap(offset, size, _CACHE_CACHABLE_COW);
+}
+
+static inline void *ioremap_uncached_accelerated(phys_t offset, unsigned long size)
+{
+ return __ioremap(offset, size, _CACHE_UNCACHED_ACCELERATED);
+}
+
extern void iounmap(void *addr);
/*
@@ -309,39 +319,6 @@
}
}
-#ifdef CONFIG_CASIO_E15
-#define __OUTS1(s) \
-extern inline void __outs##s(unsigned int port, const void * addr, unsigned long count) {
-
-#define __OUTS2(m) \
-if (count) \
-__asm__ __volatile__ ( \
- ".set\tnoreorder\n\t" \
- ".set\tnoat\n" \
- "1:\tl" #m "\t$1,(%0)\n\t" \
- "subu\t%1,1\n\t" \
- "s" #m "\t$1,%4(%5)\n\t" \
- "bne\t$0,%1,1b\n\t" \
- "addiu\t%0,%6\n\t" \
- ".set\tat\n\t" \
- ".set\treorder"
-
-#define __OUTS(m,s,i) \
-__OUTS1(s) __OUTS2(m) \
- : "=r" (addr), "=r" (count) \
- : "0" (addr), "1" (count), "i" (0), "r" (mips_io_port_base+port), "I" (i) \
- : "$1");} \
-__OUTS1(s##c) __OUTS2(m) \
- : "=r" (addr), "=r" (count) \
- : "0" (addr), "1" (count), "ir" (port), "r" (mips_io_port_base), "I" (i) \
- : "$1");}
-
-__OUTS(h,w,2)
-
-#define outsw(port,addr,count) \
- __outsw ((port),(addr),(count))
-
-#else
static inline void outsw(unsigned long port, void *addr, unsigned int count)
{
while (count--) {
@@ -349,41 +326,7 @@
addr += 2;
}
}
-#endif
-
-#ifdef CONFIG_CASIO_E15
-#define __INS1(s) \
-extern inline void __ins##s(unsigned int port, void * addr, unsigned long count) {
-#define __INS2(m) \
-if (count) \
-__asm__ __volatile__ ( \
- ".set\tnoreorder\n\t" \
- ".set\tnoat\n" \
- "1:\tl" #m "\t$1,%4(%5)\n\t" \
- "subu\t%1,1\n\t" \
- "s" #m "\t$1,(%0)\n\t" \
- "bne\t$0,%1,1b\n\t" \
- "addiu\t%0,%6\n\t" \
- ".set\tat\n\t" \
- ".set\treorder"
-
-#define __INS(m,s,i) \
-__INS1(s) __INS2(m) \
- : "=r" (addr), "=r" (count) \
- : "0" (addr), "1" (count), "i" (0), "r" (mips_io_port_base+port), "I" (i) \
- : "$1");} \
-__INS1(s##c) __INS2(m) \
- : "=r" (addr), "=r" (count) \
- : "0" (addr), "1" (count), "ir" (port), "r" (mips_io_port_base), "I" (i) \
- : "$1");}
-
-__INS(h,w,2)
-
-#define insw(port,addr,count) \
- __insw((port),(addr),(count))
-
-#else
static inline void insw(unsigned long port, void *addr, unsigned int count)
{
while (count--) {
@@ -391,7 +334,6 @@
addr += 2;
}
}
-#endif
static inline void outsl(unsigned long port, void *addr, unsigned int count)
{
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