Update of /cvsroot/linux-mips/linux/include/asm-mips
In directory usw-pr-cvs1:/tmp/cvs-serv14866/asm-mips
Modified Files:
cpu.h mipsregs.h
Log Message:
Implement {get,set}_errorepc() to access the c0_errorepc register.
Index: cpu.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/cpu.h,v
retrieving revision 1.21
retrieving revision 1.22
diff -u -d -r1.21 -r1.22
--- cpu.h 19 Jan 2002 21:17:35 -0000 1.21
+++ cpu.h 26 Feb 2002 17:08:29 -0000 1.22
@@ -137,7 +137,7 @@
CPU_R5000A, CPU_R4640, CPU_NEVADA, CPU_RM7000, CPU_R5432, CPU_4KC,
CPU_5KC, CPU_R4310, CPU_SB1, CPU_TX3912, CPU_TX3922, CPU_TX3927,
CPU_AU1000, CPU_4KEC, CPU_4KSC, CPU_VR41XX, CPU_R5500, CPU_TX49XX,
- CPU_TX39XX, CPU_R5900, CPU_AU1500, CPU_RC32300, CPU_SR7100, CPU_LAST
+ CPU_TX39XX, CPU_AU1500, CPU_R5900, CPU_RC32300, CPU_SR7100, CPU_LAST
};
#endif
Index: mipsregs.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/mipsregs.h,v
retrieving revision 1.18
retrieving revision 1.19
diff -u -d -r1.18 -r1.19
--- mipsregs.h 19 Feb 2002 17:25:24 -0000 1.18
+++ mipsregs.h 26 Feb 2002 17:08:29 -0000 1.19
@@ -900,6 +900,30 @@
: : "Jr" (val));
}
+static inline unsigned long get_errorepc(void)
+{
+ unsigned long val;
+
+ __asm__ __volatile__(
+ ".set push\n\t"
+ ".set reorder\n\t"
+ "mfc0 %0, $30\n\t"
+ ".set pop"
+ : "=r" (val));
+
+ return val;
+}
+
+static inline void set_errorepc(unsigned long val)
+{
+ __asm__ __volatile__(
+ ".set push\n\t"
+ ".set reorder\n\t"
+ "mtc0 %z0, $30\n\t"
+ ".set pop"
+ : : "Jr" (val));
+}
+
/*
* Manipulate the status register.
* Mostly used to access the interrupt bits.
|
