Update of /cvsroot/linux-mips/linux/drivers/sound
In directory usw-pr-cvs1:/tmp/cvs-serv26596
Modified Files:
hal2.c hal2.h
Log Message:
HAL2 driver FIFO fixes.
Index: hal2.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/drivers/sound/hal2.c,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- hal2.c 14 Feb 2002 20:36:20 -0000 1.3
+++ hal2.c 19 Feb 2002 17:19:38 -0000 1.4
@@ -413,10 +413,10 @@
sample_size = 2 * hal2->adc.voices;
- highwater = (sample_size * 2) >> 1; /* halfwords */
- fifobeg = (4 * 4) >> 3; /* record is second */
- fifoend = (sample_size * 4) >> 3; /* doublewords */
- pbus->ctrl = HPC3_PDMACTRL_RT | HPC3_PDMACTRL_RCV | HPC3_PDMACTRL_LD |
+ highwater = (sample_size * 2) >> 1; /* halfwords */
+ fifobeg = (4 * 4) >> 3; /* record is second */
+ fifoend = (4 * 4 + sample_size * 4) >> 3; /* doublewords */
+ pbus->ctrl = HPC3_PDMACTRL_RT | HPC3_PDMACTRL_RCV | HPC3_PDMACTRL_LD |
(highwater << 8) | (fifobeg << 16) | (fifoend << 24);
pbus->pbus->pbdma_ctrl = HPC3_PDMACTRL_LD;
hal2_i_clearbit16(hal2, H2I_DMA_PORT_EN, H2I_DMA_PORT_EN_CODECR);
@@ -427,7 +427,6 @@
hal2_i_write16(hal2, H2I_ADC_C1, (pbus->pbusnr << H2I_C1_DMA_SHIFT)
| (2 << H2I_C1_CLKID_SHIFT)
| (hal2->adc.voices << H2I_C1_DATAT_SHIFT));
-
}
static void hal2_start_dac(hal2_card_t *hal2)
@@ -489,16 +488,18 @@
#define hal2_alloc_adc_dmabuf(hal2) hal2_alloc_dmabuf(hal2, 0)
static int hal2_alloc_dmabuf(hal2_card_t *hal2, int is_dac)
{
- int buffers;
+ int buffers, cntinfo;
hal2_buf_t *buf, *prev;
hal2_codec_t *codec;
if (is_dac) {
codec = &hal2->dac;
buffers = obuffers;
+ cntinfo = HPCDMA_XIE | HPCDMA_EOX;
} else {
codec = &hal2->adc;
buffers = ibuffers;
+ cntinfo = HPCDMA_XIE | H2_BUFFER_SIZE;
}
DEBUG("allocating %d DMA buffers.\n", buffers);
@@ -511,8 +512,7 @@
while (--buffers) {
buf->info.desc.pbuf = PHYSADDR(&buf->data);
- buf->info.desc.cntinfo = HPCDMA_XIE | (is_dac) ?
- HPCDMA_EOX : H2_BUFFER_SIZE;
+ buf->info.desc.cntinfo = cntinfo;
buf->info.cnt = 0;
prev = buf;
buf = (hal2_buf_t*) get_zeroed_page(GFP_KERNEL);
@@ -534,8 +534,7 @@
dma_cache_wback_inv((unsigned long) prev, PAGE_SIZE);
}
buf->info.desc.pbuf = PHYSADDR(&buf->data);
- buf->info.desc.cntinfo = HPCDMA_XIE | (is_dac) ?
- HPCDMA_EOX : H2_BUFFER_SIZE;
+ buf->info.desc.cntinfo = cntinfo;
buf->info.cnt = 0;
buf->info.next = codec->head;
buf->info.desc.pnext = PHYSADDR(codec->head);
Index: hal2.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/drivers/sound/hal2.h,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -d -r1.2 -r1.3
--- hal2.h 14 Feb 2002 20:36:20 -0000 1.2
+++ hal2.h 19 Feb 2002 17:19:38 -0000 1.3
@@ -178,47 +178,25 @@
#define H2I_SYNTH_MAP_C 0x1104 /* synth dma handshake ctrl */
-/* Clock generator 1 CTL 1, 16 bit */
-
-#define H2I_BRES1_C1 0x2104
-#define H2I_BRES1_C1_SHIFT 0 /* 0=48.0 1=44.1 2=aes_rx */
-#define H2I_BRES1_C1_M 0x03
-
-/* Clock generator 1 CTL 2, 32 bit */
-
-#define H2I_BRES1_C2 0x2108
-#define H2I_BRES1_C2_INC_SHIFT 0 /* increment value */
-#define H2I_BRES1_C2_INC_M 0xffff
-#define H2I_BRES1_C2_MOD_SHIFT 16 /* modcontrol value */
-#define H2I_BRES1_C2_MOD_M 0xffff0000 /* modctrl=0xffff&(modinc-1) */
+/* Clock generator CTL 1, 16 bit */
-/* Clock generator 2 CTL 1, 16 bit */
+#define H2I_BRES1_C1 0x2104
+#define H2I_BRES2_C1 0x2204
+#define H2I_BRES3_C1 0x2304
-#define H2I_BRES2_C1 0x2204
-#define H2I_BRES2_C1_SHIFT 0 /* 0=48.0 1=44.1 2=aes_rx */
-#define H2I_BRES2_C1_M 0x03
+#define H2I_BRES_C1_SHIFT 0 /* 0=48.0 1=44.1 2=aes_rx */
+#define H2I_BRES_C1_M 0x03
-/* Clock generator 2 CTL 2, 32 bit */
+/* Clock generator CTL 2, 32 bit */
+#define H2I_BRES1_C2 0x2108
#define H2I_BRES2_C2 0x2208
-#define H2I_BRES2_C2_INC_SHIFT 0 /* increment value */
-#define H2I_BRES2_C2_INC_M 0xffff
-#define H2I_BRES2_C2_MOD_SHIFT 16 /* modcontrol value */
-#define H2I_BRES2_C2_MOD_M 0xffff0000 /* modctrl=0xffff&(modinc-1) */
-
-/* Clock generator 3 CTL 1, 16 bit */
-
-#define H2I_BRES3_C1 0x2304
-#define H2I_BRES3_C1_SHIFT 0 /* 0=48.0 1=44.1 2=aes_rx */
-#define H2I_BRES3_C1_M 0x03
-
-/* Clock generator 3 CTL 2, 32 bit */
-
#define H2I_BRES3_C2 0x2308
-#define H2I_BRES3_C2_INC_SHIFT 0 /* increment value */
-#define H2I_BRES3_C2_INC_M 0xffff
-#define H2I_BRES3_C2_MOD_SHIFT 16 /* modcontrol value */
-#define H2I_BRES3_C2_MOD_M 0xffff0000 /* modctrl=0xffff&(modinc-1) */
+
+#define H2I_BRES_C2_INC_SHIFT 0 /* increment value */
+#define H2I_BRES_C2_INC_M 0xffff
+#define H2I_BRES_C2_MOD_SHIFT 16 /* modcontrol value */
+#define H2I_BRES_C2_MOD_M 0xffff0000 /* modctrl=0xffff&(modinc-1) */
/* Unix timer, 64 bit */
|
