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linux-mips-commits
Update of /cvsroot/linux-mips/linux/arch/mips/au1000/common
In directory usw-pr-cvs1:/tmp/cvs-serv7382/arch/mips/au1000/common
Modified Files:
Makefile clocks.c dbg_io.c dma.c irq.c power.c reset.c
serial.c time.c usbdev.c
Added Files:
rtc.c
Log Message:
* removed runtime copyright prints
* Added Pb1500 support (only pcmcia not working at this time) and
modified all drivers as necessary
* renamed most Au1000 registers to match latest databook
* better Au1000 usb hardware fixes for early silicon
* updated mtd driver to support Pb1500 partitioning
--- NEW FILE: rtc.c ---
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* RTC routines for PC style attached Dallas chip.
*
* Copyright (C) 1998, 2001 by Ralf Baechle
*/
#include <linux/mc146818rtc.h>
#include <asm/io.h>
#define PB1500_RTC_ADDR 0xAC000000
static unsigned char std_rtc_read_data(unsigned long addr)
{
addr <<= 2;
return readb(addr + PB1500_RTC_ADDR);
}
static void std_rtc_write_data(unsigned char data, unsigned long addr)
{
addr <<= 2;
writeb(data, addr + PB1500_RTC_ADDR);
}
static int std_rtc_bcd_mode(void)
{
return 1;
}
struct rtc_ops pb1500_rtc_ops = {
&std_rtc_read_data,
&std_rtc_write_data,
&std_rtc_bcd_mode
};
Index: Makefile
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/au1000/common/Makefile,v
retrieving revision 1.7
retrieving revision 1.8
diff -u -d -r1.7 -r1.8
--- Makefile 6 Nov 2001 00:43:16 -0000 1.7
+++ Makefile 15 Feb 2002 19:47:24 -0000 1.8
@@ -19,12 +19,13 @@
O_TARGET := au1000.o
-export-objs = prom.o serial.o
+export-objs = prom.o serial.o clocks.o
obj-y := prom.o int-handler.o dma.o irq.o puts.o time.o reset.o power.o clocks.o
obj-$(CONFIG_AU1000_UART) += serial.o
obj-$(CONFIG_AU1000_USB_DEVICE) += usbdev.o
obj-$(CONFIG_REMOTE_DEBUG) += dbg_io.o
+obj-$(CONFIG_RTC) += rtc.o
include $(TOPDIR)/Rules.make
Index: clocks.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/au1000/common/clocks.c,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -d -r1.2 -r1.3
--- clocks.c 30 Aug 2001 21:52:39 -0000 1.2
+++ clocks.c 15 Feb 2002 19:47:24 -0000 1.3
@@ -27,6 +27,7 @@
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
+#include <linux/module.h>
#include <asm/au1000.h>
static unsigned int au1000_clock; // Hz
@@ -74,27 +75,24 @@
unsigned int static_cfg0;
unsigned int sys_busclk =
(get_au1000_speed()/1000) /
- ((int)(inl(PM_POWERUP_CONTROL)&0x03) + 2);
+ ((int)(inl(SYS_POWERCTRL)&0x03) + 2);
- static_cfg0 = inl(STATIC_CONFIG_0);
- if (sys_busclk/4 > 40000) {
- static_cfg0 |= (1<<11);
- outl(static_cfg0, STATIC_CONFIG_0);
- lcd_clock = sys_busclk / 5;
- if (lcd_clock > 40000)
+ static_cfg0 = inl(MEM_STCFG0);
+
+ if (static_cfg0 & (1<<11))
+ lcd_clock = sys_busclk / 5; /* note: BCLK switching fails with D5 */
+ else
+ lcd_clock = sys_busclk / 4;
+
+ if (lcd_clock > 50000) /* Epson MAX */
printk(__FUNCTION__
": warning: LCD clock too high (%d KHz)\n",
lcd_clock);
- } else {
- static_cfg0 &= ~(1<<11);
- outl(static_cfg0, STATIC_CONFIG_0);
- lcd_clock = sys_busclk / 4;
- }
- // some time to allow LCD clock to settle
- udelay(100);
}
unsigned int get_au1000_lcd_clock(void)
{
- return lcd_clock;
+ return lcd_clock;
}
+
+EXPORT_SYMBOL(get_au1000_lcd_clock);
Index: dbg_io.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/au1000/common/dbg_io.c,v
retrieving revision 1.4
retrieving revision 1.5
diff -u -d -r1.4 -r1.5
--- dbg_io.c 13 Sep 2001 17:29:36 -0000 1.4
+++ dbg_io.c 15 Feb 2002 19:47:24 -0000 1.5
@@ -53,8 +53,8 @@
#define UART_MOD_CNTRL 0x100 /* Module Control */
/* memory-mapped read/write of the port */
-#define UART16550_READ(y) (inl(DEBUG_BASE + y) & 0xff)
-#define UART16550_WRITE(y,z) (outl(z&0xff, DEBUG_BASE + y))
+#define UART16550_READ(y) (readl(DEBUG_BASE + y) & 0xff)
+#define UART16550_WRITE(y,z) (writel(z&0xff, DEBUG_BASE + y))
extern unsigned long get_au1000_uart_baud_base(void);
extern unsigned long cal_r4koff(void);
Index: dma.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/au1000/common/dma.c,v
retrieving revision 1.5
retrieving revision 1.6
diff -u -d -r1.5 -r1.6
--- dma.c 6 Nov 2001 20:23:53 -0000 1.5
+++ dma.c 15 Feb 2002 19:47:24 -0000 1.6
@@ -32,6 +32,7 @@
#include <linux/kernel.h>
#include <linux/errno.h>
+#include <linux/sched.h>
#include <linux/spinlock.h>
#include <linux/string.h>
#include <linux/delay.h>
@@ -85,12 +86,12 @@
AC97C_DATA, DMA_DR | DMA_DW16 | DMA_NC}, {
UART3_ADDR + UART_TX, DMA_DW8 | DMA_NC}, {
UART3_ADDR + UART_RX, DMA_DR | DMA_DW8 | DMA_NC}, {
- USB_DEV_EP0_READ_FIFO, DMA_DR | DMA_DW8 | DMA_NC}, {
- USB_DEV_EP0_WRITE_FIFO, DMA_DW8 | DMA_NC}, {
- USB_DEV_EP2_WRITE_FIFO, DMA_DW8 | DMA_NC}, {
- USB_DEV_EP3_WRITE_FIFO, DMA_DW8 | DMA_NC}, {
- USB_DEV_EP4_READ_FIFO, DMA_DR | DMA_DW8 | DMA_NC}, {
- USB_DEV_EP5_READ_FIFO, DMA_DR | DMA_DW8 | DMA_NC}, {
+ USBD_EP0RD, DMA_DR | DMA_DW8 | DMA_NC}, {
+ USBD_EP0WR, DMA_DW8 | DMA_NC}, {
+ USBD_EP2WR, DMA_DW8 | DMA_NC}, {
+ USBD_EP3WR, DMA_DW8 | DMA_NC}, {
+ USBD_EP4RD, DMA_DR | DMA_DW8 | DMA_NC}, {
+ USBD_EP5RD, DMA_DR | DMA_DW8 | DMA_NC}, {
I2S_DATA, DMA_DW32 | DMA_NC}, {
I2S_DATA, DMA_DR | DMA_DW32 | DMA_NC}
};
Index: irq.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/au1000/common/irq.c,v
retrieving revision 1.13
retrieving revision 1.14
diff -u -d -r1.13 -r1.14
--- irq.c 2 Jan 2002 18:19:35 -0000 1.13
+++ irq.c 15 Feb 2002 19:47:24 -0000 1.14
@@ -89,6 +89,7 @@
inline void local_disable_irq(unsigned int irq_nr);
extern unsigned int do_IRQ(int irq, struct pt_regs *regs);
+extern void __init init_generic_irq(void);
#ifdef CONFIG_PM
extern void counter0_irq(int irq, void *dev_id, struct pt_regs *regs);
@@ -102,86 +103,86 @@
if (irq_nr > AU1000_LAST_INTC0_INT) {
switch (type) {
case INTC_INT_RISE_EDGE: /* 0:0:1 */
- outl(1<<(irq_nr-32),INTC1_CONFIG2_CLEAR);
- outl(1<<(irq_nr-32), INTC1_CONFIG1_CLEAR);
- outl(1<<(irq_nr-32), INTC1_CONFIG0_SET);
+ outl(1<<(irq_nr-32), IC1_CFG2CLR);
+ outl(1<<(irq_nr-32), IC1_CFG1CLR);
+ outl(1<<(irq_nr-32), IC1_CFG0SET);
break;
case INTC_INT_FALL_EDGE: /* 0:1:0 */
- outl(1<<(irq_nr-32), INTC1_CONFIG2_CLEAR);
- outl(1<<(irq_nr-32), INTC1_CONFIG1_SET);
- outl(1<<(irq_nr-32), INTC1_CONFIG0_CLEAR);
+ outl(1<<(irq_nr-32), IC1_CFG2CLR);
+ outl(1<<(irq_nr-32), IC1_CFG1SET);
+ outl(1<<(irq_nr-32), IC1_CFG0CLR);
break;
case INTC_INT_HIGH_LEVEL: /* 1:0:1 */
- outl(1<<(irq_nr-32), INTC1_CONFIG2_SET);
- outl(1<<(irq_nr-32), INTC1_CONFIG1_CLEAR);
- outl(1<<(irq_nr-32), INTC1_CONFIG0_SET);
+ outl(1<<(irq_nr-32), IC1_CFG2SET);
+ outl(1<<(irq_nr-32), IC1_CFG1CLR);
+ outl(1<<(irq_nr-32), IC1_CFG0SET);
break;
case INTC_INT_LOW_LEVEL: /* 1:1:0 */
- outl(1<<(irq_nr-32), INTC1_CONFIG2_SET);
- outl(1<<(irq_nr-32), INTC1_CONFIG1_SET);
- outl(1<<(irq_nr-32), INTC1_CONFIG0_CLEAR);
+ outl(1<<(irq_nr-32), IC1_CFG2SET);
+ outl(1<<(irq_nr-32), IC1_CFG1SET);
+ outl(1<<(irq_nr-32), IC1_CFG0CLR);
break;
case INTC_INT_DISABLED: /* 0:0:0 */
- outl(1<<(irq_nr-32), INTC1_CONFIG0_CLEAR);
- outl(1<<(irq_nr-32), INTC1_CONFIG1_CLEAR);
- outl(1<<(irq_nr-32), INTC1_CONFIG2_CLEAR);
+ outl(1<<(irq_nr-32), IC1_CFG0CLR);
+ outl(1<<(irq_nr-32), IC1_CFG1CLR);
+ outl(1<<(irq_nr-32), IC1_CFG2CLR);
break;
default: /* disable the interrupt */
printk("unexpected int type %d (irq %d)\n", type, irq_nr);
- outl(1<<(irq_nr-32), INTC1_CONFIG0_CLEAR);
- outl(1<<(irq_nr-32), INTC1_CONFIG1_CLEAR);
- outl(1<<(irq_nr-32), INTC1_CONFIG2_CLEAR);
+ outl(1<<(irq_nr-32), IC1_CFG0CLR);
+ outl(1<<(irq_nr-32), IC1_CFG1CLR);
+ outl(1<<(irq_nr-32), IC1_CFG2CLR);
return;
}
if (int_req) /* assign to interrupt request 1 */
- outl(1<<(irq_nr-32), INTC1_ASSIGN_REQ_CLEAR);
+ outl(1<<(irq_nr-32), IC1_ASSIGNCLR);
else /* assign to interrupt request 0 */
- outl(1<<(irq_nr-32), INTC1_ASSIGN_REQ_SET);
- outl(1<<(irq_nr-32), INTC1_SOURCE_SET);
- outl(1<<(irq_nr-32), INTC1_MASK_CLEAR);
- outl(1<<(irq_nr-32), INTC1_WAKEUP_CLEAR);
+ outl(1<<(irq_nr-32), IC1_ASSIGNSET);
+ outl(1<<(irq_nr-32), IC1_SRCSET);
+ outl(1<<(irq_nr-32), IC1_MASKCLR);
+ outl(1<<(irq_nr-32), IC1_WAKECLR);
}
else {
switch (type) {
case INTC_INT_RISE_EDGE: /* 0:0:1 */
- outl(1<<irq_nr,INTC0_CONFIG2_CLEAR);
- outl(1<<irq_nr, INTC0_CONFIG1_CLEAR);
- outl(1<<irq_nr, INTC0_CONFIG0_SET);
+ outl(1<<irq_nr, IC0_CFG2CLR);
+ outl(1<<irq_nr, IC0_CFG1CLR);
+ outl(1<<irq_nr, IC0_CFG0SET);
break;
case INTC_INT_FALL_EDGE: /* 0:1:0 */
- outl(1<<irq_nr, INTC0_CONFIG2_CLEAR);
- outl(1<<irq_nr, INTC0_CONFIG1_SET);
- outl(1<<irq_nr, INTC0_CONFIG0_CLEAR);
+ outl(1<<irq_nr, IC0_CFG2CLR);
+ outl(1<<irq_nr, IC0_CFG1SET);
+ outl(1<<irq_nr, IC0_CFG0CLR);
break;
case INTC_INT_HIGH_LEVEL: /* 1:0:1 */
- outl(1<<irq_nr, INTC0_CONFIG2_SET);
- outl(1<<irq_nr, INTC0_CONFIG1_CLEAR);
- outl(1<<irq_nr, INTC0_CONFIG0_SET);
+ outl(1<<irq_nr, IC0_CFG2SET);
+ outl(1<<irq_nr, IC0_CFG1CLR);
+ outl(1<<irq_nr, IC0_CFG0SET);
break;
case INTC_INT_LOW_LEVEL: /* 1:1:0 */
- outl(1<<irq_nr, INTC0_CONFIG2_SET);
- outl(1<<irq_nr, INTC0_CONFIG1_SET);
- outl(1<<irq_nr, INTC0_CONFIG0_CLEAR);
+ outl(1<<irq_nr, IC0_CFG2SET);
+ outl(1<<irq_nr, IC0_CFG1SET);
+ outl(1<<irq_nr, IC0_CFG0CLR);
break;
case INTC_INT_DISABLED: /* 0:0:0 */
- outl(1<<irq_nr, INTC0_CONFIG0_CLEAR);
- outl(1<<irq_nr, INTC0_CONFIG1_CLEAR);
- outl(1<<irq_nr, INTC0_CONFIG2_CLEAR);
+ outl(1<<irq_nr, IC0_CFG0CLR);
+ outl(1<<irq_nr, IC0_CFG1CLR);
+ outl(1<<irq_nr, IC0_CFG2CLR);
break;
default: /* disable the interrupt */
printk("unexpected int type %d (irq %d)\n", type, irq_nr);
- outl(1<<irq_nr, INTC0_CONFIG0_CLEAR);
- outl(1<<irq_nr, INTC0_CONFIG1_CLEAR);
- outl(1<<irq_nr, INTC0_CONFIG2_CLEAR);
+ outl(1<<irq_nr, IC0_CFG0CLR);
+ outl(1<<irq_nr, IC0_CFG1CLR);
+ outl(1<<irq_nr, IC0_CFG2CLR);
return;
}
if (int_req) /* assign to interrupt request 1 */
- outl(1<<irq_nr, INTC0_ASSIGN_REQ_CLEAR);
+ outl(1<<irq_nr, IC0_ASSIGNCLR);
else /* assign to interrupt request 0 */
- outl(1<<irq_nr, INTC0_ASSIGN_REQ_SET);
- outl(1<<irq_nr, INTC0_SOURCE_SET);
- outl(1<<irq_nr, INTC0_MASK_CLEAR);
- outl(1<<irq_nr, INTC0_WAKEUP_CLEAR);
+ outl(1<<irq_nr, IC0_ASSIGNSET);
+ outl(1<<irq_nr, IC0_SRCSET);
+ outl(1<<irq_nr, IC0_MASKCLR);
+ outl(1<<irq_nr, IC0_WAKECLR);
}
au_sync();
}
@@ -204,12 +205,12 @@
inline void local_enable_irq(unsigned int irq_nr)
{
if (irq_nr > AU1000_LAST_INTC0_INT) {
- outl(1<<(irq_nr-32), INTC1_MASK_SET);
- outl(1<<(irq_nr-32), INTC1_WAKEUP_SET);
+ outl(1<<(irq_nr-32), IC1_MASKSET);
+ outl(1<<(irq_nr-32), IC1_WAKESET);
}
else {
- outl(1<<irq_nr, INTC0_MASK_SET);
- outl(1<<irq_nr, INTC0_WAKEUP_SET);
+ outl(1<<irq_nr, IC0_MASKSET);
+ outl(1<<irq_nr, IC0_WAKESET);
}
au_sync();
}
@@ -218,12 +219,12 @@
inline void local_disable_irq(unsigned int irq_nr)
{
if (irq_nr > AU1000_LAST_INTC0_INT) {
- outl(1<<(irq_nr-32), INTC1_MASK_CLEAR);
- outl(1<<(irq_nr-32), INTC1_WAKEUP_CLEAR);
+ outl(1<<(irq_nr-32), IC1_MASKCLR);
+ outl(1<<(irq_nr-32), IC1_WAKECLR);
}
else {
- outl(1<<irq_nr, INTC0_MASK_CLEAR);
- outl(1<<irq_nr, INTC0_WAKEUP_CLEAR);
+ outl(1<<irq_nr, IC0_MASKCLR);
+ outl(1<<irq_nr, IC0_WAKECLR);
}
au_sync();
}
@@ -232,12 +233,12 @@
static inline void mask_and_ack_rise_edge_irq(unsigned int irq_nr)
{
if (irq_nr > AU1000_LAST_INTC0_INT) {
- outl(1<<(irq_nr-32), INTC1_R_EDGE_DETECT_CLEAR);
- outl(1<<(irq_nr-32), INTC1_MASK_CLEAR);
+ outl(1<<(irq_nr-32), IC1_RISINGCLR);
+ outl(1<<(irq_nr-32), IC1_MASKCLR);
}
else {
- outl(1<<irq_nr, INTC0_R_EDGE_DETECT_CLEAR);
- outl(1<<irq_nr, INTC0_MASK_CLEAR);
+ outl(1<<irq_nr, IC0_RISINGCLR);
+ outl(1<<irq_nr, IC0_MASKCLR);
}
au_sync();
}
@@ -246,12 +247,12 @@
static inline void mask_and_ack_fall_edge_irq(unsigned int irq_nr)
{
if (irq_nr > AU1000_LAST_INTC0_INT) {
- outl(1<<(irq_nr-32), INTC1_F_EDGE_DETECT_CLEAR);
- outl(1<<(irq_nr-32), INTC1_MASK_CLEAR);
+ outl(1<<(irq_nr-32), IC1_FALLINGCLR);
+ outl(1<<(irq_nr-32), IC1_MASKCLR);
}
else {
- outl(1<<irq_nr, INTC0_F_EDGE_DETECT_CLEAR);
- outl(1<<irq_nr, INTC0_MASK_CLEAR);
+ outl(1<<irq_nr, IC0_FALLINGCLR);
+ outl(1<<irq_nr, IC0_MASKCLR);
}
au_sync();
}
@@ -264,7 +265,7 @@
au_sync();
#if defined(CONFIG_MIPS_PB1000)
if (irq_nr == AU1000_GPIO_15) {
- writew(0x8000, AU1000_MDR); /* ack int */
+ writew(0x8000, PB1000_MDR); /* ack int */
au_sync();
}
#endif
@@ -283,7 +284,7 @@
}
#if defined(CONFIG_MIPS_PB1000)
if (irq_nr == AU1000_GPIO_15) {
- writew(0x4000, AU1000_MDR); /* enable int */
+ writew(0x4000, PB1000_MDR); /* enable int */
au_sync();
}
#endif
@@ -296,13 +297,13 @@
save_and_cli(flags);
if (controller) {
- mask = readl(INTC1_MASK_SET);
+ mask = readl(IC1_MASKSET);
for (i=32; i<64; i++) {
local_disable_irq(i);
}
}
else {
- mask = readl(INTC0_MASK_SET);
+ mask = readl(IC0_MASKSET);
for (i=0; i<32; i++) {
local_disable_irq(i);
}
@@ -326,9 +327,9 @@
}
}
if (controller)
- new_mask = readl(INTC1_MASK_SET);
+ new_mask = readl(IC1_MASKSET);
else
- new_mask = readl(INTC0_MASK_SET);
+ new_mask = readl(IC0_MASKSET);
restore_flags(flags);
}
@@ -372,7 +373,7 @@
#ifdef CONFIG_PM
void startup_match20_interrupt(void)
{
- local_enable_irq(AU1000_PC0_MATCH2_INT);
+ local_enable_irq(AU1000_TOY_MATCH2_INT);
}
#endif
@@ -396,12 +397,14 @@
for (i = 0; i <= AU1000_MAX_INTR; i++) {
switch (i) {
case AU1000_UART0_INT:
+ case AU1000_UART3_INT:
+#ifdef CONFIG_MIPS_PB1000
case AU1000_UART1_INT:
case AU1000_UART2_INT:
- case AU1000_UART3_INT:
case AU1000_SSI0_INT:
case AU1000_SSI1_INT:
+#endif
case AU1000_DMA_INT_BASE:
case AU1000_DMA_INT_BASE+1:
@@ -417,12 +420,27 @@
case AU1000_MAC0_DMA_INT:
case AU1000_MAC1_DMA_INT:
+
+ case AU1500_GPIO_204:
setup_local_irq(i, INTC_INT_HIGH_LEVEL, 0);
irq_desc[i].handler = &level_irq_type;
break;
+#ifdef CONFIG_MIPS_PB1000
case AU1000_GPIO_15:
+#endif
case AU1000_USB_HOST_INT:
+#ifdef CONFIG_MIPS_PB1500
+ case AU1000_PCI_INTA:
+ case AU1000_PCI_INTB:
+ case AU1000_PCI_INTC:
+ case AU1000_PCI_INTD:
+ case AU1500_GPIO_201:
+ case AU1500_GPIO_202:
+ case AU1500_GPIO_203:
+ case AU1500_GPIO_205:
+ case AU1500_GPIO_207:
+#endif
setup_local_irq(i, INTC_INT_LOW_LEVEL, 0);
irq_desc[i].handler = &level_irq_type;
break;
@@ -430,13 +448,13 @@
case AU1000_AC97C_INT:
case AU1000_USB_DEV_REQ_INT:
case AU1000_USB_DEV_SUS_INT:
- case AU1000_PC0_INT:
- case AU1000_PC0_MATCH0_INT:
- case AU1000_PC0_MATCH1_INT:
- case AU1000_PC1_INT:
- case AU1000_PC1_MATCH0_INT:
- case AU1000_PC1_MATCH1_INT:
- case AU1000_PC1_MATCH2_INT:
+ case AU1000_TOY_INT:
+ case AU1000_TOY_MATCH0_INT:
+ case AU1000_TOY_MATCH1_INT:
+ case AU1000_RTC_INT:
+ case AU1000_RTC_MATCH0_INT:
+ case AU1000_RTC_MATCH1_INT:
+ case AU1000_RTC_MATCH2_INT:
setup_local_irq(i, INTC_INT_RISE_EDGE, 0);
irq_desc[i].handler = &rise_edge_irq_type;
break;
@@ -444,7 +462,7 @@
// Careful if you change match 2 request!
// The interrupt handler is called directly
// from the low level dispatch code.
- case AU1000_PC0_MATCH2_INT:
+ case AU1000_TOY_MATCH2_INT:
setup_local_irq(i, INTC_INT_RISE_EDGE, 1);
irq_desc[i].handler = &rise_edge_irq_type;
break;
@@ -476,7 +494,7 @@
int irq = 0, i;
static unsigned long intc0_req0 = 0;
- intc0_req0 |= inl(INTC0_REQ0_INT);
+ intc0_req0 |= inl(IC0_REQ0INT);
if (!intc0_req0) return;
@@ -496,7 +514,7 @@
int irq = 0, i;
static unsigned long intc0_req1 = 0;
- intc0_req1 = inl(INTC0_REQ1_INT);
+ intc0_req1 = inl(IC0_REQ1INT);
if (!intc0_req1) return;
@@ -504,7 +522,7 @@
if ((intc0_req1 & (1<<i))) {
intc0_req1 &= ~(1<<i);
#ifdef CONFIG_PM
- if (i == AU1000_PC0_MATCH2_INT) {
+ if (i == AU1000_TOY_MATCH2_INT) {
mask_and_ack_rise_edge_irq(irq);
counter0_irq(irq, NULL, regs);
local_enable_irq(irq);
@@ -532,7 +550,7 @@
volatile unsigned short levels, mdr;
unsigned char ide_status;
- intc1_req0 |= inl(INTC1_REQ0_INT);
+ intc1_req0 |= inl(IC1_REQ0INT);
if (!intc1_req0) return;
@@ -564,7 +582,7 @@
int irq = 0, i;
static unsigned long intc1_req1 = 0;
- intc1_req1 |= inl(INTC1_REQ1_INT);
+ intc1_req1 |= inl(IC1_REQ1INT);
if (!intc1_req1) return;
Index: power.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/au1000/common/power.c,v
retrieving revision 1.4
retrieving revision 1.5
diff -u -d -r1.4 -r1.5
--- power.c 2 Dec 2001 19:05:29 -0000 1.4
+++ power.c 15 Feb 2002 19:47:24 -0000 1.5
@@ -60,6 +60,11 @@
extern void restore_local_and_enable(int controller, unsigned long mask);
extern void local_enable_irq(unsigned int irq_nr);
+/* Quick acpi hack. This will have to change! */
+#define CTL_ACPI 9999
+#define ACPI_S1_SLP_TYP 19
+#define ACPI_SLEEP 21
+
#ifdef CONFIG_PM
unsigned long suspend_mode;
@@ -76,16 +81,16 @@
flush_cache_all();
/* pin 6 is gpio */
- writel(readl(PIN_STATE) & ~(1 << 11), PIN_STATE);
+ writel(readl(SYS_PINSTATERD) & ~(1 << 11), SYS_PINSTATERD);
/* gpio 6 can cause a wake up event */
- wakeup = readl(PM_WAKEUP_SOURCE_MASK);
+ wakeup = readl(SYS_WAKEMSK);
wakeup &= ~(1 << 8); /* turn off match20 wakeup */
wakeup |= 1 << 6; /* turn on gpio 6 wakeup */
- writel(wakeup, PM_WAKEUP_SOURCE_MASK);
+ writel(wakeup, SYS_WAKEMSK);
- writel(1, PM_WAKEUP_CAUSE); /* clear cause */
- writel(1, PM_SLEEP_POWER); /* prepare to sleep */
+ writel(1, SYS_WAKESRC); /* clear cause */
+ writel(1, SYS_SLPPWR); /* prepare to sleep */
__asm__("la $4, 1f\n\t"
"lui $5, 0xb190\n\t"
@@ -189,14 +194,14 @@
set_au1000_speed(new_cpu_freq);
set_au1000_uart_baud_base(new_baud_base);
- old_refresh = readl(REFRESH_CONFIG) & 0x1ffffff;
+ old_refresh = readl(MEM_SDREFCFG) & 0x1ffffff;
new_refresh =
((old_refresh * new_cpu_freq) /
- old_cpu_freq) | (readl(REFRESH_CONFIG) & ~0x1ffffff);
+ old_cpu_freq) | (readl(MEM_SDREFCFG) & ~0x1ffffff);
- writel(pll, CPU_PLL_CNTRL);
+ writel(pll, SYS_CPUPLL);
au_sync_delay(1);
- writel(new_refresh, REFRESH_CONFIG);
+ writel(new_refresh, MEM_SDREFCFG);
au_sync_delay(1);
for (i = 0; i < 4; i++) {
@@ -241,7 +246,7 @@
*/
intc0_mask = save_local_and_disable(0);
intc1_mask = save_local_and_disable(1);
- local_enable_irq(AU1000_PC0_MATCH2_INT);
+ local_enable_irq(AU1000_TOY_MATCH2_INT);
restore_flags(flags);
calibrate_delay();
restore_local_and_enable(0, intc0_mask);
Index: reset.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/au1000/common/reset.c,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -d -r1.2 -r1.3
--- reset.c 28 Aug 2001 07:23:54 -0000 1.2
+++ reset.c 15 Feb 2002 19:47:24 -0000 1.3
@@ -40,6 +40,52 @@
void au1000_restart(char *command)
{
+ /* Set all integrated peripherals to disabled states */
+ u32 prid = read_32bit_cp0_register(CP0_PRID);
+
+ printk(KERN_NOTICE "\n** Resetting Integrated Peripherals\n");
+ switch (prid & 0xFF000000)
+ {
+ case 0x00000000: /* Au1000 */
+ outl(0x02, 0xb0000010); /* ac97_enable */
+ outl(0x08, 0xb017fffc); /* usbh_enable - early errata */
+ asm("sync");
+ outl(0x00, 0xb017fffc); /* usbh_enable */
+ outl(0x00, 0xb0200058); /* usbd_enable */
+ outl(0x00, 0xb0300040); /* ir_enable */
+ outl(0x00, 0xb0520000); /* macen0 */
+ outl(0x00, 0xb0520004); /* macen1 */
+ outl(0x00, 0xb1000008); /* i2s_enable */
+ outl(0x00, 0xb1100100); /* uart0_enable */
+ outl(0x00, 0xb1200100); /* uart1_enable */
+ outl(0x00, 0xb1300100); /* uart2_enable */
+ outl(0x00, 0xb1400100); /* uart3_enable */
+ outl(0x02, 0xb1600100); /* ssi0_enable */
+ outl(0x02, 0xb1680100); /* ssi1_enable */
+ outl(0x00, 0xb1900020); /* sys_freqctrl0 */
+ outl(0x00, 0xb1900024); /* sys_freqctrl1 */
+ outl(0x00, 0xb1900028); /* sys_clksrc */
+ outl(0x00, 0xb1900100); /* sys_pininputen */
+ break;
+ case 0x01000000: /* Au1500 */
+ outl(0x02, 0xb0000010); /* ac97_enable */
+ outl(0x08, 0xb017fffc); /* usbh_enable - early errata */
+ asm("sync");
+ outl(0x00, 0xb017fffc); /* usbh_enable */
+ outl(0x00, 0xb0200058); /* usbd_enable */
+ outl(0x00, 0xb1520000); /* macen0 */
+ outl(0x00, 0xb1520004); /* macen1 */
+ outl(0x00, 0xb1100100); /* uart0_enable */
+ outl(0x00, 0xb1400100); /* uart3_enable */
+ outl(0x00, 0xb1900020); /* sys_freqctrl0 */
+ outl(0x00, 0xb1900024); /* sys_freqctrl1 */
+ outl(0x00, 0xb1900028); /* sys_clksrc */
+ outl(0x00, 0xb1900100); /* sys_pininputen */
+
+ default:
+ break;
+ }
+
set_cp0_status((ST0_BEV | ST0_ERL));
set_cp0_config(CONF_CM_UNCACHED);
flush_cache_all();
Index: serial.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/au1000/common/serial.c,v
retrieving revision 1.6
retrieving revision 1.7
diff -u -d -r1.6 -r1.7
--- serial.c 2 Dec 2001 19:05:29 -0000 1.6
+++ serial.c 15 Feb 2002 19:47:24 -0000 1.7
@@ -987,8 +987,10 @@
set_bit(TTY_IO_ERROR, &info->tty->flags);
info->flags &= ~ASYNC_INITIALIZED;
+#ifndef CONFIG_REMOTE_DEBUG
outl(0, UART_MOD_CNTRL + state->port);
au_sync_delay(10);
+#endif
restore_flags(flags);
}
@@ -2547,9 +2549,10 @@
(void)serial_in(info, UART_RX);
serial_outp(info, UART_IER, 0);
+#ifndef CONFIG_REMOTE_DEBUG
outl(0, UART_MOD_CNTRL + state->port);
au_sync_delay(10);
-
+#endif
restore_flags(flags);
}
Index: time.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/au1000/common/time.c,v
retrieving revision 1.9
retrieving revision 1.10
diff -u -d -r1.9 -r1.10
--- time.c 15 Oct 2001 22:57:28 -0000 1.9
+++ time.c 15 Feb 2002 19:47:24 -0000 1.10
@@ -36,6 +36,8 @@
#include <asm/mipsregs.h>
#include <asm/ptrace.h>
+#include <asm/time.h>
+#include <asm/hardirq.h>
#include <asm/div64.h>
#include <asm/au1000.h>
@@ -50,6 +52,7 @@
static unsigned long r4k_offset; /* Amount to increment compare reg each time */
static unsigned long r4k_cur; /* What counter should be at next timer irq */
extern rwlock_t xtime_lock;
+unsigned int mips_counter_frequency = 0;
/* Cycle counter value at the previous timer interrupt.. */
static unsigned int timerhi = 0, timerlo = 0;
@@ -75,6 +78,10 @@
{
int irq = 63;
unsigned long count;
+ int cpu = smp_processor_id();
+
+ irq_enter(cpu, irq);
+ kstat.irqs[cpu][irq]++;
#ifdef CONFIG_PM
printk(KERN_ERR "Unexpected CP0 interrupt\n");
@@ -98,6 +105,10 @@
} while (((unsigned long)read_32bit_cp0_register(CP0_COUNT)
- r4k_cur) < 0x7fffffff);
+ irq_exit(cpu, irq);
+
+ if (softirq_pending(cpu))
+ do_softirq();
return;
null:
@@ -112,13 +123,13 @@
static int jiffie_drift = 0;
kstat.irqs[0][irq]++;
- if (readl(PC_COUNTER_CNTRL) & PC_CNTRL_M20) {
+ if (readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20) {
/* should never happen! */
printk(KERN_WARNING "counter 0 w status eror\n");
return;
}
- pc0 = inl(PC0_COUNTER_READ);
+ pc0 = inl(SYS_TOYREAD);
if (pc0 < last_match20) {
/* counter overflowed */
time_elapsed = (0xffffffff - last_match20) + pc0;
@@ -135,7 +146,7 @@
}
last_pc0 = pc0;
- outl(last_match20 + MATCH20_INC, PC0_MATCH2);
+ outl(last_match20 + MATCH20_INC, SYS_TOYMATCH2);
au_sync();
/* our counter ticks at 10.009765625 ms/tick, we we're running
@@ -165,30 +176,31 @@
save_and_cli(flags);
- counter = inl(PC_COUNTER_CNTRL);
- outl(counter | PC_CNTRL_EN1, PC_COUNTER_CNTRL);
+ counter = inl(SYS_COUNTER_CNTRL);
+ outl(counter | SYS_CNTRL_EN1, SYS_COUNTER_CNTRL);
- while (inl(PC_COUNTER_CNTRL) & PC_CNTRL_T1S);
- outl(trim_divide-1, PC1_TRIM); /* RTC now ticks at 32.768/16 kHz */
- while (inl(PC_COUNTER_CNTRL) & PC_CNTRL_T1S);
+ while (inl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T1S);
+ outl(trim_divide-1, SYS_RTCTRIM); /* RTC now ticks at 32.768/16 kHz */
+ while (inl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T1S);
- while (inl(PC_COUNTER_CNTRL) & PC_CNTRL_C1S);
- outl (0, PC1_COUNTER_WRITE);
- while (inl(PC_COUNTER_CNTRL) & PC_CNTRL_C1S);
+ while (inl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S);
+ outl (0, SYS_TOYWRITE);
+ while (inl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S);
- start = inl(PC1_COUNTER_READ);
+ start = inl(SYS_RTCREAD);
start += 2;
/* wait for the beginning of a new tick */
- while (inl(PC1_COUNTER_READ) < start);
+ while (inl(SYS_RTCREAD) < start);
/* Start r4k counter. */
write_32bit_cp0_register(CP0_COUNT, 0);
end = start + (32768 / trim_divide)/2; /* wait 0.5 seconds */
- while (end > inl(PC1_COUNTER_READ));
+ while (end > inl(SYS_RTCREAD));
count = read_32bit_cp0_register(CP0_COUNT);
cpu_speed = count * 2;
+ mips_counter_frequency = count;
set_au1000_uart_baud_base(((cpu_speed) / 4) / 16);
restore_flags(flags);
return (cpu_speed / HZ);
@@ -210,9 +222,7 @@
printk("CPU frequency %d.%02d MHz\n", est_freq/1000000,
(est_freq%1000000)*100/1000000);
set_au1000_speed(est_freq);
-#ifdef CONFIG_FB_E1356
set_au1000_lcd_clock(); // program the LCD clock
-#endif
r4k_cur = (read_32bit_cp0_register(CP0_COUNT) + r4k_offset);
write_32bit_cp0_register(CP0_COMPARE, r4k_cur);
@@ -231,20 +241,20 @@
* counter 0 interrupt as a special irq and it doesn't show
* up under /proc/interrupts.
*/
- while (readl(PC_COUNTER_CNTRL) & PC_CNTRL_C0S);
- writel(0, PC0_COUNTER_WRITE);
- while (readl(PC_COUNTER_CNTRL) & PC_CNTRL_C0S);
+ while (readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C0S);
+ writel(0, SYS_TOYWRITE);
+ while (readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C0S);
- writel(readl(PM_WAKEUP_SOURCE_MASK) | (1<<8), PM_WAKEUP_SOURCE_MASK);
- writel(~0, PM_WAKEUP_CAUSE);
+ writel(readl(SYS_WAKEMSK) | (1<<8), SYS_WAKEMSK);
+ writel(~0, SYS_WAKESRC);
au_sync();
- while (readl(PC_COUNTER_CNTRL) & PC_CNTRL_M20);
+ while (readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20);
/* setup match20 to interrupt once every 10ms */
- last_pc0 = last_match20 = readl(PC0_COUNTER_READ);
- writel(last_match20 + MATCH20_INC, PC0_MATCH2);
+ last_pc0 = last_match20 = readl(SYS_TOYREAD);
+ writel(last_match20 + MATCH20_INC, SYS_TOYMATCH2);
au_sync();
- while (readl(PC_COUNTER_CNTRL) & PC_CNTRL_M20);
+ while (readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20);
startup_match20_interrupt();
#endif
@@ -254,7 +264,7 @@
/* This is for machines which generate the exact clock. */
#define USECS_PER_JIFFY (1000000/HZ)
-#define USECS_PER_JIFFY_FRAC ((u32)((1000000ULL << 32) / HZ))
+#define USECS_PER_JIFFY_FRAC (0x100000000*1000000/HZ&0xffffffff)
static unsigned long
@@ -272,7 +282,7 @@
unsigned long pc0;
unsigned long offset;
- pc0 = readl(PC0_COUNTER_READ);
+ pc0 = readl(SYS_TOYREAD);
if (pc0 < last_pc0) {
offset = 0xffffffff - last_pc0 + pc0;
printk("offset over: %x\n", (unsigned)offset);
@@ -325,8 +335,7 @@
"mfhi\t%0"
:"=r" (res)
:"r" (count),
- "r" (quotient)
- :"$1");
+ "r" (quotient));
/*
* Due to possible jiffies inconsistencies, we need to check
Index: usbdev.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/au1000/common/usbdev.c,v
retrieving revision 1.7
retrieving revision 1.8
diff -u -d -r1.7 -r1.8
--- usbdev.c 16 Jan 2002 23:54:18 -0000 1.7
+++ usbdev.c 15 Feb 2002 19:47:24 -0000 1.8
@@ -279,20 +279,15 @@
static endpoint_reg_t ep_reg[] = {
// FIFO's 0 and 1 are EP0 default control
- {USB_DEV_EP0_READ_FIFO, USB_DEV_EP0_WRITE_FIFO,
- USB_DEV_EP0_CS, USB_DEV_FIFO0_STATUS, USB_DEV_FIFO1_STATUS},
+ {USBD_EP0RD, USBD_EP0WR, USBD_EP0CS, USBD_EP0RDSTAT, USBD_EP0WRSTAT},
// FIFO 2 is EP2, Port 0, bulk IN
- { -1, USB_DEV_EP2_WRITE_FIFO, USB_DEV_EP2_CS,
- -1, USB_DEV_FIFO2_STATUS },
+ { -1, USBD_EP2WR, USBD_EP2CS, -1, USBD_EP2WRSTAT },
// FIFO 4 is EP4, Port 0, bulk OUT
- {USB_DEV_EP4_READ_FIFO, -1, USB_DEV_EP4_CS,
- USB_DEV_FIFO4_STATUS, -1},
+ {USBD_EP4RD, -1, USBD_EP4CS, USBD_EP3WR, -1},
// FIFO 3 is EP3, Port 1, bulk IN
- { -1, USB_DEV_EP3_WRITE_FIFO, USB_DEV_EP3_CS,
- -1, USB_DEV_FIFO3_STATUS },
+ { -1, USBD_EP3WRSTAT, USBD_EP3CS, -1, USBD_EP3WRSTAT },
// FIFO 5 is EP5, Port 1, bulk OUT
- {USB_DEV_EP5_READ_FIFO, -1, USB_DEV_EP5_CS,
- USB_DEV_FIFO5_STATUS, -1}
+ {USBD_EP5RD, -1, USBD_EP5CS, USBD_EP5RDSTAT, -1}
};
static struct {
|
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