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linux-mips-commits
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From: Steve L. <slo...@us...> - 2002-01-24 20:13:36
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Update of /cvsroot/linux-mips/linux/arch/mips/rc32300/79S334
In directory usw-pr-cvs1:/tmp/cvs-serv9288/rc32300/79S334
Modified Files:
irq.c pci_fixup.c pci_ops.c setup.c
Log Message:
H/W PCI byte-swapping on the RC32334 does not work - disable and
use s/w swapping instead (CONFIG_SWAP_IO_SPACE).
Index: irq.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/rc32300/79S334/irq.c,v
retrieving revision 1.7
retrieving revision 1.8
diff -u -d -r1.7 -r1.8
--- irq.c 2002/01/19 01:35:17 1.7
+++ irq.c 2002/01/24 20:13:34 1.8
@@ -105,12 +105,18 @@
{ GROUP14_IRQ_BASE, 1, 0x00000001 } // SPI intr
};
-#define READ_PEND(g) inl(IC_GROUP0_PEND + (g)*IC_GROUP_OFFSET)
-#define WRITE_PEND(g,val) outl((val), IC_GROUP0_PEND + (g)*IC_GROUP_OFFSET)
-#define READ_MASK(g) inl(IC_GROUP0_MASK + (g)*IC_GROUP_OFFSET)
-#define WRITE_MASK(g,val) outl((val), IC_GROUP0_MASK + (g)*IC_GROUP_OFFSET)
-#define READ_CLEAR(g) inl(IC_GROUP0_CLEAR + (g)*IC_GROUP_OFFSET)
-#define WRITE_CLEAR(g,val) outl((val), IC_GROUP0_CLEAR + (g)*IC_GROUP_OFFSET)
+#define READ_PEND(g) \
+ rc32300_inl(IC_GROUP0_PEND + (g)*IC_GROUP_OFFSET)
+#define WRITE_PEND(g,val) \
+ rc32300_outl((val), IC_GROUP0_PEND + (g)*IC_GROUP_OFFSET)
+#define READ_MASK(g) \
+ rc32300_inl(IC_GROUP0_MASK + (g)*IC_GROUP_OFFSET)
+#define WRITE_MASK(g,val) \
+ rc32300_outl((val), IC_GROUP0_MASK + (g)*IC_GROUP_OFFSET)
+#define READ_CLEAR(g) \
+ rc32300_inl(IC_GROUP0_CLEAR + (g)*IC_GROUP_OFFSET)
+#define WRITE_CLEAR(g,val) \
+ rc32300_outl((val), IC_GROUP0_CLEAR + (g)*IC_GROUP_OFFSET)
static inline int irq_to_group(unsigned int irq_nr)
{
@@ -381,7 +387,9 @@
return; // no interrupts in this group ???
intr = 31 - rc32300_clz(pend);
+#ifdef DEBUG_IRQ
idtprintf("%02d%02d", group, intr);
+#endif
do_IRQ(g->irq_base + intr, regs);
}
Index: pci_fixup.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/rc32300/79S334/pci_fixup.c,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- pci_fixup.c 2002/01/17 21:07:24 1.3
+++ pci_fixup.c 2002/01/24 20:13:34 1.4
@@ -53,7 +53,7 @@
/*
* Enable CPU and IP Bus Error exceptions, and disable WatchDog.
*/
- outl(0x18, CPU_IP_BUSERR_CNTL);
+ rc32300_outl(0x18, CPU_IP_BUSERR_CNTL);
}
void __init pcibios_fixup_irqs(void)
Index: pci_ops.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/rc32300/79S334/pci_ops.c,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- pci_ops.c 2002/01/17 21:07:24 1.3
+++ pci_ops.c 2002/01/24 20:13:34 1.4
@@ -50,9 +50,9 @@
#endif
#ifdef __MIPSEB__
-#define SWAP_ENDIAN_BIT 1
+#define SWAP_BIT 1
#else
-#define SWAP_ENDIAN_BIT 0
+#define SWAP_BIT 0
#endif
extern struct resource rc32334_res_pci_io;
@@ -60,8 +60,11 @@
extern struct resource rc32334_res_pci_mem2;
extern struct resource rc32334_res_pci_mem3;
+extern char * __init prom_getcmdline(void);
+
#define PCI_CFG_SET(slot,func,off) \
- outl((0x80000000 | ((slot)<<11) | ((func)<<8) | (off)), PCI_CFG_CNTL)
+ rc32300_outl((0x80000000 | ((slot)<<11) | ((func)<<8) | (off)), \
+ PCI_CFG_CNTL)
static int
config_access(u8 type, u8 bus, u8 devfn, u8 where, u32 *data)
@@ -82,9 +85,9 @@
rc32300_sync();
if (type == PCI_ACCESS_WRITE)
- outl(*data, PCI_CFG_DATA);
+ rc32300_outl(*data, PCI_CFG_DATA);
else
- *data = inl(PCI_CFG_DATA);
+ *data = rc32300_inl(PCI_CFG_DATA);
rc32300_sync();
/*
@@ -236,13 +239,13 @@
u32 val;
printk("RC32334 PCI Bridge Config:\n");
- printk("PCI_MEM1_BASE: 0x%08x\n", inl(PCI_MEM1_BASE));
- printk("PCI_MEM2_BASE: 0x%08x\n", inl(PCI_MEM2_BASE));
- printk("PCI_MEM3_BASE: 0x%08x\n", inl(PCI_MEM3_BASE));
- printk("PCI_IO1_BASE: 0x%08x\n", inl(PCI_IO1_BASE));
- printk("PCI_ARBITRATION:0x%08x\n", inl(PCI_ARBITRATION));
- printk("PCI_CPU_MEM1_BASE:0x%08x\n", inl(PCI_CPU_MEM1_BASE));
- printk("PCI_CPU_IO_BASE:0x%08x\n", inl(PCI_CPU_IO_BASE));
+ printk("PCI_MEM1_BASE: 0x%08x\n", rc32300_inl(PCI_MEM1_BASE));
+ printk("PCI_MEM2_BASE: 0x%08x\n", rc32300_inl(PCI_MEM2_BASE));
+ printk("PCI_MEM3_BASE: 0x%08x\n", rc32300_inl(PCI_MEM3_BASE));
+ printk("PCI_IO1_BASE: 0x%08x\n", rc32300_inl(PCI_IO1_BASE));
+ printk("PCI_ARBITRATION:0x%08x\n", rc32300_inl(PCI_ARBITRATION));
+ printk("PCI_CPU_MEM1_BASE:0x%08x\n", rc32300_inl(PCI_CPU_MEM1_BASE));
+ printk("PCI_CPU_IO_BASE:0x%08x\n", rc32300_inl(PCI_CPU_IO_BASE));
for (i=0; i<17; i++) {
config_read(0, 0, i*4, &val);
@@ -252,8 +255,10 @@
void __init rc32334_pcibridge_init(void)
{
+ char *argptr;
+
/* allow writes to bridge config space */
- outl(4, PCI_ARBITRATION);
+ rc32300_outl(4, PCI_ARBITRATION);
config_write(0, 0, PCI_VENDOR_ID,
PCI_VENDOR_ID_IDT | (PCI_DEVICE_ID_IDT_RC32334 << 16));
@@ -283,24 +288,56 @@
/* retry timeout, trdy timeout */
config_write(0, 0, PCI_INTERRUPT_LINE+4, 0x00008080);
- outl(0x00000000, PCI_CFG_CNTL);
+ rc32300_outl(0x00000000, PCI_CFG_CNTL);
/*
* CPU -> PCI address translation. Make CPU physical and
* PCI bus addresses the same.
*/
+ /*
+ * Note!
+ *
+ * Contrary to the RC32334 documentation, the behavior of
+ * the PCI byte-swapping bits appears to be the following:
+ *
+ * when cpu is in LE: 0 = don't swap, 1 = swap
+ * when cpu is in BE: 1 = don't swap, 0 = swap
+ *
+ * This is true both when the cpu/DMA accesses PCI device
+ * memory/io, and when a PCI bus master accesses system memory.
+ *
+ * Furthermore, byte-swapping doesn't even seem to work
+ * correctly when it is enabled.
+ *
+ * The solution to all this is to disable h/w byte-swapping,
+ * use s/w swapping (CONFIG_SWAP_IO_SPACE) for the in/out/read/
+ * write macros (which takes care of device accesses by cpu/dma)
+ * and hope that drivers swap device data in memory (which takes
+ * care of memory accesses by bus-masters).
+ *
+ * Finally, despite the above workaround, there are still
+ * PCI h/w problems on the 79S334A. PCI bus timeouts and
+ * system/parity errors have been encountered.
+ */
+
/* mem space 1 */
- outl(rc32334_res_pci_mem1.start, PCI_MEM1_BASE);
+ rc32300_outl(rc32334_res_pci_mem1.start | SWAP_BIT, PCI_MEM1_BASE);
/* mem space 2 */
- outl(rc32334_res_pci_mem2.start, PCI_MEM2_BASE);
+ rc32300_outl(rc32334_res_pci_mem2.start | SWAP_BIT, PCI_MEM2_BASE);
/* mem space 3 */
- outl(rc32334_res_pci_mem3.start, PCI_MEM3_BASE);
+ rc32300_outl(rc32334_res_pci_mem3.start | SWAP_BIT, PCI_MEM3_BASE);
/* i/o space */
- outl(rc32334_res_pci_io.start, PCI_IO1_BASE);
+ rc32300_outl(rc32334_res_pci_io.start | SWAP_BIT, PCI_IO1_BASE);
- /* use internal arbiter, 0=round robin, 1=fixed arbitration */
- outl(0, PCI_ARBITRATION);
+ argptr = prom_getcmdline();
+ if ((argptr = strstr(argptr, "pciextarb")) == NULL) {
+ /* use internal arbiter, 0=round robin, 1=fixed */
+ rc32300_outl(0, PCI_ARBITRATION);
+ } else {
+ /* use external arbiter */
+ rc32300_outl(2, PCI_ARBITRATION);
+ }
/*
* PCI -> CPU accesses
@@ -308,8 +345,8 @@
* Let PCI see system memory at 0x00000000 physical
*/
- outl(0x0 | SWAP_ENDIAN_BIT, PCI_CPU_MEM1_BASE); /* mem space */
- outl(0x0 | SWAP_ENDIAN_BIT, PCI_CPU_IO_BASE); /* i/o space */
+ rc32300_outl(0x0 | SWAP_BIT, PCI_CPU_MEM1_BASE); /* mem space */
+ rc32300_outl(0x0 | SWAP_BIT, PCI_CPU_IO_BASE); /* i/o space */
rc32300_sync();
}
Index: setup.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/rc32300/79S334/setup.c,v
retrieving revision 1.5
retrieving revision 1.6
diff -u -d -r1.5 -r1.6
--- setup.c 2002/01/19 01:47:29 1.5
+++ setup.c 2002/01/24 20:13:34 1.6
@@ -138,9 +138,9 @@
printk("RC32334 %s bus error:\n", data ? "Data" : "Instruction");
printk(" EPC == %08lx, RA == %08lx\n", regs->cp0_epc, regs->regs[31]);
- printk(" CPU bus address == %08x\n", readl(CPU_BUSERR_ADDR));
- printk(" IP bus address == %08x\n", inl(CPU_IP_BUSERR_ADDR));
- cntl = inl(CPU_IP_BUSERR_CNTL);
+ printk(" CPU bus address == %08x\n", rc32300_readl(CPU_BUSERR_ADDR));
+ printk(" IP bus address == %08x\n", rc32300_inl(CPU_IP_BUSERR_ADDR));
+ cntl = rc32300_inl(CPU_IP_BUSERR_CNTL);
printk(" Bus error occured on a %s on %s bus\n",
cntl & 1 ? "read" : "write",
cntl & 4 ? "CPU" : "IP");
@@ -149,7 +149,7 @@
rc32300_ack_irq(GROUP4_IRQ_BASE+4); // ack timer 4 rollover intr
rc32300_ack_irq(GROUP4_IRQ_BASE+5); // ack timer 5 rollover intr
rc32300_ack_irq(GROUP1_IRQ_BASE); // ack bus error intr
- outl(cntl & ~0x07, CPU_IP_BUSERR_CNTL);
+ rc32300_outl(cntl & ~0x07, CPU_IP_BUSERR_CNTL);
//die_if_kernel("Oops", regs);
force_sig(SIGBUS, current);
@@ -175,24 +175,24 @@
* Disable CPU and IP Bus Error exceptions (PCI scan will
* cause bus timeouts), and disable WatchDog.
*/
- outl(0x98, CPU_IP_BUSERR_CNTL);
+ rc32300_outl(0x98, CPU_IP_BUSERR_CNTL);
- outl(0, TIMER0_CNTL + 4*TIMER_REG_OFFSET);
- outl(0, TIMER0_CNTL + 5*TIMER_REG_OFFSET);
- outl(0x3fff, TIMER0_COMPARE + 4*TIMER_REG_OFFSET);
- outl(0x3fff, TIMER0_COMPARE + 5*TIMER_REG_OFFSET);
- outl(1, TIMER0_CNTL + 4*TIMER_REG_OFFSET);
- outl(1, TIMER0_CNTL + 5*TIMER_REG_OFFSET);
+ rc32300_outl(0, TIMER0_CNTL + 4*TIMER_REG_OFFSET);
+ rc32300_outl(0, TIMER0_CNTL + 5*TIMER_REG_OFFSET);
+ rc32300_outl(0x3fff, TIMER0_COMPARE + 4*TIMER_REG_OFFSET);
+ rc32300_outl(0x3fff, TIMER0_COMPARE + 5*TIMER_REG_OFFSET);
+ rc32300_outl(1, TIMER0_CNTL + 4*TIMER_REG_OFFSET);
+ rc32300_outl(1, TIMER0_CNTL + 5*TIMER_REG_OFFSET);
#if 0
printk(__FUNCTION__ ": Timer4 Cntl = 0x%08x\n",
- inl(TIMER0_CNTL + 4*TIMER_REG_OFFSET));
+ rc32300_inl(TIMER0_CNTL + 4*TIMER_REG_OFFSET));
printk(__FUNCTION__ ": Timer4 Cmp = 0x%08x\n",
- inl(TIMER0_COMPARE + 4*TIMER_REG_OFFSET));
+ rc32300_inl(TIMER0_COMPARE + 4*TIMER_REG_OFFSET));
printk(__FUNCTION__ ": Timer5 Cntl = 0x%08x\n",
- inl(TIMER0_CNTL + 5*TIMER_REG_OFFSET));
+ rc32300_inl(TIMER0_CNTL + 5*TIMER_REG_OFFSET));
printk(__FUNCTION__ ": Timer5 Cmp = 0x%08x\n",
- inl(TIMER0_COMPARE + 5*TIMER_REG_OFFSET));
+ rc32300_inl(TIMER0_COMPARE + 5*TIMER_REG_OFFSET));
request_irq(GROUP4_IRQ_BASE+4, bus_error_interrupt, SA_INTERRUPT,
"RC32334 CPU Bus Error", NULL);
@@ -230,6 +230,8 @@
// clear out any wired entries
write_32bit_cp0_register(CP0_WIRED, 0);
+ inb(LCD_CLEAR); // clear the 4-digit LCD display
+
#ifdef CONFIG_BLK_DEV_INITRD
ROOT_DEV = MKDEV(RAMDISK_MAJOR, 0);
initrd_start = (unsigned long)&__rd_start;
@@ -238,43 +240,43 @@
#if 0
printk(__FUNCTION__ ": CPU_PORT_WIDTH = 0x%08x\n",
- readl(CPU_PORT_WIDTH));
+ rc32300_readl(CPU_PORT_WIDTH));
printk(__FUNCTION__ ": CPU_BTA = 0x%08x\n",
- readl(CPU_BTA));
+ rc32300_readl(CPU_BTA));
printk(__FUNCTION__ ": CPU_BUSERR_ADDR = 0x%08x\n",
- readl(CPU_BUSERR_ADDR));
+ rc32300_readl(CPU_BUSERR_ADDR));
printk(__FUNCTION__ ": CPU_IP_BTA = 0x%08x\n",
- inl(CPU_IP_BTA));
+ rc32300_inl(CPU_IP_BTA));
printk(__FUNCTION__ ": CPU_IP_ADDR_LATCH = 0x%08x\n",
- inl(CPU_IP_ADDR_LATCH));
+ rc32300_inl(CPU_IP_ADDR_LATCH));
printk(__FUNCTION__ ": CPU_IP_ARBITRATION = 0x%08x\n",
- inl(CPU_IP_ARBITRATION));
+ rc32300_inl(CPU_IP_ARBITRATION));
printk(__FUNCTION__ ": CPU_IP_BUSERR_CNTL = 0x%08x\n",
- inl(CPU_IP_BUSERR_CNTL));
+ rc32300_inl(CPU_IP_BUSERR_CNTL));
printk(__FUNCTION__ ": CPU_IP_BUSERR_ADDR = 0x%08x\n",
- inl(CPU_IP_BUSERR_ADDR));
+ rc32300_inl(CPU_IP_BUSERR_ADDR));
printk(__FUNCTION__ ": CPU_IP_SYSID = 0x%08x\n",
- inl(CPU_IP_SYSID));
+ rc32300_inl(CPU_IP_SYSID));
printk(__FUNCTION__ ": MEM_BASE_BANK0 = 0x%08x\n",
- inl(MEM_BASE_BANK0));
+ rc32300_inl(MEM_BASE_BANK0));
printk(__FUNCTION__ ": MEM_MASK_BANK0 = 0x%08x\n",
- inl(MEM_MASK_BANK0));
+ rc32300_inl(MEM_MASK_BANK0));
printk(__FUNCTION__ ": MEM_CNTL_BANK0 = 0x%08x\n",
- inl(MEM_CNTL_BANK0));
+ rc32300_inl(MEM_CNTL_BANK0));
printk(__FUNCTION__ ": MEM_BASE_BANK1 = 0x%08x\n",
- inl(MEM_BASE_BANK1));
+ rc32300_inl(MEM_BASE_BANK1));
printk(__FUNCTION__ ": MEM_MASK_BANK1 = 0x%08x\n",
- inl(MEM_MASK_BANK1));
+ rc32300_inl(MEM_MASK_BANK1));
printk(__FUNCTION__ ": MEM_CNTL_BANK1 = 0x%08x\n",
- inl(MEM_CNTL_BANK1));
+ rc32300_inl(MEM_CNTL_BANK1));
printk(__FUNCTION__ ": MEM_CNTL_BANK2 = 0x%08x\n",
- inl(MEM_CNTL_BANK2));
+ rc32300_inl(MEM_CNTL_BANK2));
printk(__FUNCTION__ ": MEM_CNTL_BANK3 = 0x%08x\n",
- inl(MEM_CNTL_BANK3));
+ rc32300_inl(MEM_CNTL_BANK3));
printk(__FUNCTION__ ": MEM_CNTL_BANK4 = 0x%08x\n",
- inl(MEM_CNTL_BANK4));
+ rc32300_inl(MEM_CNTL_BANK4));
printk(__FUNCTION__ ": MEM_CNTL_BANK5 = 0x%08x\n",
- inl(MEM_CNTL_BANK5));
+ rc32300_inl(MEM_CNTL_BANK5));
#endif
#ifdef CONFIG_PCI
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