Update of /cvsroot/linux-mips/linux/include/asm-mips
In directory usw-pr-cvs1:/tmp/cvs-serv15987
Modified Files:
mmu_context.h
Log Message:
Flush virtually tagged i-caches on ASID overflow.
Index: mmu_context.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/mmu_context.h,v
retrieving revision 1.7
retrieving revision 1.8
diff -u -d -r1.7 -r1.8
--- mmu_context.h 2001/11/19 17:57:38 1.7
+++ mmu_context.h 2001/11/26 18:50:19 1.8
@@ -14,6 +14,7 @@
#include <linux/config.h>
#include <linux/slab.h>
#include <asm/pgalloc.h>
+#include <asm/pgtable.h>
/*
* For the fast tlb miss handlers, we currently keep a per cpu array
@@ -66,6 +67,7 @@
unsigned long asid = ASID_CACHE(cpu);
if (! ((asid += ASID_INC) & ASID_MASK) ) {
+ flush_icache_all();
local_flush_tlb_all(); /* start new asid cycle */
if (!asid) /* fix version if needed */
asid = ASID_FIRST_VERSION;
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