Update of /cvsroot/linux-mips/linux/arch/mips/kernel
In directory usw-pr-cvs1:/tmp/cvs-serv15292
Modified Files:
setup.c
Log Message:
Add a kernel option to disable the FPU in the kernel. Useful for debugging the full FPU emulator on fpu-full systems.
Index: setup.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/kernel/setup.c,v
retrieving revision 1.31
retrieving revision 1.32
diff -u -d -r1.31 -r1.32
--- setup.c 2001/11/22 01:19:24 1.31
+++ setup.c 2001/11/26 18:48:14 1.32
@@ -7,7 +7,7 @@
* Copyright (C) 1995 Waldorf Electronics
* Copyright (C) 1995, 1996, 1997, 1998, 1999, 2000, 2001 Ralf Baechle
* Copyright (C) 1996 Stoned Elipot
- * Copyright (C) 2000 Maciej W. Rozycki
+ * Copyright (C) 2000, 2001 Maciej W. Rozycki
*/
#include <linux/config.h>
#include <linux/errno.h>
@@ -17,6 +17,7 @@
#include <linux/sched.h>
#include <linux/kernel.h>
#include <linux/mm.h>
+#include <linux/module.h>
#include <linux/stddef.h>
#include <linux/string.h>
#include <linux/unistd.h>
@@ -105,13 +106,14 @@
* mips_io_port_base is the begin of the address space to which x86 style
* I/O ports are mapped.
*/
-unsigned long mips_io_port_base;
+unsigned long mips_io_port_base; EXPORT_SYMBOL(mips_io_port_base);
+
/*
* isa_slot_offset is the address where E(ISA) busaddress 0 is is mapped
* for the processor.
*/
-unsigned long isa_slot_offset;
+unsigned long isa_slot_offset; EXPORT_SYMBOL(isa_slot_offset);
extern void sgi_sysinit(void);
extern void SetUpBootInfo(void);
@@ -182,6 +184,28 @@
#endif
}
+/*
+ * Get the FPU Implementation/Revision.
+ */
+static inline unsigned long cpu_get_fpu_id(void)
+{
+ unsigned long tmp, fpu_id;
+
+ tmp = read_32bit_cp0_register(CP0_STATUS);
+ write_32bit_cp0_register(CP0_STATUS, tmp | ST0_CU1);
+ fpu_id = read_32bit_cp1_register(CP1_REVISION);
+ write_32bit_cp0_register(CP0_STATUS, tmp);
+ return fpu_id;
+}
+
+/*
+ * Check the CPU has an FPU the official way.
+ */
+static inline int cpu_has_fpu(void)
+{
+ return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE);
+}
+
/* declaration of the global struct */
struct mips_cpu mips_cpu = {PRID_IMP_UNKNOWN, CPU_UNKNOWN, 0, 0, 0,
{0,0,0,0}, {0,0,0,0}, {0,0,0,0}, {0,0,0,0}};
@@ -206,6 +230,8 @@
mips_cpu.cputype = CPU_R2000;
mips_cpu.isa_level = MIPS_CPU_ISA_I;
mips_cpu.options = MIPS_CPU_TLB;
+ if (cpu_has_fpu())
+ mips_cpu.options |= MIPS_CPU_FPU;
mips_cpu.tlbsize = 64;
break;
case PRID_IMP_R3000:
@@ -218,6 +244,8 @@
mips_cpu.cputype = CPU_R3000;
mips_cpu.isa_level = MIPS_CPU_ISA_I;
mips_cpu.options = MIPS_CPU_TLB;
+ if (cpu_has_fpu())
+ mips_cpu.options |= MIPS_CPU_FPU;
mips_cpu.tlbsize = 64;
break;
case PRID_IMP_R4000:
@@ -344,7 +372,7 @@
mips_cpu.cputype = CPU_NEVADA;
mips_cpu.isa_level = MIPS_CPU_ISA_IV;
mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU |
- MIPS_CPU_32FPR | MIPS_CPU_DIVEC;
+ MIPS_CPU_32FPR | MIPS_CPU_DIVEC;
mips_cpu.tlbsize = 48;
mips_cpu.icache.ways = 2;
mips_cpu.dcache.ways = 2;
@@ -630,7 +658,7 @@
void atlas_setup(void);
void baget_setup(void);
void ddb_setup(void);
- void cobalt_setup(void);
+ void cobalt_setup(void);
void decstation_setup(void);
void deskstation_setup(void);
void jazz_setup(void);
@@ -647,12 +675,14 @@
void ps2_setup(void);
void clio_1000_setup(void);
void jmr3927_setup(void);
- void it8172_setup(void);
+ void it8172_setup(void);
+ void swarm_setup(void);
+ void hp_setup(void);
unsigned long bootmap_size;
unsigned long start_pfn, max_pfn, first_usable_pfn;
#ifdef CONFIG_BLK_DEV_INITRD
- unsigned long *initrd_header;
+ unsigned long* initrd_header;
unsigned long tmp;
#endif
int i;
@@ -797,7 +827,7 @@
#endif
#ifdef CONFIG_HP_LASERJET
case MACH_GROUP_HP_LASERJET:
- { void hp_setup(void); hp_setup(); }
+ hp_setup();
break;
#endif
default:
@@ -985,3 +1015,10 @@
"wait\n\t"
".set\tmips0");
}
+
+int __init fpu_disable(char *s)
+{
+ mips_cpu.options &= ~MIPS_CPU_FPU;
+ return 1;
+}
+__setup("nofpu", fpu_disable);
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