Update of /cvsroot/linux-mips/linux/arch/mips64/mm
In directory usw-pr-cvs1:/tmp/cvs-serv17597/mm
Modified Files:
init.c loadmmu.c r4xx0.c
Log Message:
Synced mips64 stuff to OSS tree.
Index: init.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips64/mm/init.c,v
retrieving revision 1.4
retrieving revision 1.5
diff -u -d -r1.4 -r1.5
--- init.c 2001/11/20 17:57:32 1.4
+++ init.c 2001/11/26 17:17:26 1.5
@@ -34,6 +34,7 @@
#include <asm/pgalloc.h>
#include <asm/mmu_context.h>
#include <asm/tlb.h>
+#include <asm/cpu.h>
mmu_gather_t mmu_gathers[NR_CPUS];
unsigned long totalram_pages;
@@ -131,7 +132,7 @@
unsigned long order, size;
struct page *page;
- switch (mips_cputype) {
+ switch (mips_cpu.cputype) {
case CPU_R4000SC:
case CPU_R4000MC:
case CPU_R4400SC:
Index: loadmmu.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips64/mm/loadmmu.c,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -d -r1.2 -r1.3
--- loadmmu.c 2001/11/20 17:53:03 1.2
+++ loadmmu.c 2001/11/26 17:17:26 1.3
@@ -17,6 +17,7 @@
#include <asm/pgtable.h>
#include <asm/system.h>
#include <asm/bootinfo.h>
+#include <asm/cpu.h>
/* memory functions */
void (*_clear_page)(void * page);
@@ -52,7 +53,7 @@
void __init load_mmu(void)
{
- switch(mips_cputype) {
+ switch(mips_cpu.cputype) {
#if defined (CONFIG_CPU_R4300) \
|| defined (CONFIG_CPU_R4X00) \
|| defined (CONFIG_CPU_R5000) \
Index: r4xx0.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips64/mm/r4xx0.c,v
retrieving revision 1.9
retrieving revision 1.10
diff -u -d -r1.9 -r1.10
--- r4xx0.c 2001/11/20 17:57:32 1.9
+++ r4xx0.c 2001/11/26 17:17:26 1.10
@@ -21,6 +21,7 @@
#include <asm/system.h>
#include <asm/bootinfo.h>
#include <asm/mmu_context.h>
+#include <asm/cpu.h>
/* CP0 hazard avoidance. */
#define BARRIER __asm__ __volatile__(".set noreorder\n\t" \
@@ -39,6 +40,7 @@
#undef DEBUG_CACHE
+
/*
* Dummy cache handling routines for machines without boardcaches
*/
@@ -2371,7 +2373,7 @@
probe_dcache(config);
setup_scache(config);
- switch(mips_cputype) {
+ switch(mips_cpu.cputype) {
case CPU_R4600: /* QED style two way caches? */
case CPU_R4700:
case CPU_R5000:
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