Update of /cvsroot/linux-mips/linux/include/asm-mips
In directory usw-pr-cvs1:/tmp/cvs-serv1183/asm-mips
Modified Files:
cpu.h
Log Message:
Add MIPS_CPU_MCHECK. Mips64 version is now a copy of the 32-bit version of this file.
Index: cpu.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/cpu.h,v
retrieving revision 1.13
retrieving revision 1.14
diff -u -d -r1.13 -r1.14
--- cpu.h 2001/11/19 17:53:00 1.13
+++ cpu.h 2001/11/20 17:39:15 1.14
@@ -53,8 +53,8 @@
#define PRID_IMP_R4640 0x2200
#define PRID_IMP_R4650 0x2200 /* Same as R4640 */
#define PRID_IMP_R5000 0x2300
-#define PRID_IMP_TX49 0x2d00
#define PRID_IMP_R5900 0x2e00
+#define PRID_IMP_TX49 0x2d00
#define PRID_IMP_SONIC 0x2400
#define PRID_IMP_MAGIC 0x2500
#define PRID_IMP_RM7000 0x2700
@@ -128,17 +128,18 @@
/*
* CPU Option encodings
*/
-#define MIPS_CPU_TLB 0x00000001 /* CPU has TLB */
+#define MIPS_CPU_TLB 0x00000001 /* CPU has TLB */
/* Leave a spare bit for variant MMU types... */
-#define MIPS_CPU_4KEX 0x00000004 /* "R4K" exception model */
-#define MIPS_CPU_4KTLB 0x00000008 /* "R4K" TLB handler */
-#define MIPS_CPU_FPU 0x00000010 /* CPU has FPU */
-#define MIPS_CPU_32FPR 0x00000020 /* 32 dbl. prec. FP registers */
-#define MIPS_CPU_COUNTER 0x00000040 /* Cycle count/compare */
-#define MIPS_CPU_WATCH 0x00000080 /* watchpoint registers */
-#define MIPS_CPU_MIPS16 0x00000100 /* code compression */
-#define MIPS_CPU_DIVEC 0x00000200 /* dedicated interrupt vector */
-#define MIPS_CPU_VCE 0x00000400 /* virt. coherence conflict possible */
+#define MIPS_CPU_4KEX 0x00000004 /* "R4K" exception model */
+#define MIPS_CPU_4KTLB 0x00000008 /* "R4K" TLB handler */
+#define MIPS_CPU_FPU 0x00000010 /* CPU has FPU */
+#define MIPS_CPU_32FPR 0x00000020 /* 32 dbl. prec. FP registers */
+#define MIPS_CPU_COUNTER 0x00000040 /* Cycle count/compare */
+#define MIPS_CPU_WATCH 0x00000080 /* watchpoint registers */
+#define MIPS_CPU_MIPS16 0x00000100 /* code compression */
+#define MIPS_CPU_DIVEC 0x00000200 /* dedicated interrupt vector */
+#define MIPS_CPU_VCE 0x00000400 /* virt. coherence conflict possible */
#define MIPS_CPU_CACHE_CDEX 0x00000800 /* Create_Dirty_Exclusive CACHE op */
+#define MIPS_CPU_MCHECK 0x00001000 /* Machine check exception */
#endif /* _ASM_CPU_H */
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