Update of /cvsroot/linux-mips/linux/arch/mips/kernel
In directory usw-pr-cvs1:/tmp/cvs-serv31722
Modified Files:
setup.c
Log Message:
Fix bunch of cut'n'paste type errors in R4kc, R5kc support. Add support for SWARM board.
Index: setup.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/kernel/setup.c,v
retrieving revision 1.26
retrieving revision 1.27
diff -u -d -r1.26 -r1.27
--- setup.c 2001/10/29 17:42:46 1.26
+++ setup.c 2001/11/08 17:12:25 1.27
@@ -422,7 +422,7 @@
* Why do we set all these options by default, THEN
* query them??
*/
- mips_cpu.cputype = MIPS_CPU_ISA_M32;
+ mips_cpu.isa_level = MIPS_CPU_ISA_M32;
mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
MIPS_CPU_4KTLB | MIPS_CPU_COUNTER |
MIPS_CPU_DIVEC | MIPS_CPU_WATCH;
@@ -437,7 +437,7 @@
break;
case PRID_IMP_5KC:
mips_cpu.cputype = CPU_5KC;
- mips_cpu.cputype = MIPS_CPU_ISA_M64;
+ mips_cpu.isa_level = MIPS_CPU_ISA_M64;
/* See comment above about querying options */
mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
MIPS_CPU_4KTLB | MIPS_CPU_COUNTER |
@@ -484,9 +484,13 @@
switch (mips_cpu.processor_id & 0xff00) {
case PRID_IMP_SB1:
mips_cpu.cputype = CPU_SB1;
- mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
- MIPS_CPU_COUNTER | MIPS_CPU_DIVEC | MIPS_CPU_FPU |
- MIPS_CPU_VCE;
+ mips_cpu.isa_level = MIPS_CPU_ISA_M64;
+ mips_cpu.options = (MIPS_CPU_TLB | MIPS_CPU_4KEX |
+ MIPS_CPU_COUNTER | MIPS_CPU_DIVEC);
+#ifndef CONFIG_SB1_PASS_1_WORKAROUNDS
+ /* FPU in pass1 is known to have issues. */
+ mips_cpu.options |= MIPS_CPU_FPU;
+#endif
break;
default:
mips_cpu.cputype = CPU_UNKNOWN;
@@ -632,6 +636,7 @@
void sgi_setup(void);
void ev96100_setup(void);
void malta_setup(void);
+ void ikos_setup(void);
void momenco_ocelot_setup(void);
void nino_setup(void);
void nec_osprey_setup(void);
@@ -774,6 +779,11 @@
#ifdef CONFIG_PS2
case MACH_GROUP_EE:
ps2_setup();
+ break;
+#endif
+#ifdef CONFIG_SIBYTE_SWARM
+ case MACH_GROUP_SIBYTE:
+ swarm_setup();
break;
#endif
default:
|
