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linux-mips-commits
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From: James S. <jsi...@us...> - 2001-10-31 18:26:55
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Update of /cvsroot/linux-mips/linux/include/asm-mips
In directory usw-pr-cvs1:/tmp/cvs-serv9038/include/asm-mips
Modified Files:
checksum.h io.h mmu_context.h pci.h pgalloc.h processor.h
r4kcache.h softirq.h
Added Files:
bcache.h branch.h jazz.h mips32_cache.h siginfo.h unaligned.h
Log Message:
Replace all incarnations of extern inline with static inline.
--- NEW FILE: branch.h ---
/*
* Branch and jump emulation.
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1996, 1997, 1998, 2001 by Ralf Baechle
*/
#include <asm/ptrace.h>
static inline int delay_slot(struct pt_regs *regs)
{
return regs->cp0_cause & CAUSEF_BD;
}
extern int __compute_return_epc(struct pt_regs *regs);
static inline int compute_return_epc(struct pt_regs *regs)
{
if (!delay_slot(regs)) {
regs->cp0_epc += 4;
return 0;
}
return __compute_return_epc(regs);
}
--- NEW FILE: jazz.h ---
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1995 - 1998 by Andreas Busse and Ralf Baechle
*/
#ifndef __ASM_JAZZ_H
#define __ASM_JAZZ_H
/*
* The addresses below are virtual address. The mappings are
* created on startup via wired entries in the tlb. The Mips
* Magnum R3000 and R4000 machines are similar in many aspects,
* but many hardware register are accessible at 0xb9000000 in
* instead of 0xe0000000.
*/
#define JAZZ_LOCAL_IO_SPACE 0xe0000000
/*
* Revision numbers in PICA_ASIC_REVISION
*
* 0xf0000000 - Rev1
* 0xf0000001 - Rev2
* 0xf0000002 - Rev3
*/
#define PICA_ASIC_REVISION 0xe0000008
/*
* The segments of the seven segment LED are mapped
* to the control bits as follows:
*
* (7)
* ---------
* | |
* (2) | | (6)
* | (1) |
* ---------
* | |
* (3) | | (5)
* | (4) |
* --------- . (0)
*/
#define PICA_LED 0xe000f000
/*
* Some characters for the LED control registers
* The original Mips machines seem to have a LED display
* with integrated decoder while the Acer machines can
* control each of the seven segments and the dot independently.
* It's only a toy, anyway...
*/
#define LED_DOT 0x01
#define LED_SPACE 0x00
#define LED_0 0xfc
#define LED_1 0x60
#define LED_2 0xda
#define LED_3 0xf2
#define LED_4 0x66
#define LED_5 0xb6
#define LED_6 0xbe
#define LED_7 0xe0
#define LED_8 0xfe
#define LED_9 0xf6
#define LED_A 0xee
#define LED_b 0x3e
#define LED_C 0x9c
#define LED_d 0x7a
#define LED_E 0x9e
#define LED_F 0x8e
#ifndef _LANGUAGE_ASSEMBLY
extern __inline__ void pica_set_led(unsigned int bits)
{
volatile unsigned int *led_register = (unsigned int *) PICA_LED;
*led_register = bits;
}
#endif
/*
* Base address of the Sonic Ethernet adapter in Jazz machines.
*/
#define JAZZ_ETHERNET_BASE 0xe0001000
/*
* Base address of the 53C94 SCSI hostadapter in Jazz machines.
*/
#define JAZZ_SCSI_BASE 0xe0002000
/*
* i8042 keyboard controller for JAZZ and PICA chipsets.
* This address is just a guess and seems to differ from
* other mips machines such as RC3xxx...
*/
#define JAZZ_KEYBOARD_ADDRESS 0xe0005000
#define JAZZ_KEYBOARD_DATA 0xe0005000
#define JAZZ_KEYBOARD_COMMAND 0xe0005001
#ifndef _LANGUAGE_ASSEMBLY
typedef struct {
unsigned char data;
unsigned char command;
} jazz_keyboard_hardware;
typedef struct {
unsigned char pad0[3];
unsigned char data;
unsigned char pad1[3];
unsigned char command;
} mips_keyboard_hardware;
/*
* For now. Needs to be changed for RC3xxx support. See below.
*/
#define keyboard_hardware jazz_keyboard_hardware
#endif
/*
* i8042 keyboard controller for most other Mips machines.
*/
#define MIPS_KEYBOARD_ADDRESS 0xb9005000
#define MIPS_KEYBOARD_DATA 0xb9005003
#define MIPS_KEYBOARD_COMMAND 0xb9005007
/*
* Serial and parallel ports (WD 16C552) on the Mips JAZZ
*/
#define JAZZ_SERIAL1_BASE (unsigned int)0xe0006000
#define JAZZ_SERIAL2_BASE (unsigned int)0xe0007000
#define JAZZ_PARALLEL_BASE (unsigned int)0xe0008000
/*
* Dummy Device Address. Used in jazzdma.c
*/
#define JAZZ_DUMMY_DEVICE 0xe000d000
/*
* JAZZ timer registers and interrupt no.
* Note that the hardware timer interrupt is actually on
* cpu level 6, but to keep compatibility with PC stuff
* it is remapped to vector 0. See arch/mips/kernel/entry.S.
*/
#define JAZZ_TIMER_INTERVAL 0xe0000228
#define JAZZ_TIMER_REGISTER 0xe0000230
/*
* DRAM configuration register
*/
#ifndef _LANGUAGE_ASSEMBLY
#ifdef __MIPSEL__
typedef struct {
unsigned int bank2 : 3;
unsigned int bank1 : 3;
unsigned int mem_bus_width : 1;
unsigned int reserved2 : 1;
unsigned int page_mode : 1;
unsigned int reserved1 : 23;
} dram_configuration;
#else /* defined (__MIPSEB__) */
typedef struct {
unsigned int reserved1 : 23;
unsigned int page_mode : 1;
unsigned int reserved2 : 1;
unsigned int mem_bus_width : 1;
unsigned int bank1 : 3;
unsigned int bank2 : 3;
} dram_configuration;
#endif
#endif /* _LANGUAGE_ASSEMBLY */
#define PICA_DRAM_CONFIG 0xe00fffe0
/*
* JAZZ interrupt control registers
*/
#define JAZZ_IO_IRQ_SOURCE 0xe0010000
#define JAZZ_IO_IRQ_ENABLE 0xe0010002
/*
* JAZZ interrupt enable bits
*/
#define JAZZ_IE_PARALLEL (1 << 0)
#define JAZZ_IE_FLOPPY (1 << 1)
#define JAZZ_IE_SOUND (1 << 2)
#define JAZZ_IE_VIDEO (1 << 3)
#define JAZZ_IE_ETHERNET (1 << 4)
#define JAZZ_IE_SCSI (1 << 5)
#define JAZZ_IE_KEYBOARD (1 << 6)
#define JAZZ_IE_MOUSE (1 << 7)
#define JAZZ_IE_SERIAL1 (1 << 8)
#define JAZZ_IE_SERIAL2 (1 << 9)
/*
* JAZZ Interrupt Level definitions
*
* This is somewhat broken. For reasons which nobody can remember anymore
* we remap the Jazz interrupts to the usual ISA style interrupt numbers.
*/
#define JAZZ_PARALLEL_IRQ 16
#define JAZZ_FLOPPY_IRQ 6 /* needs to be consistent with floppy driver! */
#define JAZZ_SOUND_IRQ 18
#define JAZZ_VIDEO_IRQ 19
#define JAZZ_ETHERNET_IRQ 20
#define JAZZ_SCSI_IRQ 21
#define JAZZ_KEYBOARD_IRQ 22
#define JAZZ_MOUSE_IRQ 23
#define JAZZ_SERIAL1_IRQ 24
#define JAZZ_SERIAL2_IRQ 25
#define JAZZ_TIMER_IRQ 31
/*
* JAZZ DMA Channels
* Note: Channels 4...7 are not used with respect to the Acer PICA-61
* chipset which does not provide these DMA channels.
*/
#define JAZZ_SCSI_DMA 0 /* SCSI */
#define JAZZ_FLOPPY_DMA 1 /* FLOPPY */
#define JAZZ_AUDIOL_DMA 2 /* AUDIO L */
#define JAZZ_AUDIOR_DMA 3 /* AUDIO R */
/*
* JAZZ R4030 MCT_ADR chip (DMA controller)
* Note: Virtual Addresses !
*/
#define JAZZ_R4030_CONFIG 0xE0000000 /* R4030 config register */
#define JAZZ_R4030_REVISION 0xE0000008 /* same as PICA_ASIC_REVISION */
#define JAZZ_R4030_INV_ADDR 0xE0000010 /* Invalid Address register */
#define JAZZ_R4030_TRSTBL_BASE 0xE0000018 /* Translation Table Base */
#define JAZZ_R4030_TRSTBL_LIM 0xE0000020 /* Translation Table Limit */
#define JAZZ_R4030_TRSTBL_INV 0xE0000028 /* Translation Table Invalidate */
#define JAZZ_R4030_CACHE_MTNC 0xE0000030 /* Cache Maintenance */
#define JAZZ_R4030_R_FAIL_ADDR 0xE0000038 /* Remote Failed Address */
#define JAZZ_R4030_M_FAIL_ADDR 0xE0000040 /* Memory Failed Address */
#define JAZZ_R4030_CACHE_PTAG 0xE0000048 /* I/O Cache Physical Tag */
#define JAZZ_R4030_CACHE_LTAG 0xE0000050 /* I/O Cache Logical Tag */
#define JAZZ_R4030_CACHE_BMASK 0xE0000058 /* I/O Cache Byte Mask */
#define JAZZ_R4030_CACHE_BWIN 0xE0000060 /* I/O Cache Buffer Window */
/*
* Remote Speed Registers.
*
* 0: free, 1: Ethernet, 2: SCSI, 3: Floppy,
* 4: RTC, 5: Kb./Mouse 6: serial 1, 7: serial 2,
* 8: parallel, 9: NVRAM, 10: CPU, 11: PROM,
* 12: reserved, 13: free, 14: 7seg LED, 15: ???
*/
#define JAZZ_R4030_REM_SPEED 0xE0000070 /* 16 Remote Speed Registers */
/* 0xE0000070,78,80... 0xE00000E8 */
#define JAZZ_R4030_IRQ_ENABLE 0xE00000E8 /* Internal Interrupt Enable */
#define JAZZ_R4030_INVAL_ADDR 0xE0000010 /* Invalid address Register */
#define JAZZ_R4030_IRQ_SOURCE 0xE0000200 /* Interrupt Source Register */
#define JAZZ_R4030_I386_ERROR 0xE0000208 /* i386/EISA Bus Error */
/*
* Virtual (E)ISA controller address
*/
#define JAZZ_EISA_IRQ_ACK 0xE0000238 /* EISA interrupt acknowledge */
/*
* Access the R4030 DMA and I/O Controller
*/
#ifndef _LANGUAGE_ASSEMBLY
static inline void r4030_delay(void)
{
__asm__ __volatile__(
".set\tnoreorder\n\t"
"nop\n\t"
"nop\n\t"
"nop\n\t"
"nop\n\t"
".set\treorder");
}
static inline unsigned short r4030_read_reg16(unsigned addr)
{
unsigned short ret = *((volatile unsigned short *)addr);
r4030_delay();
return ret;
}
static inline unsigned int r4030_read_reg32(unsigned addr)
{
unsigned int ret = *((volatile unsigned int *)addr);
r4030_delay();
return ret;
}
static inline void r4030_write_reg16(unsigned addr, unsigned val)
{
*((volatile unsigned short *)addr) = val;
r4030_delay();
}
static inline void r4030_write_reg32(unsigned addr, unsigned val)
{
*((volatile unsigned int *)addr) = val;
r4030_delay();
}
#endif /* !LANGUAGE_ASSEMBLY__ */
#define JAZZ_FDC_BASE 0xe0003000
#define JAZZ_RTC_BASE 0xe0004000
#define JAZZ_PORT_BASE 0xe2000000
#define JAZZ_EISA_BASE 0xe3000000
#endif /* __ASM_JAZZ_H */
--- NEW FILE: siginfo.h ---
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1998, 1999 by Ralf Baechle
*/
#ifndef _ASM_SIGINFO_H
#define _ASM_SIGINFO_H
#include <linux/types.h>
/* This structure matches IRIX 32/n32 ABIs for binary compatibility. */
typedef union sigval {
int sival_int;
void *sival_ptr;
} sigval_t;
/* This structure matches IRIX 32/n32 ABIs for binary compatibility but
has Linux extensions. */
#define SI_MAX_SIZE 128
#define SI_PAD_SIZE ((SI_MAX_SIZE/sizeof(int)) - 3)
typedef struct siginfo {
int si_signo;
int si_code;
int si_errno;
union {
int _pad[SI_PAD_SIZE];
/* kill() */
struct {
pid_t _pid; /* sender's pid */
uid_t _uid; /* sender's uid */
} _kill;
/* SIGCHLD */
struct {
pid_t _pid; /* which child */
uid_t _uid; /* sender's uid */
clock_t _utime;
int _status; /* exit code */
clock_t _stime;
} _sigchld;
/* IRIX SIGCHLD */
struct {
pid_t _pid; /* which child */
clock_t _utime;
int _status; /* exit code */
clock_t _stime;
} _irix_sigchld;
/* SIGILL, SIGFPE, SIGSEGV, SIGBUS */
struct {
void *_addr; /* faulting insn/memory ref. */
} _sigfault;
/* SIGPOLL, SIGXFSZ (To do ...) */
struct {
int _band; /* POLL_IN, POLL_OUT, POLL_MSG */
int _fd;
} _sigpoll;
/* POSIX.1b timers */
struct {
unsigned int _timer1;
unsigned int _timer2;
} _timer;
/* POSIX.1b signals */
struct {
pid_t _pid; /* sender's pid */
uid_t _uid; /* sender's uid */
sigval_t _sigval;
} _rt;
} _sifields;
} siginfo_t;
/*
* How these fields are to be accessed.
*/
#define si_pid _sifields._kill._pid
#define si_uid _sifields._kill._uid
#define si_status _sifields._sigchld._status
#define si_utime _sifields._sigchld._utime
#define si_stime _sifields._sigchld._stime
#define si_value _sifields._rt._sigval
#define si_int _sifields._rt._sigval.sival_int
#define si_ptr _sifields._rt._sigval.sival_ptr
#define si_addr _sifields._sigfault._addr
#define si_band _sifields._sigpoll._band
#define si_fd _sifields._sigpoll._fd
#ifdef __KERNEL__
#define __SI_MASK 0xffff0000
#define __SI_KILL (0 << 16)
#define __SI_TIMER (1 << 16)
#define __SI_POLL (2 << 16)
#define __SI_FAULT (3 << 16)
#define __SI_CHLD (4 << 16)
#define __SI_RT (5 << 16)
#define __SI_CODE(T,N) ((T) << 16 | ((N) & 0xffff))
#else
#define __SI_KILL 0
#define __SI_TIMER 0
#define __SI_POLL 0
#define __SI_FAULT 0
#define __SI_CHLD 0
#define __SI_RT 0
#define __SI_CODE(T,N) (N)
#endif
/*
* si_code values
* Again these have been choosen to be IRIX compatible.
*/
#define SI_USER 0 /* sent by kill, sigsend, raise */
#define SI_KERNEL 0x80 /* sent by the kernel from somewhere */
#define SI_QUEUE -1 /* sent by sigqueue */
#define SI_ASYNCIO -2 /* sent by AIO completion */
#define SI_TIMER __SI_CODE(__SI_TIMER,-3) /* sent by timer expiration */
#define SI_MESGQ -4 /* sent by real time mesq state change */
#define SI_SIGIO -5 /* sent by queued SIGIO */
#define SI_FROMUSER(siptr) ((siptr)->si_code <= 0)
#define SI_FROMKERNEL(siptr) ((siptr)->si_code > 0)
/*
* SIGILL si_codes
*/
#define ILL_ILLOPC (__SI_FAULT|1) /* illegal opcode */
#define ILL_ILLOPN (__SI_FAULT|2) /* illegal operand */
#define ILL_ILLADR (__SI_FAULT|3) /* illegal addressing mode */
#define ILL_ILLTRP (__SI_FAULT|4) /* illegal trap */
#define ILL_PRVOPC (__SI_FAULT|5) /* privileged opcode */
#define ILL_PRVREG (__SI_FAULT|6) /* privileged register */
#define ILL_COPROC (__SI_FAULT|7) /* coprocessor error */
#define ILL_BADSTK (__SI_FAULT|8) /* internal stack error */
#define NSIGILL 8
/*
* SIGFPE si_codes
*/
#define FPE_INTDIV (__SI_FAULT|1) /* integer divide by zero */
#define FPE_INTOVF (__SI_FAULT|2) /* integer overflow */
#define FPE_FLTDIV (__SI_FAULT|3) /* floating point divide by zero */
#define FPE_FLTOVF (__SI_FAULT|4) /* floating point overflow */
#define FPE_FLTUND (__SI_FAULT|5) /* floating point underflow */
#define FPE_FLTRES (__SI_FAULT|6) /* floating point inexact result */
#define FPE_FLTINV (__SI_FAULT|7) /* floating point invalid operation */
#define FPE_FLTSUB (__SI_FAULT|8) /* subscript out of range */
#define NSIGFPE 8
/*
* SIGSEGV si_codes
*/
#define SEGV_MAPERR (__SI_FAULT|1) /* address not mapped to object */
#define SEGV_ACCERR (__SI_FAULT|2) /* invalid permissions for mapped object */
#define NSIGSEGV 2
/*
* SIGBUS si_codes
*/
#define BUS_ADRALN (__SI_FAULT|1) /* invalid address alignment */
#define BUS_ADRERR (__SI_FAULT|2) /* non-existant physical address */
#define BUS_OBJERR (__SI_FAULT|3) /* object specific hardware error */
#define NSIGBUS 3
/*
* SIGTRAP si_codes
*/
#define TRAP_BRKPT (__SI_FAULT|1) /* process breakpoint */
#define TRAP_TRACE (__SI_FAULT|2) /* process trace trap */
#define NSIGTRAP 2
/*
* SIGCHLD si_codes
*/
#define CLD_EXITED (__SI_CHLD|1) /* child has exited */
#define CLD_KILLED (__SI_CHLD|2) /* child was killed */
#define CLD_DUMPED (__SI_CHLD|3) /* child terminated abnormally */
#define CLD_TRAPPED (__SI_CHLD|4) /* traced child has trapped */
#define CLD_STOPPED (__SI_CHLD|5) /* child has stopped */
#define CLD_CONTINUED (__SI_CHLD|6) /* stopped child has continued */
#define NSIGCHLD 6
/*
* SIGPOLL si_codes
*/
#define POLL_IN (__SI_POLL|1) /* data input available */
#define POLL_OUT (__SI_POLL|2) /* output buffers available */
#define POLL_MSG (__SI_POLL|3) /* input message available */
#define POLL_ERR (__SI_POLL|4) /* i/o error */
#define POLL_PRI (__SI_POLL|5) /* high priority input available */
#define POLL_HUP (__SI_POLL|6) /* device disconnected */
#define NSIGPOLL 6
/*
* sigevent definitions
*
* It seems likely that SIGEV_THREAD will have to be handled from
* userspace, libpthread transmuting it to SIGEV_SIGNAL, which the
* thread manager then catches and does the appropriate nonsense.
* However, everything is written out here so as to not get lost.
*/
#define SIGEV_NONE 128 /* other notification: meaningless */
#define SIGEV_SIGNAL 129 /* notify via signal */
#define SIGEV_CALLBACK 130 /* ??? */
#define SIGEV_THREAD 131 /* deliver via thread creation */
#define SIGEV_MAX_SIZE 64
#define SIGEV_PAD_SIZE ((SIGEV_MAX_SIZE/sizeof(int)) - 4)
/* XXX This one isn't yet IRIX / ABI compatible. */
typedef struct sigevent {
int sigev_notify;
sigval_t sigev_value;
int sigev_signo;
union {
int _pad[SIGEV_PAD_SIZE];
struct {
void (*_function)(sigval_t);
void *_attribute; /* really pthread_attr_t */
} _sigev_thread;
} _sigev_un;
} sigevent_t;
#define sigev_notify_function _sigev_un._sigev_thread._function
#define sigev_notify_attributes _sigev_un._sigev_thread._attribute
#ifdef __KERNEL__
#include <linux/string.h>
static inline void copy_siginfo(siginfo_t *to, siginfo_t *from)
{
if (from->si_code < 0)
memcpy(to, from, sizeof(siginfo_t));
else
/* _sigchld is currently the largest know union member */
memcpy(to, from, 3*sizeof(int) + sizeof(from->_sifields._sigchld));
}
extern int copy_siginfo_to_user(siginfo_t *to, siginfo_t *from);
#endif /* __KERNEL__ */
#endif /* _ASM_SIGINFO_H */
Index: checksum.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/checksum.h,v
retrieving revision 1.4
retrieving revision 1.5
diff -u -d -r1.4 -r1.5
--- checksum.h 2001/10/23 17:14:04 1.4
+++ checksum.h 2001/10/31 18:26:52 1.5
@@ -41,7 +41,7 @@
* Copy and checksum to user
*/
#define HAVE_CSUM_COPY_USER
-extern inline unsigned int csum_and_copy_to_user (const char *src, char *dst,
+static inline unsigned int csum_and_copy_to_user (const char *src, char *dst,
int len, int sum,
int *err_ptr)
{
Index: io.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/io.h,v
retrieving revision 1.6
retrieving revision 1.7
diff -u -d -r1.6 -r1.7
--- io.h 2001/09/25 03:36:35 1.6
+++ io.h 2001/10/31 18:26:52 1.7
@@ -102,12 +102,12 @@
* Change virtual addresses to physical addresses and vv.
* These are trivial on the 1:1 Linux/MIPS mapping
*/
-extern inline unsigned long virt_to_phys(volatile void * address)
+static inline unsigned long virt_to_phys(volatile void * address)
{
return PHYSADDR(address);
}
-extern inline void * phys_to_virt(unsigned long address)
+static inline void * phys_to_virt(unsigned long address)
{
return (void *)KSEG0ADDR(address);
}
@@ -115,12 +115,12 @@
/*
* IO bus memory addresses are also 1:1 with the physical address
*/
-extern inline unsigned long virt_to_bus(volatile void * address)
+static inline unsigned long virt_to_bus(volatile void * address)
{
return PHYSADDR(address);
}
-extern inline void * bus_to_virt(unsigned long address)
+static inline void * bus_to_virt(unsigned long address)
{
return (void *)KSEG0ADDR(address);
}
@@ -140,12 +140,12 @@
extern void * __ioremap(unsigned long offset, unsigned long size, unsigned long flags);
-extern inline void *ioremap(unsigned long offset, unsigned long size)
+static inline void *ioremap(unsigned long offset, unsigned long size)
{
return __ioremap(offset, size, _CACHE_UNCACHED);
}
-extern inline void *ioremap_nocache(unsigned long offset, unsigned long size)
+static inline void *ioremap_nocache(unsigned long offset, unsigned long size)
{
return __ioremap(offset, size, _CACHE_UNCACHED);
}
@@ -227,7 +227,7 @@
*/
#define __OUT1(s) \
-extern inline void __out##s(unsigned int value, unsigned int port) {
+static inline void __out##s(unsigned int value, unsigned int port) {
#define __OUT2(m) \
__asm__ __volatile__ ("s" #m "\t%0,%1(%2)"
@@ -275,7 +275,7 @@
#define __inlc_p(port) __INMAC_P(unsigned int,w,32,port)
#define __INS1(s) \
-extern inline void __ins##s(unsigned int port, void * addr, unsigned long count) {
+static inline void __ins##s(unsigned int port, void * addr, unsigned long count) {
#define __INS2(m,count) \
if (count) \
@@ -295,7 +295,7 @@
: "=r" (addr), "=r" (count) \
: "0" (addr), "1" (count), "i" (0), \
"r" (mips_io_port_base+port), "I" (i) \
- : "$1");}
+ : "$1");} \
#define __INSMAC(m,i,port,addr,count) ({ void *_a = (addr); unsigned long _c = (count); \
__INS2(m,_c) \
@@ -303,12 +303,13 @@
: "0" (_a), "1" (_c), "i#*X" (port), \
"r" (mips_io_port_base), "I" (i) \
: "$1"); })
+
#define __insbc(port,addr,count) __INSMAC(b,1,port,addr,count)
#define __inswc(port,addr,count) __INSMAC(h,2,port,addr,count)
#define __inslc(port,addr,count) __INSMAC(w,4,port,addr,count)
-
+
#define __OUTS1(s) \
-extern inline void __outs##s(unsigned int port, const void * addr, unsigned long count) {
+static inline void __outs##s(unsigned int port, const void * addr, unsigned long count) {
#define __OUTS2(m,count) \
if (count) \
@@ -327,7 +328,7 @@
__OUTS1(s) __OUTS2(m,count) \
: "=r" (addr), "=r" (count) \
: "0" (addr), "1" (count), "i" (0), "r" (mips_io_port_base+port), "I" (i) \
- : "$1");}
+ : "$1");}
#define __OUTSMAC(m,i,port,addr,count) ({ void *_a = (addr); unsigned long _c = (count); \
__OUTS2(m,_c) \
Index: mmu_context.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/mmu_context.h,v
retrieving revision 1.5
retrieving revision 1.6
diff -u -d -r1.5 -r1.6
--- mmu_context.h 2001/10/24 23:32:54 1.5
+++ mmu_context.h 2001/10/31 18:26:52 1.6
@@ -60,7 +60,7 @@
#define ASID_VERSION_MASK ((unsigned long)~(ASID_MASK|(ASID_MASK-1)))
#define ASID_FIRST_VERSION ((unsigned long)(~ASID_VERSION_MASK) + 1)
-extern inline void
+static inline void
get_new_cpu_mmu_context(struct mm_struct *mm, unsigned long cpu)
{
unsigned long asid = ASID_CACHE(cpu);
@@ -77,7 +77,7 @@
* Initialize the context related info for a new mm_struct
* instance.
*/
-extern inline int
+static inline int
init_new_context(struct task_struct *tsk, struct mm_struct *mm)
{
#ifndef CONFIG_SMP
@@ -96,7 +96,7 @@
return 0;
}
-extern inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
+static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
struct task_struct *tsk, unsigned cpu)
{
/* Check if our ASID is of an older version and thus invalid */
@@ -111,7 +111,7 @@
* Destroy context related info for an mm_struct that is about
* to be put to rest.
*/
-extern inline void destroy_context(struct mm_struct *mm)
+static inline void destroy_context(struct mm_struct *mm)
{
#ifdef CONFIG_SMP
if (mm->context)
@@ -123,7 +123,7 @@
* After we have set current->mm to a new value, this activates
* the context for the new mm so we see the new mappings.
*/
-extern inline void
+static inline void
activate_mm(struct mm_struct *prev, struct mm_struct *next)
{
/* Unconditionally get a new ASID. */
Index: pci.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/pci.h,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- pci.h 2001/08/22 18:18:14 1.3
+++ pci.h 2001/10/31 18:26:52 1.4
@@ -23,12 +23,12 @@
#define PCIBIOS_MIN_IO 0x1000
#define PCIBIOS_MIN_MEM 0x10000000
-extern inline void pcibios_set_master(struct pci_dev *dev)
+static inline void pcibios_set_master(struct pci_dev *dev)
{
/* No special bus mastering setup handling */
}
-extern inline void pcibios_penalize_isa_irq(int irq)
+static inline void pcibios_penalize_isa_irq(int irq)
{
/* We don't do dynamic PCI IRQ allocation */
}
@@ -84,7 +84,7 @@
* Once the device is given the dma address, the device owns this memory
* until either pci_unmap_single or pci_dma_sync_single is performed.
*/
-extern inline dma_addr_t pci_map_single(struct pci_dev *hwdev, void *ptr,
+static inline dma_addr_t pci_map_single(struct pci_dev *hwdev, void *ptr,
size_t size, int direction)
{
if (direction == PCI_DMA_NONE)
@@ -105,7 +105,7 @@
* After this call, reads by the cpu to the buffer are guarenteed to see
* whatever the device wrote there.
*/
-extern inline void pci_unmap_single(struct pci_dev *hwdev, dma_addr_t dma_addr,
+static inline void pci_unmap_single(struct pci_dev *hwdev, dma_addr_t dma_addr,
size_t size, int direction)
{
if (direction == PCI_DMA_NONE)
@@ -130,7 +130,7 @@
* Device ownership issues as mentioned above for pci_map_single are
* the same here.
*/
-extern inline int pci_map_sg(struct pci_dev *hwdev, struct scatterlist *sg,
+static inline int pci_map_sg(struct pci_dev *hwdev, struct scatterlist *sg,
int nents, int direction)
{
#ifndef CONFIG_COHERENT_IO
@@ -154,7 +154,7 @@
* Again, cpu read rules concerning calls here are the same as for
* pci_unmap_single() above.
*/
-extern inline void pci_unmap_sg(struct pci_dev *hwdev, struct scatterlist *sg,
+static inline void pci_unmap_sg(struct pci_dev *hwdev, struct scatterlist *sg,
int nents, int direction)
{
if (direction == PCI_DMA_NONE)
@@ -173,7 +173,7 @@
* next point you give the PCI dma address back to the card, the
* device again owns the buffer.
*/
-extern inline void pci_dma_sync_single(struct pci_dev *hwdev,
+static inline void pci_dma_sync_single(struct pci_dev *hwdev,
dma_addr_t dma_handle,
size_t size, int direction)
{
@@ -192,7 +192,7 @@
* The same as pci_dma_sync_single but for a scatter-gather list,
* same rules and usage.
*/
-extern inline void pci_dma_sync_sg(struct pci_dev *hwdev,
+static inline void pci_dma_sync_sg(struct pci_dev *hwdev,
struct scatterlist *sg,
int nelems, int direction)
{
@@ -215,7 +215,7 @@
* only drive the low 24-bits during PCI bus mastering, then
* you would pass 0x00ffffff as the mask to this function.
*/
-extern inline int pci_dma_supported(struct pci_dev *hwdev, dma_addr_t mask)
+static inline int pci_dma_supported(struct pci_dev *hwdev, dma_addr_t mask)
{
/*
* we fall back to GFP_DMA when the mask isn't all 1s,
Index: pgalloc.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/pgalloc.h,v
retrieving revision 1.4
retrieving revision 1.5
diff -u -d -r1.4 -r1.5
--- pgalloc.h 2001/10/19 21:19:40 1.4
+++ pgalloc.h 2001/10/31 18:26:52 1.5
@@ -43,7 +43,7 @@
#endif /* CONFIG_SMP */
-extern inline void flush_tlb_pgtables(struct mm_struct *mm,
+static inline void flush_tlb_pgtables(struct mm_struct *mm,
unsigned long start, unsigned long end)
{
/* Nothing to do on MIPS. */
Index: processor.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/processor.h,v
retrieving revision 1.7
retrieving revision 1.8
diff -u -d -r1.7 -r1.8
--- processor.h 2001/10/26 16:03:53 1.7
+++ processor.h 2001/10/31 18:26:52 1.8
@@ -216,7 +216,7 @@
/*
* Return saved PC of a blocked thread.
*/
-extern inline unsigned long thread_saved_pc(struct thread_struct *t)
+static inline unsigned long thread_saved_pc(struct thread_struct *t)
{
extern void ret_from_fork(void);
Index: r4kcache.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/r4kcache.h,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- r4kcache.h 2001/10/24 23:32:54 1.1
+++ r4kcache.h 2001/10/31 18:26:52 1.2
@@ -11,7 +11,7 @@
#include <asm/asm.h>
#include <asm/cacheops.h>
-extern inline void flush_icache_line_indexed(unsigned long addr)
+static inline void flush_icache_line_indexed(unsigned long addr)
{
__asm__ __volatile__(
".set noreorder\n\t"
@@ -24,7 +24,7 @@
"i" (Index_Invalidate_I));
}
-extern inline void flush_dcache_line_indexed(unsigned long addr)
+static inline void flush_dcache_line_indexed(unsigned long addr)
{
__asm__ __volatile__(
".set noreorder\n\t"
@@ -37,7 +37,7 @@
"i" (Index_Writeback_Inv_D));
}
-extern inline void flush_scache_line_indexed(unsigned long addr)
+static inline void flush_scache_line_indexed(unsigned long addr)
{
__asm__ __volatile__(
".set noreorder\n\t"
@@ -50,7 +50,7 @@
"i" (Index_Writeback_Inv_SD));
}
-extern inline void flush_icache_line(unsigned long addr)
+static inline void flush_icache_line(unsigned long addr)
{
__asm__ __volatile__(
".set noreorder\n\t"
@@ -63,7 +63,7 @@
"i" (Hit_Invalidate_I));
}
-extern inline void flush_dcache_line(unsigned long addr)
+static inline void flush_dcache_line(unsigned long addr)
{
__asm__ __volatile__(
".set noreorder\n\t"
@@ -76,7 +76,7 @@
"i" (Hit_Writeback_Inv_D));
}
-extern inline void invalidate_dcache_line(unsigned long addr)
+static inline void invalidate_dcache_line(unsigned long addr)
{
__asm__ __volatile__(
".set noreorder\n\t"
@@ -89,7 +89,7 @@
"i" (Hit_Invalidate_D));
}
-extern inline void invalidate_scache_line(unsigned long addr)
+static inline void invalidate_scache_line(unsigned long addr)
{
__asm__ __volatile__(
".set noreorder\n\t"
@@ -102,7 +102,7 @@
"i" (Hit_Invalidate_SD));
}
-extern inline void flush_scache_line(unsigned long addr)
+static inline void flush_scache_line(unsigned long addr)
{
__asm__ __volatile__(
".set noreorder\n\t"
@@ -118,7 +118,7 @@
/*
* The next two are for badland addresses like signal trampolines.
*/
-extern inline void protected_flush_icache_line(unsigned long addr)
+static inline void protected_flush_icache_line(unsigned long addr)
{
__asm__ __volatile__(
".set noreorder\n\t"
@@ -134,7 +134,7 @@
"i" (Hit_Invalidate_I));
}
-extern inline void protected_writeback_dcache_line(unsigned long addr)
+static inline void protected_writeback_dcache_line(unsigned long addr)
{
__asm__ __volatile__(
".set noreorder\n\t"
@@ -176,7 +176,7 @@
: "r" (base), \
"i" (op));
-extern inline void blast_dcache16(void)
+static inline void blast_dcache16(void)
{
unsigned long start = KSEG0;
unsigned long end = (start + dcache_size);
@@ -187,7 +187,7 @@
}
}
-extern inline void blast_dcache16_wayLSB(void)
+static inline void blast_dcache16_wayLSB(void)
{
unsigned long start = KSEG0;
unsigned long end = (start + mips_cpu.dcache.sets * mips_cpu.dcache.linesz);
@@ -201,7 +201,7 @@
}
}
-extern inline void blast_dcache16_page(unsigned long page)
+static inline void blast_dcache16_page(unsigned long page)
{
unsigned long start = page;
unsigned long end = (start + PAGE_SIZE);
@@ -212,7 +212,7 @@
}
}
-extern inline void blast_dcache16_page_indexed(unsigned long page)
+static inline void blast_dcache16_page_indexed(unsigned long page)
{
unsigned long start = page;
unsigned long end = (start + PAGE_SIZE);
@@ -223,7 +223,7 @@
}
}
-extern inline void blast_dcache16_page_indexed_wayLSB(unsigned long page)
+static inline void blast_dcache16_page_indexed_wayLSB(unsigned long page)
{
unsigned long start = page;
unsigned long end = (start + PAGE_SIZE);
@@ -237,7 +237,7 @@
}
}
-extern inline void blast_icache16(void)
+static inline void blast_icache16(void)
{
unsigned long start = KSEG0;
unsigned long end = (start + icache_size);
@@ -248,7 +248,7 @@
}
}
-extern inline void blast_icache16_wayLSB(void)
+static inline void blast_icache16_wayLSB(void)
{
unsigned long start = KSEG0;
unsigned long end = (start + mips_cpu.icache.sets * mips_cpu.icache.linesz);
@@ -262,7 +262,7 @@
}
}
-extern inline void blast_icache16_page(unsigned long page)
+static inline void blast_icache16_page(unsigned long page)
{
unsigned long start = page;
unsigned long end = (start + PAGE_SIZE);
@@ -273,7 +273,7 @@
}
}
-extern inline void blast_icache16_page_indexed(unsigned long page)
+static inline void blast_icache16_page_indexed(unsigned long page)
{
unsigned long start = page;
unsigned long end = (start + PAGE_SIZE);
@@ -284,7 +284,7 @@
}
}
-extern inline void blast_scache16(void)
+static inline void blast_scache16(void)
{
unsigned long start = KSEG0;
unsigned long end = KSEG0 + scache_size;
@@ -295,7 +295,7 @@
}
}
-extern inline void blast_scache16_page(unsigned long page)
+static inline void blast_scache16_page(unsigned long page)
{
unsigned long start = page;
unsigned long end = page + PAGE_SIZE;
@@ -306,7 +306,7 @@
}
}
-extern inline void blast_scache16_page_indexed(unsigned long page)
+static inline void blast_scache16_page_indexed(unsigned long page)
{
unsigned long start = page;
unsigned long end = page + PAGE_SIZE;
@@ -343,7 +343,7 @@
: "r" (base), \
"i" (op));
-extern inline void blast_dcache32(void)
+static inline void blast_dcache32(void)
{
unsigned long start = KSEG0;
unsigned long end = (start + dcache_size);
@@ -354,7 +354,7 @@
}
}
-extern inline void blast_dcache32_wayLSB(void)
+static inline void blast_dcache32_wayLSB(void)
{
unsigned long start = KSEG0;
unsigned long end = (start + mips_cpu.dcache.sets * mips_cpu.dcache.linesz);
@@ -380,7 +380,7 @@
* (Revision 2.0 device errata from IDT available on http://www.idt.com/
* in .pdf format.)
*/
-extern inline void blast_dcache32_page(unsigned long page)
+static inline void blast_dcache32_page(unsigned long page)
{
unsigned long start = page;
unsigned long end = (start + PAGE_SIZE);
@@ -397,7 +397,7 @@
}
}
-extern inline void blast_dcache32_page_indexed(unsigned long page)
+static inline void blast_dcache32_page_indexed(unsigned long page)
{
unsigned long start = page;
unsigned long end = (start + PAGE_SIZE);
@@ -408,7 +408,7 @@
}
}
-extern inline void blast_dcache32_page_indexed_wayLSB(unsigned long page)
+static inline void blast_dcache32_page_indexed_wayLSB(unsigned long page)
{
unsigned long start = page;
unsigned long end = (start + PAGE_SIZE);
@@ -422,7 +422,7 @@
}
}
-extern inline void blast_icache32(void)
+static inline void blast_icache32(void)
{
unsigned long start = KSEG0;
unsigned long end = (start + icache_size);
@@ -433,7 +433,7 @@
}
}
-extern inline void blast_icache32_wayLSB(void)
+static inline void blast_icache32_wayLSB(void)
{
unsigned long start = KSEG0;
unsigned long end = (start + mips_cpu.icache.sets * mips_cpu.icache.linesz);
@@ -447,7 +447,7 @@
}
}
-extern inline void blast_icache32_page(unsigned long page)
+static inline void blast_icache32_page(unsigned long page)
{
unsigned long start = page;
unsigned long end = (start + PAGE_SIZE);
@@ -458,7 +458,7 @@
}
}
-extern inline void blast_icache32_page_indexed(unsigned long page)
+static inline void blast_icache32_page_indexed(unsigned long page)
{
unsigned long start = page;
unsigned long end = (start + PAGE_SIZE);
@@ -469,7 +469,7 @@
}
}
-extern inline void blast_scache32(void)
+static inline void blast_scache32(void)
{
unsigned long start = KSEG0;
unsigned long end = KSEG0 + scache_size;
@@ -480,7 +480,7 @@
}
}
-extern inline void blast_scache32_page(unsigned long page)
+static inline void blast_scache32_page(unsigned long page)
{
unsigned long start = page;
unsigned long end = page + PAGE_SIZE;
@@ -491,7 +491,7 @@
}
}
-extern inline void blast_scache32_page_indexed(unsigned long page)
+static inline void blast_scache32_page_indexed(unsigned long page)
{
unsigned long start = page;
unsigned long end = page + PAGE_SIZE;
@@ -528,7 +528,7 @@
: "r" (base), \
"i" (op));
-extern inline void blast_scache64(void)
+static inline void blast_scache64(void)
{
unsigned long start = KSEG0;
unsigned long end = KSEG0 + scache_size;
@@ -539,7 +539,7 @@
}
}
-extern inline void blast_scache64_page(unsigned long page)
+static inline void blast_scache64_page(unsigned long page)
{
unsigned long start = page;
unsigned long end = page + PAGE_SIZE;
@@ -550,7 +550,7 @@
}
}
-extern inline void blast_scache64_page_indexed(unsigned long page)
+static inline void blast_scache64_page_indexed(unsigned long page)
{
unsigned long start = page;
unsigned long end = page + PAGE_SIZE;
@@ -587,7 +587,7 @@
: "r" (base), \
"i" (op));
-extern inline void blast_scache128(void)
+static inline void blast_scache128(void)
{
unsigned long start = KSEG0;
unsigned long end = KSEG0 + scache_size;
@@ -598,12 +598,12 @@
}
}
-extern inline void blast_scache128_page(unsigned long page)
+static inline void blast_scache128_page(unsigned long page)
{
cache128_unroll32(page,Hit_Writeback_Inv_SD);
}
-extern inline void blast_scache128_page_indexed(unsigned long page)
+static inline void blast_scache128_page_indexed(unsigned long page)
{
cache128_unroll32(page,Index_Writeback_Inv_SD);
}
Index: softirq.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/softirq.h,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- softirq.h 2001/10/19 21:19:40 1.3
+++ softirq.h 2001/10/31 18:26:52 1.4
@@ -13,13 +13,13 @@
#include <asm/atomic.h>
#include <asm/hardirq.h>
-extern inline void cpu_bh_disable(int cpu)
+static inline void cpu_bh_disable(int cpu)
{
local_bh_count(cpu)++;
barrier();
}
-extern inline void __cpu_bh_enable(int cpu)
+static inline void __cpu_bh_enable(int cpu)
{
barrier();
local_bh_count(cpu)--;
|
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