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linux-mips-commits
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From: James S. <jsi...@us...> - 2001-10-31 17:28:57
|
Update of /cvsroot/linux-mips/linux/include/asm-mips
In directory usw-pr-cvs1:/tmp/cvs-serv24711/include/asm-mips
Modified Files:
bootinfo.h cpu.h mipsregs.h pgtable.h
Log Message:
Don't set CU1 bit if we don't have an FPU. Some b0rken silicon doesn't like it at all.
Index: bootinfo.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/bootinfo.h,v
retrieving revision 1.10
retrieving revision 1.11
diff -u -d -r1.10 -r1.11
--- bootinfo.h 2001/10/28 23:04:19 1.10
+++ bootinfo.h 2001/10/31 17:28:54 1.11
@@ -310,7 +310,6 @@
* values in setup.c (or whereever suitable) so they are in
* .data section
*/
-extern struct mips_cpu mips_cpu;
extern unsigned long mips_machtype;
extern unsigned long mips_machgroup;
extern unsigned long mips_tlb_entries;
Index: cpu.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/cpu.h,v
retrieving revision 1.11
retrieving revision 1.12
diff -u -d -r1.11 -r1.12
--- cpu.h 2001/10/26 16:09:07 1.11
+++ cpu.h 2001/10/31 17:28:54 1.12
@@ -55,12 +55,12 @@
#define PRID_IMP_R4640 0x2200
#define PRID_IMP_R4650 0x2200 /* Same as R4640 */
#define PRID_IMP_R5000 0x2300
+#define PRID_IMP_TX49 0x2d00
+#define PRID_IMP_R5900 0x2e00
#define PRID_IMP_SONIC 0x2400
#define PRID_IMP_MAGIC 0x2500
#define PRID_IMP_RM7000 0x2700
#define PRID_IMP_NEVADA 0x2800 /* RM5260 ??? */
-#define PRID_IMP_TX49 0x2d00
-#define PRID_IMP_R5900 0x2e00
#define PRID_IMP_R5432 0x5400
#define PRID_IMP_R5500 0x5500
#define PRID_IMP_4KC 0x8000
@@ -89,8 +89,8 @@
#define PRID_REV_TX3912 0x0010
#define PRID_REV_TX3922 0x0030
#define PRID_REV_TX3927 0x0040
-#define PRID_REV_TX3927B 0x0041
-#define PRID_REV_TX39H3TEG 0x0050
+#define PRID_REV_TX3927B 0x0041
+#define PRID_REV_TX39H3TEG 0x0050
#define PRID_REV_TX4955 0x0011
#define PRID_REV_TX4955A 0x0020
#define PRID_REV_TX4927 0x0021
@@ -111,6 +111,8 @@
struct cache_desc scache; /* Secondary cache */
struct cache_desc tcache; /* Tertiary/split secondary cache */
};
+
+extern struct mips_cpu mips_cpu;
#endif
Index: mipsregs.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/mipsregs.h,v
retrieving revision 1.9
retrieving revision 1.10
diff -u -d -r1.9 -r1.10
--- mipsregs.h 2001/10/27 17:28:55 1.9
+++ mipsregs.h 2001/10/31 17:28:54 1.10
@@ -148,12 +148,15 @@
*/
#include <linux/config.h>
#ifdef CONFIG_CPU_VR41XX
+
#define PM_1K 0x00000000
#define PM_4K 0x00001800
#define PM_16K 0x00007800
#define PM_64K 0x0001f800
#define PM_256K 0x0007f800
+
#else
+
#define PM_4K 0x00000000
#define PM_16K 0x00006000
#define PM_64K 0x0001e000
@@ -161,6 +164,7 @@
#define PM_1M 0x001fe000
#define PM_4M 0x007fe000
#define PM_16M 0x01ffe000
+
#endif
/*
@@ -175,75 +179,6 @@
#define PL_16M 24
/*
- * Macros to access the system control coprocessor
- */
-#define read_32bit_cp0_register(source) \
-({ int __res; \
- __asm__ __volatile__( \
- ".set\tpush\n\t" \
- ".set\treorder\n\t" \
- "mfc0\t%0,"STR(source)"\n\t" \
- ".set\tpop" \
- : "=r" (__res)); \
- __res;})
-
-#define read_32bit_cp0_set1_register(source) \
-({ int __res; \
- __asm__ __volatile__( \
- ".set\tpush\n\t" \
- ".set\treorder\n\t" \
- "cfc0\t%0,"STR(source)"\n\t" \
- ".set\tpop" \
- : "=r" (__res)); \
- __res;})
-
-/*
- * For now use this only with interrupts disabled!
- */
-#define read_64bit_cp0_register(source) \
-({ int __res; \
- __asm__ __volatile__( \
- ".set\tmips3\n\t" \
- "dmfc0\t%0,"STR(source)"\n\t" \
- ".set\tmips0" \
- : "=r" (__res)); \
- __res;})
-
-#define write_32bit_cp0_register(register,value) \
- __asm__ __volatile__( \
- "mtc0\t%0,"STR(register)"\n\t" \
- "nop" \
- : : "r" (value));
-
-#define write_32bit_cp0_set1_register(register,value) \
- __asm__ __volatile__( \
- "ctc0\t%0,"STR(register)"\n\t" \
- "nop" \
- : : "r" (value));
-
-#define write_64bit_cp0_register(register,value) \
- __asm__ __volatile__( \
- ".set\tmips3\n\t" \
- "dmtc0\t%0,"STR(register)"\n\t" \
- ".set\tmips0" \
- : : "r" (value))
-
-/*
- * This should be changed when we get a compiler that support the MIPS32 ISA.
- */
-#define read_mips32_cp0_config1() \
-({ int __res; \
- __asm__ __volatile__( \
- ".set\tnoreorder\n\t" \
- ".set\tnoat\n\t" \
- ".word\t0x40018001\n\t" \
- "move\t%0,$1\n\t" \
- ".set\tat\n\t" \
- ".set\treorder" \
- :"=r" (__res)); \
- __res;})
-
-/*
* R4x00 interrupt enable / cause bits
*/
#define IE_SW0 (1<< 8)
@@ -267,55 +202,6 @@
#define C_IRQ4 (1<<14)
#define C_IRQ5 (1<<15)
-#ifndef _LANGUAGE_ASSEMBLY
-/*
- * Manipulate the status register.
- * Mostly used to access the interrupt bits.
- */
-#define __BUILD_SET_CP0(name,register) \
-extern inline unsigned int \
-set_cp0_##name(unsigned int set) \
-{ \
- unsigned int res; \
- \
- res = read_32bit_cp0_register(register); \
- res |= set; \
- write_32bit_cp0_register(register, res); \
- \
- return res; \
-} \
- \
-extern inline unsigned int \
-clear_cp0_##name(unsigned int clear) \
-{ \
- unsigned int res; \
- \
- res = read_32bit_cp0_register(register); \
- res &= ~clear; \
- write_32bit_cp0_register(register, res); \
- \
- return res; \
-} \
- \
-extern inline unsigned int \
-change_cp0_##name(unsigned int change, unsigned int new) \
-{ \
- unsigned int res; \
- \
- res = read_32bit_cp0_register(register); \
- res &= ~change; \
- res |= (new & change); \
- write_32bit_cp0_register(register, res); \
- \
- return res; \
-}
-
-__BUILD_SET_CP0(status,CP0_STATUS)
-__BUILD_SET_CP0(cause,CP0_CAUSE)
-__BUILD_SET_CP0(config,CP0_CONFIG)
-
-#endif /* defined (_LANGUAGE_ASSEMBLY) */
-
/*
* Bitfields in the R4xx0 cp0 status register
*/
@@ -547,5 +433,440 @@
#define CEB_SUPERVISOR 4 /* Count events in supvervisor mode EXL = ERL = 0 */
#define CEB_KERNEL 2 /* Count events in kernel mode EXL = ERL = 0 */
#define CEB_EXL 1 /* Count events with EXL = 1, ERL = 0 */
+
+#ifndef _LANGUAGE_ASSEMBLY
+
+/*
+ * Macros to access the system control coprocessor
+ */
+#define read_32bit_cp0_register(source) \
+({ int __res; \
+ __asm__ __volatile__( \
+ ".set\tpush\n\t" \
+ ".set\treorder\n\t" \
+ "mfc0\t%0,"STR(source)"\n\t" \
+ ".set\tpop" \
+ : "=r" (__res)); \
+ __res;})
+
+#define read_32bit_cp0_set1_register(source) \
+({ int __res; \
+ __asm__ __volatile__( \
+ ".set\tpush\n\t" \
+ ".set\treorder\n\t" \
+ "cfc0\t%0,"STR(source)"\n\t" \
+ ".set\tpop" \
+ : "=r" (__res)); \
+ __res;})
+
+/*
+ * For now use this only with interrupts disabled!
+ */
+#define read_64bit_cp0_register(source) \
+({ int __res; \
+ __asm__ __volatile__( \
+ ".set\tmips3\n\t" \
+ "dmfc0\t%0,"STR(source)"\n\t" \
+ ".set\tmips0" \
+ : "=r" (__res)); \
+ __res;})
+
+#define write_32bit_cp0_register(register,value) \
+ __asm__ __volatile__( \
+ "mtc0\t%0,"STR(register)"\n\t" \
+ "nop" \
+ : : "r" (value));
+
+#define write_32bit_cp0_set1_register(register,value) \
+ __asm__ __volatile__( \
+ "ctc0\t%0,"STR(register)"\n\t" \
+ "nop" \
+ : : "r" (value));
+
+#define write_64bit_cp0_register(register,value) \
+ __asm__ __volatile__( \
+ ".set\tmips3\n\t" \
+ "dmtc0\t%0,"STR(register)"\n\t" \
+ ".set\tmips0" \
+ : : "r" (value))
+
+/*
+ * This should be changed when we get a compiler that support the MIPS32 ISA.
+ */
+#define read_mips32_cp0_config1() \
+({ int __res; \
+ __asm__ __volatile__( \
+ ".set\tnoreorder\n\t" \
+ ".set\tnoat\n\t" \
+ ".word\t0x40018001\n\t" \
+ "move\t%0,$1\n\t" \
+ ".set\tat\n\t" \
+ ".set\treorder" \
+ :"=r" (__res)); \
+ __res;})
+
+/* TLB operations. */
+static inline void tlb_probe(void)
+{
+ __asm__ __volatile__(
+ ".set push\n\t"
+ ".set reorder\n\t"
+ "tlbp\n\t"
+ ".set pop");
+}
+
+static inline void tlb_read(void)
+{
+ __asm__ __volatile__(
+ ".set push\n\t"
+ ".set reorder\n\t"
+ "tlbr\n\t"
+ ".set pop");
+}
+
+static inline void tlb_write_indexed(void)
+{
+ __asm__ __volatile__(
+ ".set push\n\t"
+ ".set reorder\n\t"
+ "tlbwi\n\t"
+ ".set pop");
+}
+
+static inline void tlb_write_random(void)
+{
+ __asm__ __volatile__(
+ ".set push\n\t"
+ ".set reorder\n\t"
+ "tlbwr\n\t"
+ ".set pop");
+}
+
+/* Dealing with various CP0 mmu/cache related registers. */
+
+
+static inline unsigned long get_pagemask(void)
+{
+ unsigned long val;
+
+ __asm__ __volatile__(
+ ".set push\n\t"
+ ".set reorder\n\t"
+ "mfc0 %0, $5\n\t"
+ ".set pop"
+ : "=r" (val));
+ return val;
+}
+
+static inline void set_pagemask(unsigned long val)
+{
+ __asm__ __volatile__(
+ ".set push\n\t"
+ ".set reorder\n\t"
+ "mtc0 %z0, $5\n\t"
+ ".set pop"
+ : : "Jr" (val));
+}
+
+/* CP0_ENTRYLO0 and CP0_ENTRYLO1 registers */
+static inline unsigned long get_entrylo0(void)
+{
+ unsigned long val;
+
+ __asm__ __volatile__(
+ ".set push\n\t"
+ ".set reorder\n\t"
+ "mfc0 %0, $2\n\t"
+ ".set pop"
+ : "=r" (val));
+ return val;
+}
+
+static inline void set_entrylo0(unsigned long val)
+{
+ __asm__ __volatile__(
+ ".set push\n\t"
+ ".set reorder\n\t"
+ "mtc0 %z0, $2\n\t"
+ ".set pop"
+ : : "Jr" (val));
+}
+
+static inline unsigned long get_entrylo1(void)
+{
+ unsigned long val;
+
+ __asm__ __volatile__(
+ ".set push\n\t"
+ ".set reorder\n\t"
+ "mfc0 %0, $3\n\t"
+ ".set pop" : "=r" (val));
+
+ return val;
+}
+
+static inline void set_entrylo1(unsigned long val)
+{
+ __asm__ __volatile__(
+ ".set push\n\t"
+ ".set reorder\n\t"
+ "mtc0 %z0, $3\n\t"
+ ".set pop"
+ : : "Jr" (val));
+}
+
+/* CP0_ENTRYHI register */
+static inline unsigned long get_entryhi(void)
+{
+ unsigned long val;
+
+ __asm__ __volatile__(
+ ".set push\n\t"
+ ".set reorder\n\t"
+ "mfc0 %0, $10\n\t"
+ ".set pop"
+ : "=r" (val));
+
+ return val;
+}
+
+static inline void set_entryhi(unsigned long val)
+{
+ __asm__ __volatile__(
+ ".set push\n\t"
+ ".set reorder\n\t"
+ "mtc0 %z0, $10\n\t"
+ ".set pop"
+ : : "Jr" (val));
+}
+
+/* CP0_INDEX register */
+static inline unsigned long get_index(void)
+{
+ unsigned long val;
+
+ __asm__ __volatile__(
+ ".set push\n\t"
+ ".set reorder\n\t"
+ "mfc0 %0, $0\n\t"
+ ".set pop"
+ : "=r" (val));
+ return val;
+}
+
+static inline void set_index(unsigned long val)
+{
+ __asm__ __volatile__(
+ ".set push\n\t"
+ ".set reorder\n\t"
+ "mtc0 %z0, $0\n\t"
+ ".set pop"
+ : : "Jr" (val));
+}
+
+/* CP0_WIRED register */
+static inline unsigned long get_wired(void)
+{
+ unsigned long val;
+
+ __asm__ __volatile__(
+ ".set push\n\t"
+ ".set reorder\n\t"
+ "mfc0 %0, $6\n\t"
+ ".set pop"
+ : "=r" (val));
+ return val;
+}
+
+static inline void set_wired(unsigned long val)
+{
+ __asm__ __volatile__(
+ ".set push\n\t"
+ ".set reorder\n\t"
+ "mtc0 %z0, $6\n\t"
+ ".set pop"
+ : : "Jr" (val));
+}
+
+/* CP0_STATUS register */
+static inline unsigned int get_status(void)
+{
+ unsigned long val;
+
+ __asm__ __volatile__(
+ ".set push\n\t"
+ ".set reorder\n\t"
+ "mfc0 %0, $12\n\t"
+ ".set pop"
+ : "=r" (val));
+ return val;
+}
+
+static inline void set_status(unsigned long val)
+{
+ __asm__ __volatile__(
+ ".set push\n\t"
+ ".set reorder\n\t"
+ "mtc0 %z0, $12\n\t"
+ ".set pop"
+ : : "Jr" (val));
+}
+
+static inline unsigned long get_info(void)
+{
+ unsigned long val;
+
+ __asm__(
+ ".set push\n\t"
+ ".set reorder\n\t"
+ "mfc0 %0, $7\n\t"
+ ".set pop"
+ : "=r" (val));
+ return val;
+}
+
+/* CP0_TAGLO and CP0_TAGHI registers */
+static inline unsigned long get_taglo(void)
+{
+ unsigned long val;
+
+ __asm__ __volatile__(
+ ".set push\n\t"
+ ".set reorder\n\t"
+ "mfc0 %0, $28\n\t"
+ ".set pop"
+ : "=r" (val));
+ return val;
+}
+
+static inline void set_taglo(unsigned long val)
+{
+ __asm__ __volatile__(
+ ".set push\n\t"
+ ".set reorder\n\t"
+ "mtc0 %z0, $28\n\t"
+ ".set pop"
+ : : "Jr" (val));
+}
+
+static inline unsigned long get_taghi(void)
+{
+ unsigned long val;
+
+ __asm__ __volatile__(
+ ".set push\n\t"
+ ".set reorder\n\t"
+ "mfc0 %0, $29\n\t"
+ ".set pop"
+ : "=r" (val));
+ return val;
+}
+
+static inline void set_taghi(unsigned long val)
+{
+ __asm__ __volatile__(
+ ".set push\n\t"
+ ".set reorder\n\t"
+ "mtc0 %z0, $29\n\t"
+ ".set pop"
+ : : "Jr" (val));
+}
+
+/* CP0_CONTEXT register */
+static inline unsigned long get_context(void)
+{
+ unsigned long val;
+
+ __asm__ __volatile__(
+ ".set push\n\t"
+ ".set reorder\n\t"
+ "mfc0 %0, $4\n\t"
+ ".set pop"
+ : "=r" (val));
+
+ return val;
+}
+
+static inline void set_context(unsigned long val)
+{
+ __asm__ __volatile__(
+ ".set push\n\t"
+ ".set reorder\n\t"
+ "mtc0 %z0, $4\n\t"
+ ".set pop"
+ : : "Jr" (val));
+}
+
+/*
+ * Manipulate the status register.
+ * Mostly used to access the interrupt bits.
+ */
+#define __BUILD_SET_CP0(name,register) \
+static inline unsigned int \
+set_cp0_##name(unsigned int set) \
+{ \
+ unsigned int res; \
+ \
+ res = read_32bit_cp0_register(register); \
+ res |= set; \
+ write_32bit_cp0_register(register, res); \
+ \
+ return res; \
+} \
+ \
+static inline unsigned int \
+clear_cp0_##name(unsigned int clear) \
+{ \
+ unsigned int res; \
+ \
+ res = read_32bit_cp0_register(register); \
+ res &= ~clear; \
+ write_32bit_cp0_register(register, res); \
+ \
+ return res; \
+} \
+ \
+static inline unsigned int \
+change_cp0_##name(unsigned int change, unsigned int new) \
+{ \
+ unsigned int res; \
+ \
+ res = read_32bit_cp0_register(register); \
+ res &= ~change; \
+ res |= (new & change); \
+ write_32bit_cp0_register(register, res); \
+ \
+ return res; \
+}
+
+__BUILD_SET_CP0(status,CP0_STATUS)
+__BUILD_SET_CP0(cause,CP0_CAUSE)
+__BUILD_SET_CP0(config,CP0_CONFIG)
+
+#define __enable_fpu() \
+do { \
+ set_cp0_status(ST0_CU1); \
+ asm("nop;nop;nop;nop"); /* max. hazard */ \
+} while (0)
+
+#define __disable_fpu() \
+do { \
+ clear_cp0_status(ST0_CU1); \
+ /* We don't care about the cp0 hazard here */ \
+} while (0)
+
+#define enable_fpu() \
+do { \
+ if (mips_cpu.options & MIPS_CPU_FPU) \
+ __enable_fpu(); \
+} while (0)
+
+#define disable_fpu() \
+do { \
+ if (mips_cpu.options & MIPS_CPU_FPU) \
+ __disable_fpu(); \
+} while (0)
+
+#endif /* !defined (_LANGUAGE_ASSEMBLY) */
#endif /* _ASM_MIPSREGS_H */
Index: pgtable.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/pgtable.h,v
retrieving revision 1.6
retrieving revision 1.7
diff -u -d -r1.6 -r1.7
--- pgtable.h 2001/10/24 23:32:54 1.6
+++ pgtable.h 2001/10/31 17:28:54 1.7
@@ -261,29 +261,29 @@
* Conversion functions: convert a page and protection to a page entry,
* and a page entry and page directory to the page they refer to.
*/
-extern inline unsigned long pmd_page(pmd_t pmd)
+static inline unsigned long pmd_page(pmd_t pmd)
{
return pmd_val(pmd);
}
-extern inline void pmd_set(pmd_t * pmdp, pte_t * ptep)
+static inline void pmd_set(pmd_t * pmdp, pte_t * ptep)
{
pmd_val(*pmdp) = (((unsigned long) ptep) & PAGE_MASK);
}
-extern inline int pte_none(pte_t pte) { return !pte_val(pte); }
-extern inline int pte_present(pte_t pte) { return pte_val(pte) & _PAGE_PRESENT; }
+static inline int pte_none(pte_t pte) { return !pte_val(pte); }
+static inline int pte_present(pte_t pte) { return pte_val(pte) & _PAGE_PRESENT; }
/* Certain architectures need to do special things when pte's
* within a page table are directly modified. Thus, the following
* hook is made available.
*/
-extern inline void set_pte(pte_t *ptep, pte_t pteval)
+static inline void set_pte(pte_t *ptep, pte_t pteval)
{
*ptep = pteval;
}
-extern inline void pte_clear(pte_t *ptep)
+static inline void pte_clear(pte_t *ptep)
{
set_pte(ptep, __pte(0));
}
@@ -298,23 +298,23 @@
/*
* Empty pgd/pmd entries point to the invalid_pte_table.
*/
-extern inline int pmd_none(pmd_t pmd)
+static inline int pmd_none(pmd_t pmd)
{
return pmd_val(pmd) == (unsigned long) invalid_pte_table;
}
-extern inline int pmd_bad(pmd_t pmd)
+static inline int pmd_bad(pmd_t pmd)
{
return ((pmd_page(pmd) > (unsigned long) high_memory) ||
(pmd_page(pmd) < PAGE_OFFSET));
}
-extern inline int pmd_present(pmd_t pmd)
+static inline int pmd_present(pmd_t pmd)
{
return (pmd_val(pmd) != (unsigned long) invalid_pte_table);
}
-extern inline void pmd_clear(pmd_t *pmdp)
+static inline void pmd_clear(pmd_t *pmdp)
{
pmd_val(*pmdp) = ((unsigned long) invalid_pte_table);
}
@@ -324,10 +324,10 @@
* setup: the pgd is never bad, and a pmd always exists (as it's folded
* into the pgd entry)
*/
-extern inline int pgd_none(pgd_t pgd) { return 0; }
-extern inline int pgd_bad(pgd_t pgd) { return 0; }
-extern inline int pgd_present(pgd_t pgd) { return 1; }
-extern inline void pgd_clear(pgd_t *pgdp) { }
+static inline int pgd_none(pgd_t pgd) { return 0; }
+static inline int pgd_bad(pgd_t pgd) { return 0; }
+static inline int pgd_present(pgd_t pgd) { return 1; }
+static inline void pgd_clear(pgd_t *pgdp) { }
/*
* Permanent address of a page. On MIPS we never have highmem, so this
@@ -344,36 +344,36 @@
* The following only work if pte_present() is true.
* Undefined behaviour if not..
*/
-extern inline int pte_read(pte_t pte) { return pte_val(pte) & _PAGE_READ; }
-extern inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_WRITE; }
-extern inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_MODIFIED; }
-extern inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; }
+static inline int pte_read(pte_t pte) { return pte_val(pte) & _PAGE_READ; }
+static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_WRITE; }
+static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_MODIFIED; }
+static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; }
-extern inline pte_t pte_wrprotect(pte_t pte)
+static inline pte_t pte_wrprotect(pte_t pte)
{
pte_val(pte) &= ~(_PAGE_WRITE | _PAGE_SILENT_WRITE);
return pte;
}
-extern inline pte_t pte_rdprotect(pte_t pte)
+static inline pte_t pte_rdprotect(pte_t pte)
{
pte_val(pte) &= ~(_PAGE_READ | _PAGE_SILENT_READ);
return pte;
}
-extern inline pte_t pte_mkclean(pte_t pte)
+static inline pte_t pte_mkclean(pte_t pte)
{
pte_val(pte) &= ~(_PAGE_MODIFIED|_PAGE_SILENT_WRITE);
return pte;
}
-extern inline pte_t pte_mkold(pte_t pte)
+static inline pte_t pte_mkold(pte_t pte)
{
pte_val(pte) &= ~(_PAGE_ACCESSED|_PAGE_SILENT_READ);
return pte;
}
-extern inline pte_t pte_mkwrite(pte_t pte)
+static inline pte_t pte_mkwrite(pte_t pte)
{
pte_val(pte) |= _PAGE_WRITE;
if (pte_val(pte) & _PAGE_MODIFIED)
@@ -381,7 +381,7 @@
return pte;
}
-extern inline pte_t pte_mkread(pte_t pte)
+static inline pte_t pte_mkread(pte_t pte)
{
pte_val(pte) |= _PAGE_READ;
if (pte_val(pte) & _PAGE_ACCESSED)
@@ -389,7 +389,7 @@
return pte;
}
-extern inline pte_t pte_mkdirty(pte_t pte)
+static inline pte_t pte_mkdirty(pte_t pte)
{
pte_val(pte) |= _PAGE_MODIFIED;
if (pte_val(pte) & _PAGE_WRITE)
@@ -414,7 +414,7 @@
return __pgprot(prot);
}
-extern inline pte_t pte_mkyoung(pte_t pte)
+static inline pte_t pte_mkyoung(pte_t pte)
{
pte_val(pte) |= _PAGE_ACCESSED;
if (pte_val(pte) & _PAGE_READ)
@@ -448,7 +448,7 @@
})
#endif
-extern inline pte_t mk_pte_phys(unsigned long physpage, pgprot_t pgprot)
+static inline pte_t mk_pte_phys(unsigned long physpage, pgprot_t pgprot)
{
#ifdef CONFIG_CPU_VR41XX
return __pte((physpage << 2) | pgprot_val(pgprot));
@@ -457,7 +457,7 @@
#endif
}
-extern inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
+static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
{
return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot));
}
@@ -470,19 +470,19 @@
#define pgd_index(address) ((address) >> PGDIR_SHIFT)
/* to find an entry in a page-table-directory */
-extern inline pgd_t *pgd_offset(struct mm_struct *mm, unsigned long address)
+static inline pgd_t *pgd_offset(struct mm_struct *mm, unsigned long address)
{
return mm->pgd + pgd_index(address);
}
/* Find an entry in the second-level page table.. */
-extern inline pmd_t *pmd_offset(pgd_t *dir, unsigned long address)
+static inline pmd_t *pmd_offset(pgd_t *dir, unsigned long address)
{
return (pmd_t *) dir;
}
/* Find an entry in the third-level page table.. */
-extern inline pte_t *pte_offset(pmd_t * dir, unsigned long address)
+static inline pte_t *pte_offset(pmd_t * dir, unsigned long address)
{
return (pte_t *) (pmd_page(*dir)) +
((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1));
@@ -506,274 +506,6 @@
/* Needs to be defined here and not in linux/mm.h, as it is arch dependent */
#define PageSkip(page) (0)
#define kern_addr_valid(addr) (1)
-
-/* TLB operations. */
-extern inline void tlb_probe(void)
-{
- __asm__ __volatile__(
- ".set push\n\t"
- ".set reorder\n\t"
- "tlbp\n\t"
- ".set pop");
-}
-
-extern inline void tlb_read(void)
-{
- __asm__ __volatile__(
- ".set push\n\t"
- ".set reorder\n\t"
- "tlbr\n\t"
- ".set pop");
-}
-
-extern inline void tlb_write_indexed(void)
-{
- __asm__ __volatile__(
- ".set push\n\t"
- ".set reorder\n\t"
- "tlbwi\n\t"
- ".set pop");
-}
-
-extern inline void tlb_write_random(void)
-{
- __asm__ __volatile__(
- ".set push\n\t"
- ".set reorder\n\t"
- "tlbwr\n\t"
- ".set pop");
-}
-
-/* Dealing with various CP0 mmu/cache related registers. */
-
-/* CP0_PAGEMASK register */
-extern inline unsigned long get_pagemask(void)
-{
- unsigned long val;
-
- __asm__ __volatile__(
- ".set push\n\t"
- ".set reorder\n\t"
- "mfc0 %0, $5\n\t"
- ".set pop"
- : "=r" (val));
- return val;
-}
-
-extern inline void set_pagemask(unsigned long val)
-{
- __asm__ __volatile__(
- ".set push\n\t"
- ".set reorder\n\t"
- "mtc0 %z0, $5\n\t"
- ".set pop"
- : : "Jr" (val));
-}
-
-/* CP0_ENTRYLO0 and CP0_ENTRYLO1 registers */
-extern inline unsigned long get_entrylo0(void)
-{
- unsigned long val;
-
- __asm__ __volatile__(
- ".set push\n\t"
- ".set reorder\n\t"
- "mfc0 %0, $2\n\t"
- ".set pop"
- : "=r" (val));
- return val;
-}
-
-extern inline void set_entrylo0(unsigned long val)
-{
- __asm__ __volatile__(
- ".set push\n\t"
- ".set reorder\n\t"
- "mtc0 %z0, $2\n\t"
- ".set pop"
- : : "Jr" (val));
-}
-
-extern inline unsigned long get_entrylo1(void)
-{
- unsigned long val;
-
- __asm__ __volatile__(
- ".set push\n\t"
- ".set reorder\n\t"
- "mfc0 %0, $3\n\t"
- ".set pop" : "=r" (val));
-
- return val;
-}
-
-extern inline void set_entrylo1(unsigned long val)
-{
- __asm__ __volatile__(
- ".set push\n\t"
- ".set reorder\n\t"
- "mtc0 %z0, $3\n\t"
- ".set pop"
- : : "Jr" (val));
-}
-
-/* CP0_ENTRYHI register */
-extern inline unsigned long get_entryhi(void)
-{
- unsigned long val;
-
- __asm__ __volatile__(
- ".set push\n\t"
- ".set reorder\n\t"
- "mfc0 %0, $10\n\t"
- ".set pop"
- : "=r" (val));
-
- return val;
-}
-
-extern inline void set_entryhi(unsigned long val)
-{
- __asm__ __volatile__(
- ".set push\n\t"
- ".set reorder\n\t"
- "mtc0 %z0, $10\n\t"
- ".set pop"
- : : "Jr" (val));
-}
-
-/* CP0_INDEX register */
-extern inline unsigned long get_index(void)
-{
- unsigned long val;
-
- __asm__ __volatile__(
- ".set push\n\t"
- ".set reorder\n\t"
- "mfc0 %0, $0\n\t"
- ".set pop"
- : "=r" (val));
- return val;
-}
-
-extern inline void set_index(unsigned long val)
-{
- __asm__ __volatile__(
- ".set push\n\t"
- ".set reorder\n\t"
- "mtc0 %z0, $0\n\t"
- ".set pop"
- : : "Jr" (val));
-}
-
-/* CP0_WIRED register */
-extern inline unsigned long get_wired(void)
-{
- unsigned long val;
-
- __asm__ __volatile__(
- ".set push\n\t"
- ".set reorder\n\t"
- "mfc0 %0, $6\n\t"
- ".set pop"
- : "=r" (val));
- return val;
-}
-
-extern inline void set_wired(unsigned long val)
-{
- __asm__ __volatile__(
- ".set push\n\t"
- ".set reorder\n\t"
- "mtc0 %z0, $6\n\t"
- ".set pop"
- : : "Jr" (val));
-}
-
-extern inline unsigned long get_info(void)
-{
- unsigned long val;
-
- __asm__(
- ".set push\n\t"
- ".set reorder\n\t"
- "mfc0 %0, $7\n\t"
- ".set pop"
- : "=r" (val));
- return val;
-}
-
-/* CP0_TAGLO and CP0_TAGHI registers */
-extern inline unsigned long get_taglo(void)
-{
- unsigned long val;
-
- __asm__ __volatile__(
- ".set push\n\t"
- ".set reorder\n\t"
- "mfc0 %0, $28\n\t"
- ".set pop"
- : "=r" (val));
- return val;
-}
-
-extern inline void set_taglo(unsigned long val)
-{
- __asm__ __volatile__(
- ".set push\n\t"
- ".set reorder\n\t"
- "mtc0 %z0, $28\n\t"
- ".set pop"
- : : "Jr" (val));
-}
-
-extern inline unsigned long get_taghi(void)
-{
- unsigned long val;
-
- __asm__ __volatile__(
- ".set push\n\t"
- ".set reorder\n\t"
- "mfc0 %0, $29\n\t"
- ".set pop"
- : "=r" (val));
- return val;
-}
-
-extern inline void set_taghi(unsigned long val)
-{
- __asm__ __volatile__(
- ".set push\n\t"
- ".set reorder\n\t"
- "mtc0 %z0, $29\n\t"
- ".set pop"
- : : "Jr" (val));
-}
-
-/* CP0_CONTEXT register */
-extern inline unsigned long get_context(void)
-{
- unsigned long val;
-
- __asm__ __volatile__(
- ".set push\n\t"
- ".set reorder\n\t"
- "mfc0 %0, $4\n\t"
- ".set pop"
- : "=r" (val));
-
- return val;
-}
-
-extern inline void set_context(unsigned long val)
-{
- __asm__ __volatile__(
- ".set push\n\t"
- ".set reorder\n\t"
- "mtc0 %z0, $4\n\t"
- ".set pop"
- : : "Jr" (val));
-}
#include <asm-generic/pgtable.h>
|
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