Update of /cvsroot/linux-mips/linux/include/asm-mips
In directory usw-pr-cvs1:/tmp/cvs-serv20100/include/asm-mips
Modified Files:
au1000.h pb1000.h
Log Message:
Sync up with oss tree:
* explicitly set polarity of all interrupts
* added pci_auto config option
* updated defconfig file
* moved the au1000 specific tlb handler to tlbex-r4k.S
* updated au1000.h with IrDA registers
Index: au1000.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/au1000.h,v
retrieving revision 1.8
retrieving revision 1.9
diff -u -d -r1.8 -r1.9
--- au1000.h 2001/10/22 19:16:45 1.8
+++ au1000.h 2001/10/31 06:16:24 1.9
@@ -608,21 +608,43 @@
#define SSI1_CONTROL 0xB1680100
/* IrDA Controller */
-#define IR_RING_PTR_STATUS 0xB1500000
-#define IR_RING_BASE_ADDR_H 0xB1500004
-#define IR_RING_BASE_ADDR_L 0xB1500008
-#define IR_RING_SIZE 0xB150000C
-#define IR_RING_PROMPT 0xB1500010
-#define IR_RING_ADDR_CMPR 0xB1500014
-#define IR_CONFIG_1 0xB1500020
-#define IR_SIR_FLAGS 0xB1500024
-#define IR_ENABLE 0xB1500028
-#define IR_READ_PHY_CONFIG 0xB150002C
-#define IR_WRITE_PHY_CONFIG 0xB1500030
-#define IR_MAX_PKT_LEN 0xB1500034
-#define IR_RX_BYTE_CNT 0xB1500038
-#define IR_CONFIG_2 0xB150003C
-#define IR_INTERFACE_CONFIG 0xB1500040
+#define IRDA_BASE 0xB0300000
+#define IR_RING_PTR_STATUS (IRDA_BASE+0x00)
+#define IR_RING_BASE_ADDR_H (IRDA_BASE+0x04)
+#define IR_RING_BASE_ADDR_L (IRDA_BASE+0x08)
+#define IR_RING_SIZE (IRDA_BASE+0x0C)
+#define IR_RING_PROMPT (IRDA_BASE+0x10)
+#define IR_RING_ADDR_CMPR (IRDA_BASE+0x14)
+#define IR_INT_CLEAR (IRDA_BASE+0x18)
+#define IR_CONFIG_1 (IRDA_BASE+0x20)
+ #define IR_RX_INVERT_LED (1<<0)
+ #define IR_TX_INVERT_LED (1<<1)
+ #define IR_ST (1<<2)
+ #define IR_SF (1<<3)
+ #define IR_SIR (1<<4)
+ #define IR_MIR (1<<5)
+ #define IR_FIR (1<<6)
+ #define IR_16CRC (1<<7)
+ #define IR_TD (1<<8)
+ #define IR_RX_ALL (1<<9)
+ #define IR_DMA_ENABLE (1<<10)
+ #define IR_RX_ENABLE (1<<11)
+ #define IR_TX_ENABLE (1<<12)
+ #define IR_LOOPBACK (1<<14)
+ #define IR_SIR_MODE (IR_SIR | IR_DMA_ENABLE | \
+ IR_RX_ALL | IR_RX_ENABLE | IR_SF | IR_16CRC)
+#define IR_SIR_FLAGS (IRDA_BASE+0x24)
+#define IR_ENABLE (IRDA_BASE+0x28)
+ #define IR_RX_STATUS (1<<9)
+ #define IR_TX_STATUS (1<<10)
+#define IR_READ_PHY_CONFIG (IRDA_BASE+0x2C)
+#define IR_WRITE_PHY_CONFIG (IRDA_BASE+0x30)
+#define IR_MAX_PKT_LEN (IRDA_BASE+0x34)
+#define IR_RX_BYTE_CNT (IRDA_BASE+0x38)
+#define IR_CONFIG_2 (IRDA_BASE+0x3C)
+ #define IR_MODE_INV (1<<0)
+ #define IR_ONE_PIN (1<<1)
+#define IR_INTERFACE_CONFIG (IRDA_BASE+0x40)
/* GPIO */
#define PIN_FUNCTION 0xB190002C
Index: pb1000.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/pb1000.h,v
retrieving revision 1.5
retrieving revision 1.6
diff -u -d -r1.5 -r1.6
--- pb1000.h 2001/10/22 19:16:45 1.5
+++ pb1000.h 2001/10/31 06:16:24 1.6
@@ -110,54 +110,54 @@
#define PCI_MEM_START 0x18000000
#define PCI_MEM_END 0x18ffffff
-extern inline u8 au_pci_io_readb(u32 addr)
+static inline u8 au_pci_io_readb(u32 addr)
{
writel(addr, PCI_IO_ADDR);
writel((readl(PCI_BRIDGE_CONFIG) & 0xffffcfff) | (1<<12), PCI_BRIDGE_CONFIG);
return (readl(PCI_IO_DATA_PORT) & 0xff);
}
-extern inline u16 au_pci_io_readw(u32 addr)
+static inline u16 au_pci_io_readw(u32 addr)
{
writel(addr, PCI_IO_ADDR);
writel((readl(PCI_BRIDGE_CONFIG) & 0xffffcfff) | (1<<13), PCI_BRIDGE_CONFIG);
return (readl(PCI_IO_DATA_PORT) & 0xffff);
}
-extern inline u32 au_pci_io_readl(u32 addr)
+static inline u32 au_pci_io_readl(u32 addr)
{
writel(addr, PCI_IO_ADDR);
writel((readl(PCI_BRIDGE_CONFIG) & 0xffffcfff), PCI_BRIDGE_CONFIG);
return readl(PCI_IO_DATA_PORT);
}
-extern inline void au_pci_io_writeb(u8 val, u32 addr)
+static inline void au_pci_io_writeb(u8 val, u32 addr)
{
writel(addr, PCI_IO_ADDR);
writel((readl(PCI_BRIDGE_CONFIG) & 0xffffcfff) | (1<<12), PCI_BRIDGE_CONFIG);
writel(val, PCI_IO_DATA_PORT);
}
-extern inline void au_pci_io_writew(u16 val, u32 addr)
+static inline void au_pci_io_writew(u16 val, u32 addr)
{
writel(addr, PCI_IO_ADDR);
writel((readl(PCI_BRIDGE_CONFIG) & 0xffffcfff) | (1<<13), PCI_BRIDGE_CONFIG);
writel(val, PCI_IO_DATA_PORT);
}
-extern inline void au_pci_io_writel(u32 val, u32 addr)
+static inline void au_pci_io_writel(u32 val, u32 addr)
{
writel(addr, PCI_IO_ADDR);
writel(readl(PCI_BRIDGE_CONFIG) & 0xffffcfff, PCI_BRIDGE_CONFIG);
writel(val, PCI_IO_DATA_PORT);
}
-extern inline void set_sdram_extbyte(void)
+static inline void set_sdram_extbyte(void)
{
writel(readl(PCI_BRIDGE_CONFIG) & 0xffffff00, PCI_BRIDGE_CONFIG);
}
-extern inline void set_slot_extbyte(void)
+static inline void set_slot_extbyte(void)
{
writel((readl(PCI_BRIDGE_CONFIG) & 0xffffbf00) | 0x18, PCI_BRIDGE_CONFIG);
}
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