Update of /cvsroot/linux-mips/linux/include/asm-mips64
In directory usw-pr-cvs1:/tmp/cvs-serv20204/include/asm-mips64
Modified Files:
bootinfo.h mipsregs.h softirq.h system.h
Log Message:
Sync with OSS (except for sysmips, which is waiting to be tested first).
Index: bootinfo.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips64/bootinfo.h,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -d -r1.2 -r1.3
--- bootinfo.h 2001/07/09 19:28:48 1.2
+++ bootinfo.h 2001/10/27 17:28:55 1.3
@@ -91,8 +91,9 @@
#define MACH_SGI_CHALLENGE_S 1 /* The Challenge S server */
#define MACH_SGI_INDIGO2 2 /* The Indigo2 system */
#define MACH_SGI_IP27 3 /* Origin 200, Origin 2000, Onyx 2 */
+#define MACH_SGI_IP32 4 /* O2 */
-#define GROUP_SGI_NAMES { "Indy", "Challenge S", "Indigo2", "IP27" }
+#define GROUP_SGI_NAMES { "Indy", "Challenge S", "Indigo2", "IP27", "O2" }
/*
Index: mipsregs.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips64/mipsregs.h,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- mipsregs.h 2001/08/20 16:03:12 1.3
+++ mipsregs.h 2001/10/27 17:28:55 1.4
@@ -145,14 +145,39 @@
* Mostly used to access the interrupt bits.
*/
#define __BUILD_SET_CP0(name,register) \
-extern __inline__ unsigned int \
-set_cp0_##name(unsigned int change, unsigned int new) \
+extern inline unsigned int \
+set_cp0_##name(unsigned int set) \
+{ \
+ unsigned int res; \
+ \
+ res = read_32bit_cp0_register(register); \
+ res |= set; \
+ write_32bit_cp0_register(register, res); \
+ \
+ return res; \
+} \
+ \
+extern inline unsigned int \
+clear_cp0_##name(unsigned int clear) \
+{ \
+ unsigned int res; \
+ \
+ res = read_32bit_cp0_register(register); \
+ res &= ~clear; \
+ write_32bit_cp0_register(register, res); \
+ \
+ return res; \
+} \
+ \
+extern inline unsigned int \
+change_cp0_##name(unsigned int change, unsigned int new) \
{ \
unsigned int res; \
\
res = read_32bit_cp0_register(register); \
res &= ~change; \
res |= (new & change); \
+ if (change) \
write_32bit_cp0_register(register, res); \
\
return res; \
Index: softirq.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips64/softirq.h,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- softirq.h 2001/09/26 16:48:21 1.3
+++ softirq.h 2001/10/27 17:28:55 1.4
@@ -39,18 +39,4 @@
#define in_softirq() (local_bh_count(smp_processor_id()) != 0)
-extern inline void __cpu_raise_softirq(int cpu, int nr)
-{
- unsigned int *m = (unsigned int *) &softirq_pending(cpu);
- unsigned int temp;
-
- __asm__ __volatile__(
- "1:\tll\t%0, %1\t\t\t# __cpu_raise_softirq\n\t"
- "or\t%0, %2\n\t"
- "sc\t%0, %1\n\t"
- "beqz\t%0, 1b"
- : "=&r" (temp), "=m" (*m)
- : "ir" (1UL << nr), "m" (*m));
-}
-
#endif /* _ASM_SOFTIRQ_H */
Index: system.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips64/system.h,v
retrieving revision 1.5
retrieving revision 1.6
diff -u -d -r1.5 -r1.6
--- system.h 2001/10/17 17:16:09 1.5
+++ system.h 2001/10/27 17:28:55 1.6
@@ -212,7 +212,7 @@
#define SWITCH_DO_LAZY_FPU \
if (prev->flags & PF_USEDFPU) { \
lazy_fpu_switch(prev, 0); \
- set_cp0_status(ST0_CU1, ~ST0_CU1); \
+ clear_cp0_status(ST0_CU1); \
prev->flags &= ~PF_USEDFPU; \
}
#else /* CONFIG_SMP */
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