Update of /cvsroot/linux-mips/linux/arch/mips64/mm
In directory usw-pr-cvs1:/tmp/cvs-serv20204/arch/mips64/mm
Modified Files:
r4xx0.c
Log Message:
Sync with OSS (except for sysmips, which is waiting to be tested first).
Index: r4xx0.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips64/mm/r4xx0.c,v
retrieving revision 1.5
retrieving revision 1.6
diff -u -d -r1.5 -r1.6
--- r4xx0.c 2001/10/11 23:06:13 1.5
+++ r4xx0.c 2001/10/27 17:28:54 1.6
@@ -330,7 +330,7 @@
"sd\t$0,-8(%0)\n\t"
".set\tat\n\t"
".set\treorder"
- : (page)
+ : "=r" (page)
: "0" (page), "I" (PAGE_SIZE), "i" (Create_Dirty_Excl_SD)
: "memory");
}
@@ -1907,7 +1907,7 @@
}
}
-static void local_flush_tlb_range(struct mm_struct *mm, unsigned long start,
+void local_flush_tlb_range(struct mm_struct *mm, unsigned long start,
unsigned long end)
{
if (CPU_CONTEXT(smp_processor_id(), mm) != 0) {
@@ -1957,7 +1957,7 @@
}
}
-static void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
+void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
{
if (CPU_CONTEXT(smp_processor_id(), vma->vm_mm) != 0) {
unsigned long flags;
@@ -2363,9 +2363,9 @@
printk("CPU revision is: %08x\n", read_32bit_cp0_register(CP0_PRID));
#ifdef CONFIG_MIPS_UNCACHED
- set_cp0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
+ change_cp0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
#else
- set_cp0_config(CONF_CM_CMASK, CONF_CM_CACHABLE_NONCOHERENT);
+ change_cp0_config(CONF_CM_CMASK, CONF_CM_CACHABLE_NONCOHERENT);
#endif /* UNCACHED */
probe_icache(config);
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