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linux-mips-commits
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From: James S. <jsi...@us...> - 2001-10-24 23:32:57
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Update of /cvsroot/linux-mips/linux/arch/mips/mm
In directory usw-pr-cvs1:/tmp/cvs-serv28848/arch/mips/mm
Modified Files:
c-tx39.c loadmmu.c tlb-r3k.c
Added Files:
c-tx49.c
Log Message:
Improved support for Toshiba TX39/TX49 series.
--- NEW FILE: c-tx49.c ---
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* r49xx.c: TX49 processor variant specific MMU/Cache routines.
*
* Copyright (C) 1996 David S. Miller (dm...@en...)
* Copyright (C) 1997, 1998, 1999, 2000 Ralf Baechle ra...@gn...
*
* Modified for R4300/TX49xx (Jun/2001)
* Copyright (C) 1999-2001 Toshiba Corporation
*
* To do:
*
* - this code is a overbloated pig
* - many of the bug workarounds are not efficient at all, but at
* least they are functional ...
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/mm.h>
#include <asm/bootinfo.h>
#include <asm/cpu.h>
#include <asm/io.h>
#include <asm/page.h>
#include <asm/pgtable.h>
#include <asm/system.h>
#include <asm/mmu_context.h>
/* Primary cache parameters. */
static int icache_size, dcache_size; /* Size in bytes */
#define ic_lsize mips_cpu.icache.linesz
#define dc_lsize mips_cpu.dcache.linesz
static unsigned long scache_size;
#include <asm/cacheops.h>
#include <asm/r4kcache.h>
#undef DEBUG_CACHE
/* TX49 does can not flush the line contains the CACHE insn itself... */
/* r4k_xxx routines are completely same as those in r4xx0.c */
/*
* If you think for one second that this stuff coming up is a lot
* of bulky code eating too many kernel cache lines. Think _again_.
*
* Consider:
* 1) Taken branches have a 3 cycle penalty on R4k
* 2) The branch itself is a real dead cycle on even R4600/R5000.
* 3) Only one of the following variants of each type is even used by
* the kernel based upon the cache parameters we detect at boot time.
*
* QED.
*/
static inline void r49_flush_cache_all_d16i32(void)
{
unsigned long flags, config;
__save_and_cli(flags);
blast_dcache16_wayLSB();
/* disable icache (set ICE#) */
config = read_32bit_cp0_register(CP0_CONFIG);
write_32bit_cp0_register(CP0_CONFIG, config|TX49_CONF_IC);
blast_icache32_wayLSB();
write_32bit_cp0_register(CP0_CONFIG, config);
__restore_flags(flags);
}
static inline void r49_flush_cache_all_d32i32(void)
{
unsigned long flags, config;
__save_and_cli(flags);
blast_dcache32_wayLSB();
/* disable icache (set ICE#) */
config = read_32bit_cp0_register(CP0_CONFIG);
write_32bit_cp0_register(CP0_CONFIG, config|TX49_CONF_IC);
blast_icache32_wayLSB();
write_32bit_cp0_register(CP0_CONFIG, config);
__restore_flags(flags);
}
static void r49_flush_cache_range_d16i32(struct mm_struct *mm,
unsigned long start,
unsigned long end)
{
if (mm->context != 0) {
unsigned long flags, config;
#ifdef DEBUG_CACHE
printk("crange[%d,%08lx,%08lx]", (int)mm->context, start, end);
#endif
__save_and_cli(flags);
blast_dcache16_wayLSB();
/* disable icache (set ICE#) */
config = read_32bit_cp0_register(CP0_CONFIG);
write_32bit_cp0_register(CP0_CONFIG, config|TX49_CONF_IC);
blast_icache32_wayLSB();
write_32bit_cp0_register(CP0_CONFIG, config);
__restore_flags(flags);
}
}
static void r49_flush_cache_range_d32i32(struct mm_struct *mm,
unsigned long start,
unsigned long end)
{
if (mm->context != 0) {
unsigned long flags, config;
#ifdef DEBUG_CACHE
printk("crange[%d,%08lx,%08lx]", (int)mm->context, start, end);
#endif
__save_and_cli(flags);
blast_dcache32_wayLSB();
/* disable icache (set ICE#) */
config = read_32bit_cp0_register(CP0_CONFIG);
write_32bit_cp0_register(CP0_CONFIG, config|TX49_CONF_IC);
blast_icache32_wayLSB();
write_32bit_cp0_register(CP0_CONFIG, config);
__restore_flags(flags);
}
}
/*
* On architectures like the Sparc, we could get rid of lines in
* the cache created only by a certain context, but on the MIPS
* (and actually certain Sparc's) we cannot.
*/
static void r49_flush_cache_mm_d16i32(struct mm_struct *mm)
{
if (mm->context != 0) {
#ifdef DEBUG_CACHE
printk("cmm[%d]", (int)mm->context);
#endif
r49_flush_cache_all_d16i32();
}
}
static void r49_flush_cache_mm_d32i32(struct mm_struct *mm)
{
if (mm->context != 0) {
#ifdef DEBUG_CACHE
printk("cmm[%d]", (int)mm->context);
#endif
r49_flush_cache_all_d32i32();
}
}
static void r49_flush_cache_page_d16i32(struct vm_area_struct *vma,
unsigned long page)
{
struct mm_struct *mm = vma->vm_mm;
unsigned long flags;
pgd_t *pgdp;
pmd_t *pmdp;
pte_t *ptep;
/*
* If ownes no valid ASID yet, cannot possibly have gotten
* this page into the cache.
*/
if (mm->context == 0)
return;
#ifdef DEBUG_CACHE
printk("cpage[%d,%08lx]", (int)mm->context, page);
#endif
__save_and_cli(flags);
page &= PAGE_MASK;
pgdp = pgd_offset(mm, page);
pmdp = pmd_offset(pgdp, page);
ptep = pte_offset(pmdp, page);
/*
* If the page isn't marked valid, the page cannot possibly be
* in the cache.
*/
if (!(pte_val(*ptep) & _PAGE_PRESENT))
goto out;
/*
* Doing flushes for another ASID than the current one is
* too difficult since stupid R4k caches do a TLB translation
* for every cache flush operation. So we do indexed flushes
* in that case, which doesn't overly flush the cache too much.
*/
if ((mm == current->active_mm) && (pte_val(*ptep) & _PAGE_VALID)) {
blast_dcache16_page(page);
} else {
/*
* Do indexed flush, too much work to get the (possible)
* tlb refills to work correctly.
*/
page = (KSEG0 + (page & (dcache_size - 1)));
blast_dcache16_page_indexed_wayLSB(page);
}
out:
__restore_flags(flags);
}
static void r49_flush_cache_page_d32i32(struct vm_area_struct *vma,
unsigned long page)
{
struct mm_struct *mm = vma->vm_mm;
unsigned long flags;
pgd_t *pgdp;
pmd_t *pmdp;
pte_t *ptep;
/*
* If ownes no valid ASID yet, cannot possibly have gotten
* this page into the cache.
*/
if (mm->context == 0)
return;
#ifdef DEBUG_CACHE
printk("cpage[%d,%08lx]", (int)mm->context, page);
#endif
__save_and_cli(flags);
page &= PAGE_MASK;
pgdp = pgd_offset(mm, page);
pmdp = pmd_offset(pgdp, page);
ptep = pte_offset(pmdp, page);
/*
* If the page isn't marked valid, the page cannot possibly be
* in the cache.
*/
if (!(pte_val(*ptep) & _PAGE_PRESENT))
goto out;
/*
* Doing flushes for another ASID than the current one is
* too difficult since stupid R4k caches do a TLB translation
* for every cache flush operation. So we do indexed flushes
* in that case, which doesn't overly flush the cache too much.
*/
if ((mm == current->active_mm) && (pte_val(*ptep) & _PAGE_VALID)) {
blast_dcache32_page(page);
} else {
/*
* Do indexed flush, too much work to get the (possible)
* tlb refills to work correctly.
*/
page = (KSEG0 + (page & (dcache_size - 1)));
blast_dcache32_page_indexed_wayLSB(page);
}
out:
__restore_flags(flags);
}
/* If the addresses passed to these routines are valid, they are
* either:
*
* 1) In KSEG0, so we can do a direct flush of the page.
* 2) In KSEG2, and since every process can translate those
* addresses all the time in kernel mode we can do a direct
* flush.
* 3) In KSEG1, no flush necessary.
*/
static void r4k_flush_page_to_ram_d16(struct page *page)
{
blast_dcache16_page((unsigned long)page_address(page));
}
static void r4k_flush_page_to_ram_d32(struct page *page)
{
blast_dcache32_page((unsigned long)page_address(page));
}
static void
r4k_flush_icache_range(unsigned long start, unsigned long end)
{
flush_cache_all();
}
/*
* Ok, this seriously sucks. We use them to flush a user page but don't
* know the virtual address, so we have to blast away the whole icache
* which is significantly more expensive than the real thing.
*/
static void
r4k_flush_icache_page(struct vm_area_struct *vma, struct page *page)
{
if (!(vma->vm_flags & VM_EXEC))
return;
flush_cache_all();
}
/*
* Writeback and invalidate the primary cache dcache before DMA.
*/
static void
r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size)
{
unsigned long end, a;
unsigned int flags;
if (size >= dcache_size) {
flush_cache_all();
} else {
__save_and_cli(flags);
a = addr & ~(dc_lsize - 1);
end = (addr + size) & ~(dc_lsize - 1);
while (1) {
flush_dcache_line(a); /* Hit_Writeback_Inv_D */
if (a == end) break;
a += dc_lsize;
}
__restore_flags(flags);
}
}
static void
r4k_dma_cache_inv(unsigned long addr, unsigned long size)
{
unsigned long end, a;
unsigned int flags;
if (size >= dcache_size) {
flush_cache_all();
} else {
__save_and_cli(flags);
a = addr & ~(dc_lsize - 1);
end = (addr + size) & ~(dc_lsize - 1);
while (1) {
flush_dcache_line(a); /* Hit_Writeback_Inv_D */
if (a == end) break;
a += dc_lsize;
}
__restore_flags(flags);
}
}
static void
r4k_dma_cache_wback(unsigned long addr, unsigned long size)
{
panic("r4k_dma_cache called - should not happen.\n");
}
/*
* While we're protected against bad userland addresses we don't care
* very much about what happens in that case. Usually a segmentation
* fault will dump the process later on anyway ...
*/
static void r4k_flush_cache_sigtramp(unsigned long addr)
{
protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
protected_flush_icache_line(addr & ~(ic_lsize - 1));
}
/* Detect and size the various r4k caches. */
static void __init probe_icache(unsigned long config)
{
icache_size = 1 << (12 + ((config >> 9) & 7));
ic_lsize = 16 << ((config >> 5) & 1);
printk("Primary instruction cache %dkb, linesize %d bytes.\n",
icache_size >> 10, ic_lsize);
}
static void __init probe_dcache(unsigned long config)
{
dcache_size = 1 << (12 + ((config >> 6) & 7));
dc_lsize = 16 << ((config >> 4) & 1);
printk("Primary data cache %dkb, linesize %d bytes.\n",
dcache_size >> 10, dc_lsize);
}
int mips_configk0 = -1; /* board-specific setup routine can override this */
void __init ld_mmu_tx49(void)
{
unsigned long config = read_32bit_cp0_register(CP0_CONFIG);
printk("CPU revision is: %08x\n", read_32bit_cp0_register(CP0_PRID));
if (mips_configk0 != -1)
change_cp0_config(CONF_CM_CMASK, mips_configk0);
else
#ifdef CONFIG_MIPS_UNCACHED
change_cp0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
#else
change_cp0_config(CONF_CM_CMASK, CONF_CM_CACHABLE_NONCOHERENT);
#endif
probe_icache(config);
probe_dcache(config);
if (mips_cpu.icache.ways == 0)
mips_cpu.icache.ways = 1;
if (mips_cpu.dcache.ways == 0)
mips_cpu.dcache.ways = 1;
mips_cpu.icache.sets =
icache_size / mips_cpu.icache.ways / mips_cpu.icache.linesz;
mips_cpu.dcache.sets =
dcache_size / mips_cpu.dcache.ways / mips_cpu.dcache.linesz;
switch(dc_lsize) {
case 16:
_clear_page = r4k_clear_page_d16;
_copy_page = r4k_copy_page_d16;
_flush_page_to_ram = r4k_flush_page_to_ram_d16;
_flush_cache_all = r49_flush_cache_all_d16i32;
_flush_cache_mm = r49_flush_cache_mm_d16i32;
_flush_cache_range = r49_flush_cache_range_d16i32;
_flush_cache_page = r49_flush_cache_page_d16i32;
break;
case 32:
_clear_page = r4k_clear_page_d32;
_copy_page = r4k_copy_page_d32;
_flush_page_to_ram = r4k_flush_page_to_ram_d32;
_flush_cache_all = r49_flush_cache_all_d32i32;
_flush_cache_mm = r49_flush_cache_mm_d32i32;
_flush_cache_range = r49_flush_cache_range_d32i32;
_flush_cache_page = r49_flush_cache_page_d32i32;
break;
}
___flush_cache_all = _flush_cache_all;
_flush_icache_page = r4k_flush_icache_page;
_dma_cache_wback_inv = r4k_dma_cache_wback_inv;
_dma_cache_wback = r4k_dma_cache_wback;
_dma_cache_inv = r4k_dma_cache_inv;
_flush_cache_sigtramp = r4k_flush_cache_sigtramp;
_flush_icache_range = r4k_flush_icache_range; /* Ouch */
__flush_cache_all();
}
Index: c-tx39.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/mm/c-tx39.c,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- c-tx39.c 2001/10/23 17:20:14 1.1
+++ c-tx39.c 2001/10/24 23:32:54 1.2
@@ -28,31 +28,27 @@
static unsigned long icache_size, dcache_size; /* Size in bytes */
extern long scache_size;
-#define icache_lsize 16 /* for all current cpu variants */
-#define dcache_lsize 4 /* for all current cpu variants */
+#define icache_lsize mips_cpu.icache.linesz
+#define dcache_lsize mips_cpu.dcache.linesz
#include <asm/r4kcache.h>
-static void tx39_flush_page_to_ram(struct page * page)
+extern int r3k_have_wired_reg; /* in r3k-tlb.c */
+
+static void tx39h_flush_page_to_ram(struct page * page)
{
}
-static void tx39_flush_icache_all(void)
+/* TX39H-style cache flush routines. */
+static void tx39h_flush_icache_all(void)
{
unsigned long start = KSEG0;
unsigned long end = (start + icache_size);
- unsigned long dummy = 0;
+ unsigned long flags, config;
- /* disable icache and stop streaming */
- __asm__ __volatile__(
- ".set\tnoreorder\n\t"
- "mfc0\t%0, $3\n\t"
- "xori\t%0, 32\n\t"
- "mtc0\t%0, $3\n\t"
- "j\t1f\n\t"
- "nop\n\t"
- "1:\t.set\treorder\n\t"
- : "+r"(dummy));
+ /* disable icache (set ICE#) */
+ __save_and_cli(flags);
+ config = read_32bit_cp0_register(CP0_CONF);
/* invalidate icache */
while (start < end) {
@@ -60,16 +56,196 @@
start += 0x200;
}
- /* enable icache */
- __asm__ __volatile__(
- ".set\tnoreorder\n\t"
- "mfc0\t%0, $3\n\t"
- "xori\t%0, 32\n\t"
- "mtc0\t%0, $3\n\t"
- ".set\treorder\n\t"
- : "+r"(dummy));
+ write_32bit_cp0_register(CP0_CONF, config);
+ __restore_flags(flags);
+}
+
+static void tx39h_dma_cache_wback_inv(unsigned long addr, unsigned long size)
+{
+ unsigned long end, a;
+ wbflush();
+
+ a = addr & ~(dcache_lsize - 1);
+ end = (addr + size) & ~(dcache_lsize - 1);
+ while (1) {
+ invalidate_dcache_line(a); /* Hit_Invalidate_D */
+ if (a == end) break;
+ a += dcache_lsize;
+ }
+}
+
+
+/* TX39H2,TX39H3 */
+static inline void tx39_flush_cache_all(void)
+{
+ unsigned long flags, config;
+
+ __save_and_cli(flags);
+ blast_dcache16_wayLSB();
+ /* disable icache (set ICE#) */
+ config = read_32bit_cp0_register(CP0_CONF);
+ write_32bit_cp0_register(CP0_CONF, config&~TX39_CONF_ICE);
+ blast_icache16_wayLSB();
+ write_32bit_cp0_register(CP0_CONF, config);
+ __restore_flags(flags);
+}
+
+static void tx39_flush_cache_mm(struct mm_struct *mm)
+{
+ if(mm->context != 0) {
+#ifdef DEBUG_CACHE
+ printk("cmm[%d]", (int)mm->context);
+#endif
+ tx39_flush_cache_all();
+ }
+}
+
+static void tx39_flush_cache_range(struct mm_struct *mm,
+ unsigned long start,
+ unsigned long end)
+{
+ if(mm->context != 0) {
+ unsigned long flags, config;
+
+#ifdef DEBUG_CACHE
+ printk("crange[%d,%08lx,%08lx]", (int)mm->context, start, end);
+#endif
+ __save_and_cli(flags);
+ blast_dcache16_wayLSB();
+ /* disable icache (set ICE#) */
+ config = read_32bit_cp0_register(CP0_CONF);
+ write_32bit_cp0_register(CP0_CONF, config&~TX39_CONF_ICE);
+ blast_icache16_wayLSB();
+ write_32bit_cp0_register(CP0_CONF, config);
+ __restore_flags(flags);
+ }
+}
+
+static void tx39_flush_cache_page(struct vm_area_struct *vma,
+ unsigned long page)
+{
+ struct mm_struct *mm = vma->vm_mm;
+ unsigned long flags;
+ pgd_t *pgdp;
+ pmd_t *pmdp;
+ pte_t *ptep;
+
+ /*
+ * If ownes no valid ASID yet, cannot possibly have gotten
+ * this page into the cache.
+ */
+ if(mm->context == 0)
+ return;
+
+#ifdef DEBUG_CACHE
+ printk("cpage[%d,%08lx]", (int)mm->context, page);
+#endif
+ __save_and_cli(flags);
+ page &= PAGE_MASK;
+ pgdp = pgd_offset(mm, page);
+ pmdp = pmd_offset(pgdp, page);
+ ptep = pte_offset(pmdp, page);
+
+ /*
+ * If the page isn't marked valid, the page cannot possibly be
+ * in the cache.
+ */
+ if(!(pte_val(*ptep) & _PAGE_PRESENT))
+ goto out;
+
+ /*
+ * Doing flushes for another ASID than the current one is
+ * too difficult since stupid R4k caches do a TLB translation
+ * for every cache flush operation. So we do indexed flushes
+ * in that case, which doesn't overly flush the cache too much.
+ */
+ if((mm == current->active_mm) && (pte_val(*ptep) & _PAGE_VALID)) {
+ blast_dcache16_page(page);
+ } else {
+ /*
+ * Do indexed flush, too much work to get the (possible)
+ * tlb refills to work correctly.
+ */
+ page = (KSEG0 + (page & (dcache_size - 1)));
+ blast_dcache16_page_indexed_wayLSB(page);
+ }
+out:
+ __restore_flags(flags);
+}
+
+static void tx39_flush_page_to_ram(struct page * page)
+{
+ blast_dcache16_page((unsigned long)page_address(page));
+}
+
+static void tx39_flush_icache_range(unsigned long start, unsigned long end)
+{
+ flush_cache_all();
+}
+
+static void tx39_flush_icache_page(struct vm_area_struct *vma, struct page *page)
+{
+ if (!(vma->vm_flags & VM_EXEC))
+ return;
+
+ flush_cache_all();
+}
+
+static void tx39_dma_cache_wback_inv(unsigned long addr, unsigned long size)
+{
+ unsigned long end, a;
+
+ if (size >= dcache_size) {
+ flush_cache_all();
+ } else {
+ a = addr & ~(dcache_lsize - 1);
+ end = (addr + size) & ~(dcache_lsize - 1);
+ while (1) {
+ flush_dcache_line(a); /* Hit_Writeback_Inv_D */
+ if (a == end) break;
+ a += dcache_lsize;
+ }
+ }
}
+static void tx39_dma_cache_inv(unsigned long addr, unsigned long size)
+{
+ unsigned long end, a;
+
+ if (size >= dcache_size) {
+ flush_cache_all();
+ } else {
+ a = addr & ~(dcache_lsize - 1);
+ end = (addr + size) & ~(dcache_lsize - 1);
+ while (1) {
+ invalidate_dcache_line(a); /* Hit_Invalidate_D */
+ if (a == end) break;
+ a += dcache_lsize;
+ }
+ }
+}
+
+static void tx39_dma_cache_wback(unsigned long addr, unsigned long size)
+{
+ panic("tx39_dma_cache called - should not happen.\n");
+}
+
+static void tx39_flush_cache_sigtramp(unsigned long addr)
+{
+ unsigned long config;
+ unsigned int flags;
+
+ __save_and_cli(flags);
+ protected_writeback_dcache_line(addr & ~(dcache_lsize - 1));
+
+ /* disable icache (set ICE#) */
+ config = read_32bit_cp0_register(CP0_CONF);
+ write_32bit_cp0_register(CP0_CONF, config&~TX39_CONF_ICE);
+ protected_flush_icache_line(addr & ~(icache_lsize - 1));
+ write_32bit_cp0_register(CP0_CONF, config);
+ __restore_flags(flags);
+}
+
static __init void tx39_probe_cache(void)
{
unsigned long config;
@@ -78,6 +254,19 @@
icache_size = 1 << (10 + ((config >> 19) & 3));
dcache_size = 1 << (10 + ((config >> 16) & 3));
+
+ icache_lsize = 16;
+ switch (mips_cpu.cputype) {
+ case CPU_TX3912:
+ dcache_lsize = 4;
+ break;
+ case CPU_TX3922:
+ case CPU_TX3927:
+ case CPU_TX39XX:
+ default:
+ dcache_lsize = 16;
+ break;
+ }
}
void __init ld_mmu_tx39(void)
@@ -95,18 +284,55 @@
tx39_probe_cache();
- _flush_cache_all = tx39_flush_icache_all;
- ___flush_cache_all = tx39_flush_icache_all;
- _flush_cache_mm = (void *) tx39_flush_icache_all;
- _flush_cache_range = (void *) tx39_flush_icache_all;
- _flush_cache_page = (void *) tx39_flush_icache_all;
- _flush_cache_sigtramp = (void *) tx39_flush_icache_all;
- _flush_page_to_ram = tx39_flush_page_to_ram;
- _flush_icache_page = (void *) tx39_flush_icache_all;
- _flush_icache_range = (void *) tx39_flush_icache_all;
+ switch (mips_cpu.cputype) {
+ case CPU_TX3912:
+ /* TX39/H core (writethru direct-map cache) */
+ _flush_cache_all = tx39h_flush_icache_all;
+ ___flush_cache_all = tx39h_flush_icache_all;
+ _flush_cache_mm = (void *) tx39h_flush_icache_all;
+ _flush_cache_range = (void *) tx39h_flush_icache_all;
+ _flush_cache_page = (void *) tx39h_flush_icache_all;
+ _flush_cache_sigtramp = (void *) tx39h_flush_icache_all;
+ _flush_page_to_ram = tx39h_flush_page_to_ram;
+ _flush_icache_page = (void *) tx39h_flush_icache_all;
+ _flush_icache_range = (void *) tx39h_flush_icache_all;
- /* This seems to be wrong for a R4k-style caches -- Ralf */
- // _dma_cache_wback_inv = r3k_dma_cache_wback_inv;
+ _dma_cache_wback_inv = tx39h_dma_cache_wback_inv;
+ break;
+
+ case CPU_TX3922:
+ case CPU_TX3927:
+ default:
+ /* TX39/H2,H3 core (writeback 2way-set-associative cache) */
+ r3k_have_wired_reg = 1;
+ set_wired (0); /* set 8 on reset... */
+ /* board-dependent init code may set WBON */
+
+ _flush_cache_all = tx39_flush_cache_all;
+ ___flush_cache_all = tx39_flush_cache_all;
+ _flush_cache_mm = tx39_flush_cache_mm;
+ _flush_cache_range = tx39_flush_cache_range;
+ _flush_cache_page = tx39_flush_cache_page;
+ _flush_cache_sigtramp = tx39_flush_cache_sigtramp;
+ _flush_page_to_ram = tx39_flush_page_to_ram;
+ _flush_icache_page = tx39_flush_icache_page;
+ _flush_icache_range = tx39_flush_icache_range;
+
+ _dma_cache_wback_inv = tx39_dma_cache_wback_inv;
+ _dma_cache_wback = tx39_dma_cache_wback;
+ _dma_cache_inv = tx39_dma_cache_inv;
+
+ break;
+ }
+
+ if (mips_cpu.icache.ways == 0)
+ mips_cpu.icache.ways = 1;
+ if (mips_cpu.dcache.ways == 0)
+ mips_cpu.dcache.ways = 1;
+ mips_cpu.icache.sets =
+ icache_size / mips_cpu.icache.ways / mips_cpu.icache.linesz;
+ mips_cpu.dcache.sets =
+ dcache_size / mips_cpu.dcache.ways / mips_cpu.dcache.linesz;
printk("Primary instruction cache %dkb, linesize %d bytes\n",
(int) (icache_size >> 10), (int) icache_lsize);
Index: loadmmu.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/mm/loadmmu.c,v
retrieving revision 1.6
retrieving revision 1.7
diff -u -d -r1.6 -r1.7
--- loadmmu.c 2001/10/23 17:20:14 1.6
+++ loadmmu.c 2001/10/24 23:32:54 1.7
@@ -40,6 +40,8 @@
extern void ld_mmu_r23000(void);
extern void ld_mmu_r4xx0(void);
+extern void ld_mmu_tx39(void);
+extern void ld_mmu_tx49(void);
extern void ld_mmu_r5432(void);
extern void ld_mmu_r6000(void);
extern void ld_mmu_rm7k(void);
@@ -67,6 +69,10 @@
ld_mmu_r5432();
r4k_tlb_init();
#endif
+#if defined(CONFIG_CPU_TX49XX)
+ ld_mmu_tx49();
+ r4k_tlb_init();
+#endif
#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
ld_mmu_mips32();
@@ -80,10 +86,20 @@
case CPU_R3081E:
ld_mmu_r23000();
r3k_tlb_init();
-
+ break;
+ case CPU_TX3912:
+ case CPU_TX3922:
+ case CPU_TX3927:
+ case CPU_TX39XX:
+ ld_mmu_tx39();
+ r3k_tlb_init();
+ break;
+#endif
+#ifdef CONFIG_CPU_TX39XX
case CPU_TX3912:
case CPU_TX3922:
case CPU_TX3927:
+ case CPU_TX39XX:
ld_mmu_tx39();
r3k_tlb_init();
break;
Index: tlb-r3k.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/mm/tlb-r3k.c,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -d -r1.2 -r1.3
--- tlb-r3k.c 2001/10/23 17:20:14 1.2
+++ tlb-r3k.c 2001/10/24 23:32:54 1.3
@@ -27,6 +27,10 @@
#undef DEBUG_TLB
+#ifdef CONFIG_CPU_TX39XX
+int r3k_have_wired_reg = 0; /* should be in mips_cpu? */
+#endif
+
/* TLB operations. */
void local_flush_tlb_all(void)
{
@@ -41,7 +45,12 @@
save_and_cli(flags);
old_ctx = (get_entryhi() & 0xfc0);
write_32bit_cp0_register(CP0_ENTRYLO0, 0);
- for (entry = 8; entry < mips_cpu.tlbsize; entry++) {
+#ifdef CONFIG_CPU_TX39XX
+ entry = r3k_have_wired_reg ? get_wired() : 8;
+#else
+ entry = 8;
+#endif
+ for (; entry < mips_cpu.tlbsize; entry++) {
write_32bit_cp0_register(CP0_INDEX, entry << 8);
write_32bit_cp0_register(CP0_ENTRYHI, ((entry | 0x80000) << 12));
__asm__ __volatile__("tlbwi");
@@ -193,6 +202,40 @@
unsigned long old_ctx;
static unsigned long wired = 0;
+#ifdef CONFIG_CPU_TX39XX
+ if (r3k_have_wired_reg) {
+ unsigned long old_pagemask;
+ unsigned long w;
+
+#ifdef DEBUG_TLB
+ printk("[tlbwired]");
+ printk("ently lo0 %8x, hi %8x\n, pagemask %8x\n",
+ entrylo0, entryhi, pagemask);
+#endif
+ save_and_cli(flags);
+ /* Save old context and create impossible VPN2 value */
+ old_ctx = (get_entryhi() & 0xff);
+ old_pagemask = get_pagemask();
+ w = get_wired();
+ set_wired (w + 1);
+ if (get_wired() != w + 1) {
+ printk("[tlbwired] No WIRED reg?\n");
+ return;
+ }
+ set_index (w << 8);
+ set_pagemask (pagemask);
+ set_entryhi(entryhi);
+ set_entrylo0(entrylo0);
+ tlb_write_indexed();
+
+ set_entryhi(old_ctx);
+ set_pagemask (old_pagemask);
+ local_flush_tlb_all();
+ restore_flags(flags);
+ return;
+ }
+#endif
+
if (wired < 8) {
__save_and_cli(flags);
old_ctx = get_entryhi() & 0xfc0;
|
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