Update of /cvsroot/linux-mips/linux/arch/mips/kernel
In directory usw-pr-cvs1:/tmp/cvs-serv28848/arch/mips/kernel
Modified Files:
gdb-low.S setup.c traps.c
Log Message:
Improved support for Toshiba TX39/TX49 series.
Index: gdb-low.S
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/kernel/gdb-low.S,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- gdb-low.S 2001/07/19 17:14:54 1.1
+++ gdb-low.S 2001/10/24 23:32:54 1.2
@@ -304,7 +304,7 @@
lw v1,GDB_FR_REG3(sp)
lw v0,GDB_FR_REG2(sp)
lw $1,GDB_FR_REG1(sp)
-#ifdef CONFIG_CPU_R3000
+#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
lw k0, GDB_FR_EPC(sp)
lw sp, GDB_FR_REG29(sp) /* Deallocate stack */
jr k0
Index: setup.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/kernel/setup.c,v
retrieving revision 1.22
retrieving revision 1.23
diff -u -d -r1.22 -r1.23
--- setup.c 2001/10/22 19:16:44 1.22
+++ setup.c 2001/10/24 23:32:54 1.23
@@ -203,6 +203,12 @@
mips_cpu.dcache.ways = 2;
#endif
break;
+ case PRID_IMP_R4300:
+ mips_cpu.cputype = CPU_R4300;
+ mips_cpu.isa_level = MIPS_CPU_ISA_III;
+ mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR;
+ mips_cpu.tlbsize = 32;
+ break;
case PRID_IMP_R4600:
mips_cpu.cputype = CPU_R4600;
mips_cpu.isa_level = MIPS_CPU_ISA_III;
@@ -237,9 +243,23 @@
mips_cpu.tlbsize = 64;
break;
case PRID_REV_TX3927:
- mips_cpu.cputype = CPU_TX3927;
+ case PRID_REV_TX3927B:
+ /* check core-mode */
+ if ((*(volatile u32 *)0xfffee004 >> 16) == 0x3927)
+ mips_cpu.cputype = CPU_TX3927;
+ else
+ mips_cpu.cputype = CPU_TX39XX;
mips_cpu.tlbsize = 64;
+ mips_cpu.icache.ways = 2;
+ mips_cpu.dcache.ways = 2;
break;
+ case PRID_REV_TX39H3TEG:
+ /* support core-mode only */
+ mips_cpu.cputype = CPU_TX39XX;
+ mips_cpu.tlbsize = 32;
+ mips_cpu.icache.ways = 2;
+ mips_cpu.dcache.ways = 2;
+ break;
default:
mips_cpu.cputype = CPU_UNKNOWN;
break;
@@ -252,6 +272,15 @@
MIPS_CPU_32FPR;
mips_cpu.tlbsize = 48;
break;
+ case PRID_IMP_TX49:
+ mips_cpu.cputype = CPU_TX49XX;
+ mips_cpu.isa_level = MIPS_CPU_ISA_III;
+ mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU |
+ MIPS_CPU_32FPR;
+ mips_cpu.tlbsize = 48;
+ mips_cpu.icache.ways = 4;
+ mips_cpu.dcache.ways = 4;
+ break;
case PRID_IMP_R5000:
mips_cpu.cputype = CPU_R5000;
mips_cpu.isa_level = MIPS_CPU_ISA_IV;
@@ -872,6 +901,12 @@
{
unsigned long cfg = read_32bit_cp0_register(CP0_CONF);
write_32bit_cp0_register(CP0_CONF, cfg|CONF_HALT);
+}
+
+void r39xx_wait(void)
+{
+ unsigned long cfg = read_32bit_cp0_register(CP0_CONF);
+ write_32bit_cp0_register(CP0_CONF, cfg|TX39_CONF_HALT);
}
void r4k_wait(void)
Index: traps.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/kernel/traps.c,v
retrieving revision 1.21
retrieving revision 1.22
diff -u -d -r1.21 -r1.22
--- traps.c 2001/10/23 17:20:14 1.21
+++ traps.c 2001/10/24 23:32:54 1.22
@@ -695,6 +695,14 @@
return;
bad_cid:
+#ifndef CONFIG_CPU_HAS_LLSC
+ switch (mips_cpu.cputype) {
+ case CPU_TX3927:
+ case CPU_TX39XX:
+ do_ri(regs);
+ return;
+ }
+#endif
compute_return_epc(regs);
force_sig(SIGILL, current);
}
@@ -956,6 +964,7 @@
case CPU_TX3912:
case CPU_TX3922:
case CPU_TX3927:
+ case CPU_TX39XX:
save_fp_context = _save_fp_context;
restore_fp_context = _restore_fp_context;
memcpy((void *)(KSEG0 + 0x80), &except_vec3_generic, 0x80);
@@ -964,6 +973,10 @@
case CPU_UNKNOWN:
default:
panic("Unknown CPU type");
+ }
+ if (!(mips_cpu.options & MIPS_CPU_FPU)) {
+ save_fp_context = fpu_emulator_save_context;
+ restore_fp_context = fpu_emulator_restore_context;
}
flush_icache_range(KSEG0, KSEG0 + 0x200);
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