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linux-mips-commits
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From: James S. <jsi...@us...> - 2001-10-11 20:45:29
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Update of /cvsroot/linux-mips/linux/arch/mips/ddb5xxx/ddb5477
In directory usw-pr-cvs1:/tmp/cvs-serv14020/arch/mips/ddb5xxx/ddb5477
Modified Files:
Makefile irq.c irq_5477.c pci.c pci_ops.c setup.c
Log Message:
Update debug crapola.
Index: Makefile
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/ddb5xxx/ddb5477/Makefile,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -d -r1.2 -r1.3
--- Makefile 2001/10/05 21:24:19 1.2
+++ Makefile 2001/10/11 20:45:26 1.3
@@ -15,7 +15,7 @@
obj-y += int-handler.o irq.o irq_5477.o setup.o pci.o pci_ops.o
-obj-$(CONFIG_LL_DEBUG) += debug.o
+obj-$(CONFIG_DEBUG) += debug.o
obj-$(CONFIG_REMOTE_DEBUG) += kgdb_io.o
include $(TOPDIR)/Rules.make
Index: irq.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/ddb5xxx/ddb5477/irq.c,v
retrieving revision 1.6
retrieving revision 1.7
diff -u -d -r1.6 -r1.7
--- irq.c 2001/09/07 18:43:41 1.6
+++ irq.c 2001/10/11 20:45:26 1.7
@@ -18,10 +18,10 @@
#include <asm/system.h>
#include <asm/mipsregs.h>
+#include <asm/debug.h>
+
#include <asm/ddb5xxx/ddb5xxx.h>
-/* [jsun] sooner or later we should move this debug stuff to MIPS common */
-#include <asm/ddb5xxx/debug.h>
/*
* IRQ mapping
@@ -76,7 +76,7 @@
void
ddb5477_irq_setup(void)
{
- MIPS_DEBUG(printk("ddb5477_irq_setup invoked.\n"));
+ db_run(printk("ddb5477_irq_setup invoked.\n"));
/* by default, we disable all interrupts and route all vrc5477
* interrupts to pin 0 (irq 2) */
@@ -141,13 +141,13 @@
u32 bitmask;
u32 i;
- MIPS_ASSERT(ddb_in32(DDB_INT2STAT) == 0);
- MIPS_ASSERT(ddb_in32(DDB_INT3STAT) == 0);
- MIPS_ASSERT(ddb_in32(DDB_INT4STAT) == 0);
- MIPS_ASSERT(ddb_in32(DDB_NMISTAT) == 0);
+ db_assert(ddb_in32(DDB_INT2STAT) == 0);
+ db_assert(ddb_in32(DDB_INT3STAT) == 0);
+ db_assert(ddb_in32(DDB_INT4STAT) == 0);
+ db_assert(ddb_in32(DDB_NMISTAT) == 0);
if (ddb_in32(DDB_INT1STAT) != 0) {
-#if defined(CONFIG_LL_DEBUG)
+#if defined(CONFIG_DEBUG)
vrc5477_show_int_regs();
#endif
panic("error interrupt has happened.\n");
Index: irq_5477.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/ddb5xxx/ddb5477/irq_5477.c,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -d -r1.1.1.1 -r1.2
--- irq_5477.c 2001/06/22 02:29:31 1.1.1.1
+++ irq_5477.c 2001/10/11 20:45:26 1.2
@@ -23,10 +23,9 @@
#include <linux/types.h>
#include <linux/ptrace.h>
-#include <asm/ddb5xxx/ddb5xxx.h>
+#include <asm/debug.h>
-/* [jsun] sooner or later we should move this debug stuff to MIPS common */
-#include <asm/ddb5xxx/debug.h>
+#include <asm/ddb5xxx/ddb5xxx.h>
/* number of total irqs supported by Vrc5477 */
#define NUM_5477_IRQ 32
@@ -37,9 +36,9 @@
static void
vrc5477_irq_enable(unsigned int irq)
{
- MIPS_ASSERT(vrc5477_irq_base != -1);
- MIPS_ASSERT(irq >= vrc5477_irq_base);
- MIPS_ASSERT(irq < vrc5477_irq_base+ NUM_5477_IRQ);
+ db_assert(vrc5477_irq_base != -1);
+ db_assert(irq >= vrc5477_irq_base);
+ db_assert(irq < vrc5477_irq_base+ NUM_5477_IRQ);
ll_vrc5477_irq_enable(irq - vrc5477_irq_base);
}
@@ -47,9 +46,9 @@
static void
vrc5477_irq_disable(unsigned int irq)
{
- MIPS_ASSERT(vrc5477_irq_base != -1);
- MIPS_ASSERT(irq >= vrc5477_irq_base);
- MIPS_ASSERT(irq < vrc5477_irq_base + NUM_5477_IRQ);
+ db_assert(vrc5477_irq_base != -1);
+ db_assert(irq >= vrc5477_irq_base);
+ db_assert(irq < vrc5477_irq_base + NUM_5477_IRQ);
ll_vrc5477_irq_disable(irq - vrc5477_irq_base);
}
@@ -65,9 +64,9 @@
static void
vrc5477_irq_ack(unsigned int irq)
{
- MIPS_ASSERT(vrc5477_irq_base != -1);
- MIPS_ASSERT(irq >= vrc5477_irq_base);
- MIPS_ASSERT(irq < vrc5477_irq_base+ NUM_5477_IRQ);
+ db_assert(vrc5477_irq_base != -1);
+ db_assert(irq >= vrc5477_irq_base);
+ db_assert(irq < vrc5477_irq_base+ NUM_5477_IRQ);
/* clear the interrupt bit */
/* some irqs require the driver to clear the sources */
@@ -82,9 +81,9 @@
static void
vrc5477_irq_end(unsigned int irq)
{
- MIPS_ASSERT(vrc5477_irq_base != -1);
- MIPS_ASSERT(irq >= vrc5477_irq_base);
- MIPS_ASSERT(irq < vrc5477_irq_base + NUM_5477_IRQ);
+ db_assert(vrc5477_irq_base != -1);
+ db_assert(irq >= vrc5477_irq_base);
+ db_assert(irq < vrc5477_irq_base + NUM_5477_IRQ);
ll_vrc5477_irq_enable( irq - vrc5477_irq_base);
}
@@ -119,8 +118,8 @@
int vrc5477_irq_to_irq(int irq)
{
- MIPS_ASSERT(irq >= 0);
- MIPS_ASSERT(irq < NUM_5477_IRQ);
+ db_assert(irq >= 0);
+ db_assert(irq < NUM_5477_IRQ);
return irq + vrc5477_irq_base;
}
@@ -131,10 +130,10 @@
u32 reg_bitmask;
u32 reg_index;
- MIPS_ASSERT(vrc5477_irq >= 0);
- MIPS_ASSERT(vrc5477_irq < NUM_5477_IRQ);
- MIPS_ASSERT(ip >= 0);
- MIPS_ASSERT((ip < 5) || (ip == 6));
+ db_assert(vrc5477_irq >= 0);
+ db_assert(vrc5477_irq < NUM_5477_IRQ);
+ db_assert(ip >= 0);
+ db_assert((ip < 5) || (ip == 6));
reg_index = DDB_INTCTRL0 + vrc5477_irq/8*4;
reg_value = ddb_in32(reg_index);
@@ -150,13 +149,13 @@
u32 reg_bitmask;
u32 reg_index;
- MIPS_ASSERT(vrc5477_irq >= 0);
- MIPS_ASSERT(vrc5477_irq < NUM_5477_IRQ);
+ db_assert(vrc5477_irq >= 0);
+ db_assert(vrc5477_irq < NUM_5477_IRQ);
reg_index = DDB_INTCTRL0 + vrc5477_irq/8*4;
reg_value = ddb_in32(reg_index);
reg_bitmask = 8 << (vrc5477_irq % 8 * 4);
- MIPS_ASSERT((reg_value & reg_bitmask) == 0);
+ db_assert((reg_value & reg_bitmask) == 0);
ddb_out32(reg_index, reg_value | reg_bitmask);
}
@@ -166,14 +165,14 @@
u32 reg_bitmask;
u32 reg_index;
- MIPS_ASSERT(vrc5477_irq >= 0);
- MIPS_ASSERT(vrc5477_irq < NUM_5477_IRQ);
+ db_assert(vrc5477_irq >= 0);
+ db_assert(vrc5477_irq < NUM_5477_IRQ);
reg_index = DDB_INTCTRL0 + vrc5477_irq/8*4;
reg_value = ddb_in32(reg_index);
reg_bitmask = 8 << (vrc5477_irq % 8 * 4);
/* we assert that the interrupt is enabled (perhaps over-zealous) */
- MIPS_ASSERT( (reg_value & reg_bitmask) != 0);
+ db_assert( (reg_value & reg_bitmask) != 0);
ddb_out32(reg_index, reg_value & ~reg_bitmask);
}
Index: pci.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/ddb5xxx/ddb5477/pci.c,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- pci.c 2001/09/26 17:12:37 1.3
+++ pci.c 2001/10/11 20:45:26 1.4
@@ -1,12 +1,25 @@
+/*
+ * PCI code for DDB5477.
+ *
+ * Copyright (C) 2001 MontaVista Software Inc.
+ * Author: Jun Sun, js...@mv... or js...@ju...
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ */
+
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/types.h>
#include <linux/pci.h>
#include <asm/pci_channel.h>
+#include <asm/debug.h>
#include <asm/ddb5xxx/ddb5xxx.h>
-#include <asm/ddb5xxx/debug.h>
static struct resource extpci_io_resource = {
"ext pci IO space",
@@ -104,8 +117,8 @@
pci_for_each_dev(dev) {
slot_num = PCI_SLOT(dev->devfn);
- MIPS_ASSERT(slot_num < MAX_SLOT_NUM);
- MIPS_ASSERT(irq_map[slot_num] != 0xff);
+ db_assert(slot_num < MAX_SLOT_NUM);
+ db_assert(irq_map[slot_num] != 0xff);
pci_write_config_byte(dev,
PCI_INTERRUPT_LINE,
@@ -114,7 +127,7 @@
}
}
-#if defined(CONFIG_LL_DEBUG)
+#if defined(CONFIG_DEBUG)
extern void jsun_scan_pci_bus(void);
extern void jsun_assign_pci_resource(void);
#endif
Index: pci_ops.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/ddb5xxx/ddb5477/pci_ops.c,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -d -r1.1.1.1 -r1.2
--- pci_ops.c 2001/06/22 02:29:31 1.1.1.1
+++ pci_ops.c 2001/10/11 20:45:26 1.2
@@ -26,7 +26,8 @@
#include <linux/types.h>
#include <asm/addrspace.h>
-#include <asm/ddb5xxx/debug.h>
+#include <asm/debug.h>
+
#include <asm/ddb5xxx/ddb5xxx.h>
/*
@@ -76,10 +77,10 @@
// if (slot_num == 4) slot_num = 0;
/* minimum pdar (window) size is 2MB */
- MIPS_ASSERT(swap->config_size >= (2 << 20));
+ db_assert(swap->config_size >= (2 << 20));
- MIPS_ASSERT(slot_num < (1 << 5));
- MIPS_ASSERT(bus < (1 << 8));
+ db_assert(slot_num < (1 << 5));
+ db_assert(bus < (1 << 8));
/* backup registers */
swap->pdar_backup = ddb_in32(swap->pdar);
@@ -115,7 +116,7 @@
virt_addr = KSEG1ADDR(swap->config_base + pci_addr);
pciinit_offset = 0;
} else {
- MIPS_ASSERT( (pci_addr & (swap->config_size - 1)) == 0);
+ db_assert( (pci_addr & (swap->config_size - 1)) == 0);
virt_addr = KSEG1ADDR(swap->config_base);
pciinit_offset = pci_addr;
}
@@ -142,13 +143,13 @@
u32 bus, slot_num, func_num;
u32 base;
- MIPS_ASSERT((where & 3) == 0);
- MIPS_ASSERT(where < (1 << 8));
+ db_assert((where & 3) == 0);
+ db_assert(where < (1 << 8));
/* check if the bus is top-level */
if (dev->bus->parent != NULL) {
bus = dev->bus->number;
- MIPS_ASSERT(bus != 0);
+ db_assert(bus != 0);
} else {
bus = 0;
}
@@ -169,7 +170,7 @@
int status;
u32 result;
- MIPS_ASSERT((where & 1) == 0);
+ db_assert((where & 1) == 0);
status = read_config_dword(swap, dev, where & ~3, &result);
if (where & 2) result >>= 16;
@@ -200,13 +201,13 @@
u32 bus, slot_num, func_num;
u32 base;
- MIPS_ASSERT((where & 3) == 0);
- MIPS_ASSERT(where < (1 << 8));
+ db_assert((where & 3) == 0);
+ db_assert(where < (1 << 8));
/* check if the bus is top-level */
if (dev->bus->parent != NULL) {
bus = dev->bus->number;
- MIPS_ASSERT(bus != 0);
+ db_assert(bus != 0);
} else {
bus = 0;
}
@@ -227,7 +228,7 @@
int status, shift=0;
u32 result;
- MIPS_ASSERT((where & 1) == 0);
+ db_assert((where & 1) == 0);
status = read_config_dword(swap, dev, where & ~3, &result);
if (status != PCIBIOS_SUCCESSFUL) return status;
@@ -303,7 +304,7 @@
iopci_write_config_dword
};
-#if defined(CONFIG_LL_DEBUG)
+#if defined(CONFIG_DEBUG)
void jsun_scan_pci_bus(void)
{
struct pci_bus bus;
@@ -332,26 +333,26 @@
int i;
dev.devfn = devfn;
- MIPS_VERIFY(pci_read_config_dword(&dev, 0, &temp),
- == PCIBIOS_SUCCESSFUL);
+ db_verify(pci_read_config_dword(&dev, 0, &temp),
+ == PCIBIOS_SUCCESSFUL);
if (temp == 0xffffffff) continue;
printk("slot %d: (addr %d) \n", devfn/8, 11+devfn/8);
/* verify read word and byte */
- MIPS_VERIFY(pci_read_config_word(&dev, 2, &temp16),
- == PCIBIOS_SUCCESSFUL);
- MIPS_ASSERT(temp16 == (temp >> 16));
- MIPS_VERIFY(pci_read_config_byte(&dev, 3, &temp8),
- == PCIBIOS_SUCCESSFUL);
- MIPS_ASSERT(temp8 == (temp >> 24));
- MIPS_VERIFY(pci_read_config_byte(&dev, 1, &temp8),
- == PCIBIOS_SUCCESSFUL);
- MIPS_ASSERT(temp8 == ((temp >> 8) & 0xff));
+ db_verify(pci_read_config_word(&dev, 2, &temp16),
+ == PCIBIOS_SUCCESSFUL);
+ db_assert(temp16 == (temp >> 16));
+ db_verify(pci_read_config_byte(&dev, 3, &temp8),
+ == PCIBIOS_SUCCESSFUL);
+ db_assert(temp8 == (temp >> 24));
+ db_verify(pci_read_config_byte(&dev, 1, &temp8),
+ == PCIBIOS_SUCCESSFUL);
+ db_assert(temp8 == ((temp >> 8) & 0xff));
for (i=0; i < 16; i++) {
- MIPS_VERIFY(pci_read_config_dword(&dev, i*4, &temp),
- == PCIBIOS_SUCCESSFUL);
+ db_verify(pci_read_config_dword(&dev, i*4, &temp),
+ == PCIBIOS_SUCCESSFUL);
printk("\t%08X", temp);
if ((i%4) == 3) printk("\n");
}
@@ -374,7 +375,7 @@
/* for slot 5 (ext pci 1) eepro card */
dev.devfn = 5*8;
pci_read_config_dword(&dev, 0, &temp);
- MIPS_ASSERT(temp == 0x12298086);
+ db_assert(temp == 0x12298086);
pci_write_config_dword(&dev, PCI_BASE_ADDRESS_0, DDB_PCI0_MEM_BASE);
pci_write_config_dword(&dev, PCI_BASE_ADDRESS_1, 0);
@@ -396,7 +397,7 @@
/* for slot 4 on board ether chip */
dev.devfn = 4*8;
pci_read_config_dword(&dev, 0, &temp);
- MIPS_ASSERT(temp == 0x00191011);
+ db_assert(temp == 0x00191011);
pci_write_config_dword(&dev, PCI_BASE_ADDRESS_0, 0x1000);
pci_write_config_dword(&dev, PCI_BASE_ADDRESS_1, DDB_PCI0_MEM_BASE);
Index: setup.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/ddb5xxx/ddb5477/setup.c,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -d -r1.1.1.1 -r1.2
--- setup.c 2001/06/22 02:29:31 1.1.1.1
+++ setup.c 2001/10/11 20:45:26 1.2
@@ -33,6 +33,7 @@
#include <asm/irq.h>
#include <asm/reboot.h>
#include <asm/gdb-stub.h>
+#include <asm/debug.h>
#include <asm/ddb5xxx/ddb5xxx.h>
@@ -60,7 +61,7 @@
/* CPU cold reset */
t = ddb_in32(DDB_CPUSTAT);
- MIPS_ASSERT((t&1));
+ db_assert((t&1));
ddb_out32(DDB_CPUSTAT, t);
/* Call the PROM */
@@ -90,7 +91,7 @@
rtc_ds1386_init(KSEG1ADDR(DDB_LCS1_BASE));
}
-#if defined(CONFIG_LL_DEBUG)
+#if defined(CONFIG_DEBUG)
int board_init_done_flag = 0;
#endif
@@ -117,7 +118,7 @@
#endif
/* this is the last board dependent code */
- MIPS_DEBUG(board_init_done_flag = 1);
+ db_run(board_init_done_flag = 1);
}
static void ddb5477_board_init(void);
@@ -164,11 +165,11 @@
/* ----------- setup PDARs ------------ */
/* SDRAM should have been set */
- MIPS_ASSERT(ddb_in32(DDB_SDRAM0) ==
+ db_assert(ddb_in32(DDB_SDRAM0) ==
ddb_calc_pdar(DDB_SDRAM_BASE, DDB_SDRAM_SIZE, 32, 0, 1));
/* SDRAM1 should be turned off. What is this for anyway ? */
- MIPS_ASSERT( (ddb_in32(DDB_SDRAM1) & 0xf) == 0);
+ db_assert( (ddb_in32(DDB_SDRAM1) & 0xf) == 0);
/* Set LDCSs */
/* flash */
@@ -179,12 +180,12 @@
ddb_set_pdar(DDB_LCS2, DDB_LCS2_BASE, DDB_LCS2_SIZE, 16, 0, 0);
/* verify VRC5477 base addr */
- MIPS_ASSERT(ddb_in32(DDB_VRC5477) ==
- ddb_calc_pdar(DDB_VRC5477_BASE, DDB_VRC5477_SIZE, 32, 0, 1));
+ db_assert(ddb_in32(DDB_VRC5477) ==
+ ddb_calc_pdar(DDB_VRC5477_BASE, DDB_VRC5477_SIZE, 32, 0, 1));
/* verify BOOT ROM addr */
- MIPS_ASSERT(ddb_in32(DDB_BOOTCS) ==
- ddb_calc_pdar(DDB_BOOTCS_BASE, DDB_BOOTCS_SIZE, 8, 0, 0));
+ db_assert(ddb_in32(DDB_BOOTCS) ==
+ ddb_calc_pdar(DDB_BOOTCS_BASE, DDB_BOOTCS_SIZE, 8, 0, 0));
/* setup PCI windows - window0 for MEM/config, window1 for IO */
ddb_set_pdar(DDB_PCIW0, DDB_PCI0_MEM_BASE, DDB_PCI0_MEM_SIZE, 32, 0, 1);
|
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