Update of /cvsroot/linux-mips/linux/arch/mips/vr4122/eagle
In directory usw-pr-cvs1:/tmp/cvs-serv17388/arch/mips/vr4122/eagle
Modified Files:
pci.c
Log Message:
Consolidate TLB context switching code. This also fixes a bunch very obscure bugs in the 32-bit code which probably didn't bite anybody yet.
Index: pci.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/vr4122/eagle/pci.c,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -d -r1.2 -r1.3
--- pci.c 2001/10/08 18:06:07 1.2
+++ pci.c 2001/10/09 21:54:21 1.3
@@ -210,7 +210,6 @@
/* assume it's a generic PCI interrupt */
dev->irq = VR4122_IRQ_PCI;
-#if 0
/* if it's wired differently, correct the assumption */
switch (dev->vendor) {
case PCI_VENDOR_ID_NEC:
@@ -228,7 +227,6 @@
dev->irq = VR4122_IRQ_MQ200;
break;
}
-#endif
}
static void __init pcibios_fixup_irqs(void)
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