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From: Jun S. <ju...@us...> - 2001-09-27 23:59:17
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Update of /cvsroot/linux-mips/linux/include/asm-mips/vr4181
In directory usw-pr-cvs1:/tmp/cvs-serv12527/include/asm-mips/vr4181
Modified Files:
vr4181.h
Added Files:
irq.h
Log Message:
Re-write low-level irq dispatching code for vr4181/osprey. Pave the way for
the complete IRQ re-write.
--- NEW FILE: irq.h ---
/*
* Copyright (C) 1999 by Michael Klar
*
* Copyright (C) 2001 MontaVista Software Inc.
* Author: Jun Sun, js...@mv... or js...@ju...
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*/
/*
* Strategy:
*
* Vr4181 has conceptually three levels of interrupt controllers:
* 1. the CPU itself with 8 intr level.
* 2. system interrupt controller, cascaded from int0 pin in CPU, 32 intrs
* 3. GPIO interrupts : forwarding external interrupts to sys intr controller
*/
/* decide the irq block assignment */
#define VR4181_NUM_CPU_IRQ 8
#define VR4181_NUM_SYS_IRQ 32
#define VR4181_NUM_GPIO_IRQ 16
#define VR4181_IRQ_BASE 0
#define VR4181_CPU_IRQ_BASE VR4181_IRQ_BASE
#define VR4181_SYS_IRQ_BASE (VR4181_CPU_IRQ_BASE + VR4181_NUM_CPU_IRQ)
#define VR4181_GPIO_IRQ_BASE (VR4181_SYS_IRQ_BASE + VR4181_NUM_SYS_IRQ)
/* CPU interrupts */
/*
IP0 - Software interrupt
IP1 - Software interrupt
IP2 - All but battery, high speed modem, and real time clock
IP3 - RTC Long1 (system timer)
IP4 - RTC Long2
IP5 - High Speed Modem (unused on VR4181)
IP6 - Unused
IP7 - Timer interrupt from CPO_COMPARE
*/
#define VR4181_IRQ_SW1 (VR4181_CPU_IRQ_BASE + 0)
#define VR4181_IRQ_SW2 (VR4181_CPU_IRQ_BASE + 1)
#define VR4181_IRQ_INT0 (VR4181_CPU_IRQ_BASE + 2)
#define VR4181_IRQ_INT1 (VR4181_CPU_IRQ_BASE + 3)
#define VR4181_IRQ_INT2 (VR4181_CPU_IRQ_BASE + 4)
#define VR4181_IRQ_INT3 (VR4181_CPU_IRQ_BASE + 5)
#define VR4181_IRQ_INT4 (VR4181_CPU_IRQ_BASE + 6)
#define VR4181_IRQ_TIMER (VR4181_CPU_IRQ_BASE + 7)
/* Cascaded from VR4181_IRQ_INT0 (ICU mapped interrupts) */
/*
IP2 - same as VR4181_IRQ_INT1
IP8 - This is a cascade to GPIO IRQ's. Do not use.
IP16 - same as VR4181_IRQ_INT2
IP18 - CompactFlash
*/
#define VR4181_IRQ_BATTERY (VR4181_SYS_IRQ_BASE + 0)
#define VR4181_IRQ_POWER (VR4181_SYS_IRQ_BASE + 1)
#define VR4181_IRQ_RTCL1 (VR4181_SYS_IRQ_BASE + 2)
#define VR4181_IRQ_ETIMER (VR4181_SYS_IRQ_BASE + 3)
#define VR4181_IRQ_RFU12 (VR4181_SYS_IRQ_BASE + 4)
#define VR4181_IRQ_PIU (VR4181_SYS_IRQ_BASE + 5)
#define VR4181_IRQ_AIU (VR4181_SYS_IRQ_BASE + 6)
#define VR4181_IRQ_KIU (VR4181_SYS_IRQ_BASE + 7)
#define VR4181_IRQ_GIU (VR4181_SYS_IRQ_BASE + 8)
#define VR4181_IRQ_SIU (VR4181_SYS_IRQ_BASE + 9)
#define VR4181_IRQ_RFU18 (VR4181_SYS_IRQ_BASE + 10)
#define VR4181_IRQ_SOFT (VR4181_SYS_IRQ_BASE + 11)
#define VR4181_IRQ_RFU20 (VR4181_SYS_IRQ_BASE + 12)
#define VR4181_IRQ_DOZEPIU (VR4181_SYS_IRQ_BASE + 13)
#define VR4181_IRQ_RFU22 (VR4181_SYS_IRQ_BASE + 14)
#define VR4181_IRQ_RFU23 (VR4181_SYS_IRQ_BASE + 15)
#define VR4181_IRQ_RTCL2 (VR4181_SYS_IRQ_BASE + 16)
#define VR4181_IRQ_LED (VR4181_SYS_IRQ_BASE + 17)
#define VR4181_IRQ_ECU (VR4181_SYS_IRQ_BASE + 18)
#define VR4181_IRQ_CSU (VR4181_SYS_IRQ_BASE + 19)
#define VR4181_IRQ_USB (VR4181_SYS_IRQ_BASE + 20)
#define VR4181_IRQ_DMA (VR4181_SYS_IRQ_BASE + 21)
#define VR4181_IRQ_LCD (VR4181_SYS_IRQ_BASE + 22)
#define VR4181_IRQ_RFU31 (VR4181_SYS_IRQ_BASE + 23)
#define VR4181_IRQ_RFU32 (VR4181_SYS_IRQ_BASE + 24)
#define VR4181_IRQ_RFU33 (VR4181_SYS_IRQ_BASE + 25)
#define VR4181_IRQ_RFU34 (VR4181_SYS_IRQ_BASE + 26)
#define VR4181_IRQ_RFU35 (VR4181_SYS_IRQ_BASE + 27)
#define VR4181_IRQ_RFU36 (VR4181_SYS_IRQ_BASE + 28)
#define VR4181_IRQ_RFU37 (VR4181_SYS_IRQ_BASE + 29)
#define VR4181_IRQ_RFU38 (VR4181_SYS_IRQ_BASE + 30)
#define VR4181_IRQ_RFU39 (VR4181_SYS_IRQ_BASE + 31)
/* Cascaded from VR4181_IRQ_GIU */
#define VR4181_IRQ_GPIO0 (VR4181_GPIO_IRQ_BASE + 0)
#define VR4181_IRQ_GPIO1 (VR4181_GPIO_IRQ_BASE + 1)
#define VR4181_IRQ_GPIO2 (VR4181_GPIO_IRQ_BASE + 2)
#define VR4181_IRQ_GPIO3 (VR4181_GPIO_IRQ_BASE + 3)
#define VR4181_IRQ_GPIO4 (VR4181_GPIO_IRQ_BASE + 4)
#define VR4181_IRQ_GPIO5 (VR4181_GPIO_IRQ_BASE + 5)
#define VR4181_IRQ_GPIO6 (VR4181_GPIO_IRQ_BASE + 6)
#define VR4181_IRQ_GPIO7 (VR4181_GPIO_IRQ_BASE + 7)
#define VR4181_IRQ_GPIO8 (VR4181_GPIO_IRQ_BASE + 8)
#define VR4181_IRQ_GPIO9 (VR4181_GPIO_IRQ_BASE + 9)
#define VR4181_IRQ_GPIO10 (VR4181_GPIO_IRQ_BASE + 10)
#define VR4181_IRQ_GPIO11 (VR4181_GPIO_IRQ_BASE + 11)
#define VR4181_IRQ_GPIO12 (VR4181_GPIO_IRQ_BASE + 12)
#define VR4181_IRQ_GPIO13 (VR4181_GPIO_IRQ_BASE + 13)
#define VR4181_IRQ_GPIO14 (VR4181_GPIO_IRQ_BASE + 14)
#define VR4181_IRQ_GPIO15 (VR4181_GPIO_IRQ_BASE + 15)
// Alternative to above GPIO IRQ defines
#define VR4181_IRQ_GPIO(pin) ((VR4181_IRQ_GPIO0) + (pin))
#define VR4181_IRQ_MAX (VR4181_IRQ_BASE + VR4181_NUM_CPU_IRQ + \
VR4181_NUM_SYS_IRQ + VR4181_NUM_GPIO_IRQ)
Index: vr4181.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/vr4181/vr4181.h,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- vr4181.h 2001/09/22 04:27:16 1.1
+++ vr4181.h 2001/09/27 23:59:15 1.2
@@ -12,73 +12,7 @@
#include <asm/addrspace.h>
-// CPU interrupts
-#define VR4181_IRQ_SW1 0 // IP0 - Software interrupt
-#define VR4181_IRQ_SW2 1 // IP1 - Software interrupt
-#define VR4181_IRQ_INT0 2 // IP2 - All but battery, high speed modem, and real time clock
-#define VR4181_IRQ_INT1 3 // IP3 - RTC Long1 (system timer)
-#define VR4181_IRQ_INT2 4 // IP4 - RTC Long2
-#define VR4181_IRQ_INT3 5 // IP5 - High Speed Modem (unused on VR4181)
-#define VR4181_IRQ_INT4 6 // IP6 - Unused
-#define VR4181_IRQ_TIMER 7 // IP7 - Timer interrupt from CPO_COMPARE (Note: RTC Long1 is the system timer.)
-
-// Cascaded from VR4181_IRQ_INT0 (ICU mapped interrupts)
-#define VR4181_IRQ_BATTERY 8
-#define VR4181_IRQ_POWER 9
-#define VR4181_IRQ_RTCL1 10 // Use VR4181_IRQ_INT1 instead.
-#define VR4181_IRQ_ETIMER 11
-#define VR4181_IRQ_RFU12 12
-#define VR4181_IRQ_PIU 13
-#define VR4181_IRQ_AIU 14
-#define VR4181_IRQ_KIU 15
-#define VR4181_IRQ_GIU 16 // This is a cascade to IRQs 40-71. Do not use.
-#define VR4181_IRQ_SIU 17
-#define VR4181_IRQ_RFU18 18
-#define VR4181_IRQ_SOFT 19
-#define VR4181_IRQ_RFU20 20
-#define VR4181_IRQ_DOZEPIU 21
-#define VR4181_IRQ_RFU22 22
-#define VR4181_IRQ_RFU23 23
-#define VR4181_IRQ_RTCL2 24 // Use VR4181_IRQ_INT2 instead.
-#define VR4181_IRQ_LED 25
-#define VR4181_IRQ_ECU 26 // (CompactFlash)
-#define VR4181_IRQ_CSU 27
-#define VR4181_IRQ_USB 28
-#define VR4181_IRQ_DMA 29
-#define VR4181_IRQ_LCD 30
-#define VR4181_IRQ_RFU31 31
-#define VR4181_IRQ_RFU32 32
-#define VR4181_IRQ_RFU33 33
-#define VR4181_IRQ_RFU34 34
-#define VR4181_IRQ_RFU35 35
-#define VR4181_IRQ_RFU36 36
-#define VR4181_IRQ_RFU37 37
-#define VR4181_IRQ_RFU38 38
-#define VR4181_IRQ_RFU39 39
-// Note: Still need to do the extra VR4181 IRQ definitions
-
-// Cascaded from VR4181_IRQ_GIU
-#define VR4181_IRQ_GPIO0 40
-#define VR4181_IRQ_GPIO1 41
-#define VR4181_IRQ_GPIO2 42
-#define VR4181_IRQ_GPIO3 43
-#define VR4181_IRQ_GPIO4 44
-#define VR4181_IRQ_GPIO5 45
-#define VR4181_IRQ_GPIO6 46
-#define VR4181_IRQ_GPIO7 47
-#define VR4181_IRQ_GPIO8 48
-#define VR4181_IRQ_GPIO9 49
-#define VR4181_IRQ_GPIO10 50
-#define VR4181_IRQ_GPIO11 51
-#define VR4181_IRQ_GPIO12 52
-#define VR4181_IRQ_GPIO13 53
-#define VR4181_IRQ_GPIO14 54
-#define VR4181_IRQ_GPIO15 55
-
-// Alternative to above GPIO IRQ defines
-#define VR4181_IRQ_GPIO(pin) ((VR4181_IRQ_GPIO0) + (pin))
-
-#define VR4181_IRQ_MAX 55
+#include <asm/vr4181/irq.h>
#ifndef _LANGUAGE_ASSEMBLY
#define __preg8 (volatile unsigned char*)
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