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linux-mips-commits
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From: Jun S. <ju...@us...> - 2001-09-22 04:27:18
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Update of /cvsroot/linux-mips/linux/arch/mips/vr4122/eagle
In directory usw-pr-cvs1:/tmp/cvs-serv27047/arch/mips/vr4122/eagle
Added Files:
Makefile irq.c pci.c prom.c setup.c
Log Message:
Initial re-structuring of vr41xx directory. More are coming to
actually get Osprey/Eagle building and running.
--- NEW FILE: Makefile ---
#
# Copyright 2001 MontaVista Software Inc.
# Author: Yoichi Yuasa
# yy...@mv... or so...@mv...
#
# Makefile for the NEC Eagle specific parts of the kernel
#
# Note! Dependencies are done automagically by 'make dep', which also
# removes any old dependencies. DON'T put your own dependencies here
# unless it's something special (ie not a .c file).
#
.S.s:
$(CPP) $(AFLAGS) $< -o $@
.S.o:
$(CC) $(AFLAGS) -c $< -o $@
O_TARGET := eagle.o
all: eagle.o
obj-y := irq.o pci.o prom.o setup.o
include $(TOPDIR)/Rules.make
--- NEW FILE: irq.c ---
/*
* BRIEF MODULE DESCRIPTION
* NEC Eagle interrupt routines.
*
* Copyright 2001 MontaVista Software Inc.
* Author: Yoichi Yuasa
* yy...@mv... or so...@mv...
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/spinlock.h>
#include <asm/io.h>
#include <asm/mipsregs.h>
#include <asm/vr4122/vr4122.h>
#include <asm/vr4122/eagle.h>
#ifdef CONFIG_REMOTE_DEBUG
extern void set_debug_traps(void);
extern void breakpoint(void);
#endif
extern asmlinkage void vr4122_handle_int(void);
extern void __init init_generic_irq(void);
spinlock_t vr4122_icu_lock = SPIN_LOCK_UNLOCKED;
static void enable_cpucore_irq(unsigned int irq)
{
unsigned long flags, status;
spin_lock_irqsave(&vr4122_icu_lock, flags);
status = read_32bit_cp0_register(CP0_STATUS);
status |= (1UL << (irq + 8));
set_cp0_status(ST0_IM, status);
spin_unlock_irqrestore(&vr4122_icu_lock, flags);
}
static void disable_cpucore_irq(unsigned int irq)
{
unsigned long flags, status;
spin_lock_irqsave(&vr4122_icu_lock, flags);
status = read_32bit_cp0_register(CP0_STATUS);
status &= ~(1UL << (irq + 8));
set_cp0_status(ST0_IM, status);
spin_unlock_irqrestore(&vr4122_icu_lock, flags);
}
static unsigned int startup_cpucore_irq(unsigned int irq)
{
enable_cpucore_irq(irq);
return 0; /* never anything pending */
}
#define shutdown_cpucore_irq disable_cpucore_irq
#define mask_and_ack_cpucore_irq disable_cpucore_irq
static void end_cpucore_irq(unsigned int irq)
{
if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
enable_cpucore_irq(irq);
}
static struct hw_interrupt_type cpucore_irq_type = {
"CPU CORE",
startup_cpucore_irq,
shutdown_cpucore_irq,
enable_cpucore_irq,
disable_cpucore_irq,
mask_and_ack_cpucore_irq,
end_cpucore_irq,
NULL
};
/*=======================================================================*/
static void enable_sysint1_irq(unsigned int irq)
{
unsigned long flags;
unsigned short val;
spin_lock_irqsave(&vr4122_icu_lock, flags);
val = readw(VR4122_MSYSINT1REG);
val |= (u16)1 << (irq - 8);
writew(val, VR4122_MSYSINT1REG);
spin_unlock_irqrestore(&vr4122_icu_lock, flags);
}
static void disable_sysint1_irq(unsigned int irq)
{
unsigned long flags;
unsigned short val;
spin_lock_irqsave(&vr4122_icu_lock, flags);
val = readw(VR4122_MSYSINT1REG);
val &= ~((u16)1 << (irq - 8));
writew(val, VR4122_MSYSINT1REG);
spin_unlock_irqrestore(&vr4122_icu_lock, flags);
}
static unsigned int startup_sysint1_irq(unsigned int irq)
{
enable_sysint1_irq(irq);
return 0; /* never anything pending */
}
#define shutdown_sysint1_irq disable_sysint1_irq
#define mask_and_ack_sysint1_irq disable_sysint1_irq
static void end_sysint1_irq(unsigned int irq)
{
if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
enable_sysint1_irq(irq);
}
static struct hw_interrupt_type sysint1_irq_type = {
"SYSINT1",
startup_sysint1_irq,
shutdown_sysint1_irq,
enable_sysint1_irq,
disable_sysint1_irq,
mask_and_ack_sysint1_irq,
end_sysint1_irq,
NULL
};
/*=======================================================================*/
static void enable_sysint2_irq(unsigned int irq)
{
unsigned long flags;
unsigned short val;
spin_lock_irqsave(&vr4122_icu_lock, flags);
if (irq == VR4122_IRQ_DSIU) {
val = readw(VR4122_MDSIUINTREG);
val |= 0x0800;
writew(val, VR4122_MDSIUINTREG);
}
val = readw(VR4122_MSYSINT2REG);
val |= (u16)1 << (irq - 24);
writew(val, VR4122_MSYSINT2REG);
spin_unlock_irqrestore(&vr4122_icu_lock, flags);
}
static void disable_sysint2_irq(unsigned int irq)
{
unsigned long flags;
unsigned short val;
spin_lock_irqsave(&vr4122_icu_lock, flags);
if (irq == VR4122_IRQ_DSIU) {
writew(0, VR4122_MDSIUINTREG);
}
val = readw(VR4122_MSYSINT2REG);
val &= ~((u16)1 << (irq - 24));
writew(val, VR4122_MSYSINT2REG);
spin_unlock_irqrestore(&vr4122_icu_lock, flags);
}
static unsigned int startup_sysint2_irq(unsigned int irq)
{
enable_sysint2_irq(irq);
return 0; /* never anything pending */
}
#define shutdown_sysint2_irq disable_sysint2_irq
#define mask_and_ack_sysint2_irq disable_sysint2_irq
static void end_sysint2_irq(unsigned int irq)
{
if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
enable_sysint2_irq(irq);
}
static struct hw_interrupt_type sysint2_irq_type = {
"SYSINT2",
startup_sysint2_irq,
shutdown_sysint2_irq,
enable_sysint2_irq,
disable_sysint2_irq,
mask_and_ack_sysint2_irq,
end_sysint2_irq,
NULL
};
/*=======================================================================*/
static void enable_giuintl_irq(unsigned int irq)
{
unsigned long flags;
unsigned short val, mask;
spin_lock_irqsave(&vr4122_icu_lock, flags);
if (irq == VR4122_IRQ_GPIO5)
*(volatile unsigned char *)KSEG1ADDR(0x0dffffe0) |= 0x10;
mask = (u16)1 << (irq - 40);
writew(mask, VR4122_GIUINTSTATL);
val = readw(VR4122_MGIUINTLREG);
val |= mask;
writew(val, VR4122_MGIUINTLREG);
val = readw(VR4122_GIUINTENL);
val |= mask;
writew(val, VR4122_GIUINTENL);
spin_unlock_irqrestore(&vr4122_icu_lock, flags);
}
static void disable_giuintl_irq(unsigned int irq)
{
unsigned long flags;
unsigned short val, mask;
spin_lock_irqsave(&vr4122_icu_lock, flags);
if (irq == 45)
*(volatile unsigned char *)KSEG1ADDR(0x0dffffe0) &= ~0x10;
mask = (u16)1 << (irq - 40);
val = readw(VR4122_GIUINTENL);
val &= ~mask;
writew(val, VR4122_GIUINTENL);
val = readw(VR4122_MGIUINTLREG);
val &= ~mask;
writew(val, VR4122_MGIUINTLREG);
writew(mask, VR4122_GIUINTSTATL);
spin_unlock_irqrestore(&vr4122_icu_lock, flags);
}
static unsigned int startup_giuintl_irq(unsigned int irq)
{
enable_giuintl_irq(irq);
return 0; /* never anything pending */
}
#define shutdown_giuintl_irq disable_giuintl_irq
#define mask_and_ack_giuintl_irq disable_giuintl_irq
static void end_giuintl_irq(unsigned int irq)
{
if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
enable_giuintl_irq(irq);
}
static struct hw_interrupt_type giuintl_irq_type = {
"GIUINTL",
startup_giuintl_irq,
shutdown_giuintl_irq,
enable_giuintl_irq,
disable_giuintl_irq,
mask_and_ack_giuintl_irq,
end_giuintl_irq,
NULL
};
/*=======================================================================*/
static void enable_giuinth_irq(unsigned int irq)
{
unsigned long flags;
unsigned short val, mask;
spin_lock_irqsave(&vr4122_icu_lock, flags);
mask = (u16)1 << (irq - 56);
writew(mask, VR4122_GIUINTSTATH);
val = readw(VR4122_MGIUINTHREG);
val |= mask;
writew(val, VR4122_MGIUINTHREG);
val = readw(VR4122_GIUINTENH);
val |= mask;
writew(val, VR4122_GIUINTENH);
spin_unlock_irqrestore(&vr4122_icu_lock, flags);
}
static void disable_giuinth_irq(unsigned int irq)
{
unsigned long flags;
unsigned short val, mask;
spin_lock_irqsave(&vr4122_icu_lock, flags);
mask = (u16)1 << (irq - 56);
val= readw(VR4122_GIUINTENH);
val &= ~mask;
writew(val, VR4122_GIUINTENH);
val = readw(VR4122_MGIUINTHREG);
val &= ~mask;
writew(val, VR4122_MGIUINTHREG);
writew(mask, VR4122_GIUINTSTATH);
spin_unlock_irqrestore(&vr4122_icu_lock, flags);
}
static unsigned int startup_giuinth_irq(unsigned int irq)
{
enable_giuinth_irq(irq);
return 0; /* never anything pending */
}
#define shutdown_giuinth_irq disable_giuinth_irq
#define mask_and_ack_giuinth_irq disable_giuinth_irq
static void end_giuinth_irq(unsigned int irq)
{
if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
enable_giuinth_irq(irq);
}
static struct hw_interrupt_type giuinth_irq_type = {
"GIUINTH",
startup_giuinth_irq,
shutdown_giuinth_irq,
enable_giuinth_irq,
disable_giuinth_irq,
mask_and_ack_giuinth_irq,
end_giuinth_irq,
NULL
};
/*=======================================================================*/
void __init init_vr4122_icu_irqs(void)
{
unsigned long flags;
int i;
spin_lock_irqsave(&vr4122_icu_lock, flags);
/* Default all ICU IRQs to off ... */
writew(0, VR4122_MSYSINT1REG);
writew(0, VR4122_MGIUINTLREG);
writew(0, VR4122_MDSIUINTREG);
writew(0, VR4122_MSYSINT2REG);
writew(0, VR4122_MGIUINTHREG);
writew(0, VR4122_MFIRINTREG);
writew(0, VR4122_MPCIINTREG);
writew(0, VR4122_MSCUINTREG);
writew(0, VR4122_MCSIINTREG);
#if 0
writew(0, VR4122_MBCUINTREG);
#endif
writew(0, VR4122_GIUINTENL);
writew(0, VR4122_GIUINTENH);
writew(0xffff, VR4122_GIUINTSTATL);
writew(0xffff, VR4122_GIUINTSTATH);
barrier();
for (i = 0; i < NR_IRQS; i++) {
irq_desc[i].status = IRQ_DISABLED;
irq_desc[i].action = 0;
irq_desc[i].depth = 1;
if (i < 8)
irq_desc[i].handler = &cpucore_irq_type;
else if (i < 24)
irq_desc[i].handler = &sysint1_irq_type;
else if (i < 40)
irq_desc[i].handler = &sysint2_irq_type;
else if (i < 56)
irq_desc[i].handler = &giuintl_irq_type;
else if (i < 72)
irq_desc[i].handler = &giuinth_irq_type;
}
spin_unlock_irqrestore(&vr4122_icu_lock, flags);
}
static struct irqaction cascade = {
no_action, 0, 0, "cascade", NULL, NULL
};
static struct irqaction reserved = {
no_action, 0, 0, "reserved", NULL, NULL
};
void __init init_IRQ(void)
{
memset(irq_desc, 0, sizeof(irq_desc));
init_generic_irq();
init_vr4122_icu_irqs();
setup_irq(VR4122_IRQ_INT0, &cascade);
setup_irq(VR4122_IRQ_GIU, &cascade);
setup_irq(VR4122_IRQ_RTCL1, &reserved);
setup_irq(VR4122_IRQ_RTCL2, &reserved);
set_except_vector(0, vr4122_handle_int);
#ifdef CONFIG_REMOTE_DEBUG
set_debug_traps();
/* you may move this line to whereever you want */
breakpoint();
#endif
}
--- NEW FILE: pci.c ---
/*
* THIS CODE AND INFORMATION IS PROVIDED "AS IS" WITHOUT WARRANTY OF
* ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR FITNESS FOR A
* PARTICULAR PURPOSE.
* Copyright (C) NEC Corporation 2001.
*/
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pci.h>
#include <linux/ioport.h>
#include <asm/types.h>
#include <asm/vr4122/vr4122.h>
#include <asm/vr4122/eagle.h>
#ifdef CONFIG_EAGLE_REV1
#define EAGLE_REV1_ON { \
unsigned short val; \
val = readw(VR4122_GIUPIODL); \
val |= VR4122_GIUPIODL_GPIO9; \
writew(val, VR4122_GIUPIODL); }
#define EAGLE_REV1_OFF { \
unsigned short val; \
val = readw(VR4122_GIUPIODL); \
val &= VR4122_GIUPIODL_GPIO9; \
writew(val, VR4122_GIUPIODL); }
#else
#define EAGLE_REV1_ON
#define EAGLE_REV1_OFF
#endif
#define MAX_PCI_DEV 64
extern struct pci_ops vr4122_pci_ops;
extern void vr4122_pcibios_init(void);
static unsigned long memstart = 0x10200000;
static unsigned long memlimit = 0x15ffffff;
static unsigned long iostart = 0x00010000;
static unsigned long iolimit = 0x01ffffff;
static int pcidevs = 0;
static unsigned long ReadConfig32(int bus, int dev, int func, int reg)
{
unsigned long config;
if (bus == 0) {
/* type 0 configuration */
if (dev < 11 || dev >= 32 || func >= 8 || reg >= 256)
return 0xffffffff;
EAGLE_REV1_ON;
writel((reg & 0xfc) | (func << 8) | (1 << dev), VR4122_PCICONFAREG);
}
else {
/* type 1 configuration */
if (bus >= 256 || dev >= 32 || func >= 8 || reg >= 256)
return 0xffffffff;
EAGLE_REV1_OFF;
writel(1 | (reg & 0xfc) | (func << 8) | (dev << 11) | (bus << 16),
VR4122_PCICONFAREG);
}
config = readl(VR4122_PCICONFDREG);
EAGLE_REV1_ON;
return config;
}
static void WriteConfig32(int bus, int dev, int func, int reg, unsigned long data)
{
if (bus == 0) {
/* type 0 configuration */
if (dev<11 || dev>=32 || func>=8 || reg>=256)
return;
EAGLE_REV1_ON;
writel((reg & 0xfc) | (func << 8) | (1 << dev),VR4122_PCICONFAREG);
}
else {
/* type 1 configuration */
if (bus>=256 || dev>=32 || func>=8 || reg>=256)
return;
EAGLE_REV1_OFF;
writel(1 | (reg & 0xfc) | (func << 8) | (dev << 11) | (bus << 16),
VR4122_PCICONFAREG);
}
writel(data, VR4122_PCICONFDREG);
EAGLE_REV1_ON;
}
static void map_resource(int bus, int dev, int func, int nbase)
{
unsigned long val, reg, next, req, base, size;
/* Scan all base registers */
next = 0x10;
while (next < 0x10 + nbase * 4) {
reg = next;
next = reg + 4;
WriteConfig32(bus, dev, func, reg, 0xFFFFFFFF);
val = ReadConfig32(bus, dev, func, reg);
if (val & 1) {
req = ~(val & 0xFFFFFFFC)+1;
if (req & (req - 1))
continue;
if (req == 0)
continue;
size = req > 0x1000 ? req : 0x1000;
base = (iostart + size - 1) & ~(size - 1);
if ((base + size - 1) > iolimit)
continue;
iostart = base + size;
}
else {
req = ~(val & 0xFFFFFFF0) + 1;
if (req & (req - 1))
continue;
if (req == 0)
continue;
switch (val & 0x00000006) {
case 0:
break;
case 2:
continue;
case 4:
WriteConfig32(bus, dev, func, reg + 4, 0);
next += 4;
break;
case 6:
continue;
}
size = req > 0x1000 ? req : 0x1000;
base = (memstart + size - 1) & ~(size - 1);
if ((base + size - 1) > memlimit)
continue;
memstart = base + size;
}
WriteConfig32(bus, dev, func, reg, base);
}
}
static int __init eagle_pcidev_init(int bus, int dev, int func)
{
u32 id, status, bhlc;
int nbase = 0;
/* Probe device */
writel(0xff00ff00, VR4122_INTCNTSTAREG);
id = ReadConfig32(bus, dev, func, PCI_VENDOR_ID);
status = readl(VR4122_INTCNTSTAREG);
writel(0xff00ff00, VR4122_INTCNTSTAREG);
if (status & 0x000000ff)
return 1;
if ((id & 0xffff) == 0xffff)
return 1;
if (pcidevs >= MAX_PCI_DEV)
return 1;
pcidevs++;
bhlc = ReadConfig32(bus, dev, func, PCI_CACHE_LINE_SIZE);
switch ((bhlc >> 16) & 0x7f) {
case 0:
nbase = 6;
break;
case 1:
nbase = 2;
break;
case 2:
nbase = 1;
break;
default:
}
map_resource(bus, dev, func, nbase);
/* Set master latency timer and cache line size */
WriteConfig32(bus, dev, func, PCI_CACHE_LINE_SIZE, 0x8004);
/* Enable device and clear all status */
WriteConfig32(bus, dev, func, PCI_COMMAND,
ReadConfig32(bus, dev, func, PCI_COMMAND) | 0xffff0000 |
PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
PCI_COMMAND_SERR);
return 0;
}
static void __init eagle_pcibus_init(int bus)
{
int dev, func;
unsigned long type;
for (dev = 0; dev < 32; dev++) {
for (func = 0; func < 8; func++) {
if (eagle_pcidev_init(bus, dev, func)) {
type = ReadConfig32(bus, dev, func,
PCI_CACHE_LINE_SIZE);
if ((type & 0x00800000) == 0)
break;
}
}
}
}
void __init pcibios_update_irq(struct pci_dev *dev, int irq)
{
/* assume it's a generic PCI interrupt */
dev->irq = VR4122_IRQ_PCI;
/* if it's wired differently, correct the assumption */
switch (dev->vendor) {
case PCI_VENDOR_ID_NEC:
switch (dev->device) {
case PCI_DEVICE_ID_NEC_VRC4173_BCU:
case PCI_DEVICE_ID_NEC_VRC4173_AC97:
case PCI_DEVICE_ID_NEC_VRC4173_CARDU:
case PCI_DEVICE_ID_NEC_VRC4173_USB: /* all three share the same IRQ */
dev->irq = VR4122_IRQ_VRC4173;
break;
}
break;
case PCI_VENDOR_ID_MEDIAQ:
if (dev->device == PCI_DEVICE_ID_MEDIAQ_MQ200)
dev->irq = VR4122_IRQ_MQ200;
break;
}
}
static void __init pcibios_fixup_irqs(void)
{
struct pci_dev *dev;
int slot_num;
int cnt = 0;
pci_for_each_dev(dev) {
slot_num = PCI_SLOT(dev->devfn);
pcibios_update_irq(dev, cnt++);
}
}
void __init pcibios_fixup_bus(struct pci_bus *b)
{
}
void pcibios_update_resource(struct pci_dev *dev, struct resource *root,
struct resource *res, int resource)
{
}
void __init pcibios_init(void)
{
vr4122_pcibios_init();
ioport_resource.start = 0;
ioport_resource.end = VR4122_PCI_IO_SIZE;
iomem_resource.start = VR4122_PCI_MEM_BASE;
iomem_resource.end = VR4122_PCI_MEM_BASE + VR4122_PCI_MEM_SIZE;
eagle_pcibus_init(0);
(void)pci_scan_bus(0, &vr4122_pci_ops, NULL);
pcibios_fixup_irqs();
}
int __init pcibios_enable_device(struct pci_dev *dev)
{
/* Not needed, sine we enable all devices at startup */
return 0;
}
void __init pcibios_align_resource(void *data, struct resource *res,
unsigned long size)
{
/* Nothing to do. */
}
char * __init pcibios_setup(char *str)
{
/* Nothing to do for now. */
return str;
}
struct pci_fixup pcibios_fixups[] = { { 0 } };
--- NEW FILE: prom.c ---
/*
* BRIEF MODULE DESCRIPTION
* PROM library initialisation code for NEC Vr4122.
*
* Copyright 2001 MontaVista Software Inc.
* Author: Yoichi Yuasa
* yy...@mv... or so...@mv...
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/config.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/string.h>
#include <asm/bootinfo.h>
char arcs_cmdline[COMMAND_LINE_SIZE];
/* Do basic initialization */
void __init prom_init(int argc, char **argv,
unsigned long magic, int *prom_vec)
{
int mem_size = CONFIG_NEC_EAGLE_MEM_SIZE;
int i;
/*
* collect args and prepare cmd_line
*/
for (i = 1; i < argc; i++) {
strcat(arcs_cmdline, argv[i]);
if (i < (argc - 1))
strcat(arcs_cmdline, " ");
}
#if defined(CONFIG_SERIAL_CONSOLE)
/* to use 38400 ttyS0 serial console */
strcat(arcs_cmdline, " console=ttyS0,38400");
#endif
mips_machgroup = MACH_GROUP_NEC_VR41XX;
#ifdef CONFIG_NEC_EAGLE
mips_machtype = MACH_NEC_EAGLE;
#endif
/* Add memory region */
switch (mem_size) {
case 32:
add_memory_region(0, 32 << 20, BOOT_MEM_RAM);
break;
case 64:
add_memory_region(0, 64 << 20, BOOT_MEM_RAM);
break;
default:
panic("Memory size error\n");
}
}
void __init prom_free_prom_memory (void)
{
}
--- NEW FILE: setup.c ---
/*
* BRIEF MODULE DESCRIPTION
* Setup for NEC Eagle board.
*
* Copyright 2001 MontaVista Software Inc.
* Author: Yoichi Yuasa
* yy...@mv... or so...@mv...
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/init.h>
#include <linux/console.h>
#include <asm/addrspace.h>
#include <asm/io.h>
#include <asm/reboot.h>
#include <asm/time.h>
#include <asm/vr4122/vr4122.h>
#include <asm/vr4122/eagle.h>
extern void vr4122_restart(char *command);
extern void vr4122_halt(void);
extern void vr4122_power_off(void);
extern void vr4122_time_init(void);
extern void vr4122_timer_setup(struct irqaction *irq);
void __init nec_eagle_setup(void)
{
unsigned long clock;
unsigned short val;
val = readw(VR4122_CLKSPEEDREG);
clock = (18432000 * 98) / (val & 0x1f);
printk("PClock: %ldHz\n", clock);
clock = clock / ((val & 0x700) >> 8);
printk("VTClock: %ldHz\n", clock);
clock = clock / (2 << ((val & 0x1000) >> 12));
printk("TClock: %ldHz\n", clock);
mips_counter_frequency = clock / 4;
mips_io_port_base = VR4122_IO_PORT_BASE;
_machine_restart = vr4122_restart;
_machine_halt = vr4122_halt;
_machine_power_off = vr4122_power_off;
board_time_init = vr4122_time_init;
board_timer_setup = vr4122_timer_setup;
#ifdef CONFIG_FB
conswitchp = &dummy_con;
#endif
/* Select RS-232C */
val = readw(VR4122_SIUIRSEL);
val &= ~VR4122_SIUIRSEL_SIRSEL;
writew(val, VR4122_SIUIRSEL);
/* Supply DSIU and SIU clock */
vr4122_clock_supply(VR4122_CMUCLKMSK_MSKSIU);
vr4122_clock_supply(VR4122_CMUCLKMSK_MSKDSIU);
vr4122_clock_supply(VR4122_CMUCLKMSK_MSKSSIU);
}
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