Update of /cvsroot/linux-mips/linux/include/asm-mips
In directory usw-pr-cvs1:/tmp/cvs-serv12962
Modified Files:
asm.h
Log Message:
Synced up.
Index: asm.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/asm.h,v
retrieving revision 1.1
retrieving revision 1.2
diff -C2 -d -r1.1 -r1.2
*** asm.h 2001/09/04 11:25:25 1.1
--- asm.h 2001/09/04 16:12:54 1.2
***************
*** 85,93 ****
* EXPORT - export definition of symbol
*/
! #define EXPORT(symbol) \
.globl symbol; \
symbol:
/*
* ABS - export absolute symbol
*/
--- 85,101 ----
* EXPORT - export definition of symbol
*/
! #define EXPORT(symbol) \
.globl symbol; \
symbol:
/*
+ * FEXPORT - export definition of a function symbol
+ */
+ #define FEXPORT(symbol) \
+ .globl symbol; \
+ .type symbol,@function; \
+ symbol:
+
+ /*
* ABS - export absolute symbol
*/
***************
*** 106,110 ****
/*
! * Print formated string
*/
#define PRINT(string) \
--- 114,118 ----
/*
! * Print formatted string
*/
#define PRINT(string) \
***************
*** 139,143 ****
* is one of them. So we should have an option not to use this instruction.
*/
! #if (_MIPS_ISA == _MIPS_ISA_MIPS4) || (_MIPS_ISA == _MIPS_ISA_MIPS5)
#define PREF(hint,addr) \
pref hint,addr
--- 147,152 ----
* is one of them. So we should have an option not to use this instruction.
*/
! #if (_MIPS_ISA == _MIPS_ISA_MIPS4 ) || (_MIPS_ISA == _MIPS_ISA_MIPS5) || \
! (_MIPS_ISA == _MIPS_ISA_MIPS64)
#define PREF(hint,addr) \
pref hint,addr
***************
*** 145,150 ****
prefx hint,addr
#else
! #define PREF(hint,addr)
! #define PREFX(hint,addr)
#endif
--- 154,159 ----
prefx hint,addr
#else
! #define PREF
! #define PREFX
#endif
***************
*** 184,203 ****
9:
#endif /* (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3) */
! #if (_MIPS_ISA == _MIPS_ISA_MIPS4) || (_MIPS_ISA == _MIPS_ISA_MIPS5)
#define MOVN(rd,rs,rt) \
movn rd,rs,rt
#define MOVZ(rd,rs,rt) \
movz rd,rs,rt
! #endif /* (_MIPS_ISA == _MIPS_ISA_MIPS4) || (_MIPS_ISA == _MIPS_ISA_MIPS5) */
/*
* Stack alignment
*/
! #if (_MIPS_ISA == _MIPS_ISA_MIPS1) || (_MIPS_ISA == _MIPS_ISA_MIPS2)
#define ALSZ 7
#define ALMASK ~7
#endif
#if (_MIPS_ISA == _MIPS_ISA_MIPS3) || (_MIPS_ISA == _MIPS_ISA_MIPS4) || \
! (_MIPS_ISA == _MIPS_ISA_MIPS5)
#define ALSZ 15
#define ALMASK ~15
--- 193,214 ----
9:
#endif /* (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3) */
! #if (_MIPS_ISA == _MIPS_ISA_MIPS4 ) || (_MIPS_ISA == _MIPS_ISA_MIPS5) || \
! (_MIPS_ISA == _MIPS_ISA_MIPS64)
#define MOVN(rd,rs,rt) \
movn rd,rs,rt
#define MOVZ(rd,rs,rt) \
movz rd,rs,rt
! #endif /* MIPS IV, MIPS V or MIPS64 */
/*
* Stack alignment
*/
! #if (_MIPS_ISA == _MIPS_ISA_MIPS1) || (_MIPS_ISA == _MIPS_ISA_MIPS2) || \
! (_MIPS_ISA == _MIPS_ISA_MIPS32)
#define ALSZ 7
#define ALMASK ~7
#endif
#if (_MIPS_ISA == _MIPS_ISA_MIPS3) || (_MIPS_ISA == _MIPS_ISA_MIPS4) || \
! (_MIPS_ISA == _MIPS_ISA_MIPS5) || (_MIPS_ISA == _MIPS_ISA_MIPS64)
#define ALSZ 15
#define ALMASK ~15
***************
*** 217,221 ****
* pointers etc.
*/
! #if (_MIPS_ISA == _MIPS_ISA_MIPS1) || (_MIPS_ISA == _MIPS_ISA_MIPS2)
#define REG_S sw
#define REG_L lw
--- 228,233 ----
* pointers etc.
*/
! #if (_MIPS_ISA == _MIPS_ISA_MIPS1) || (_MIPS_ISA == _MIPS_ISA_MIPS2) || \
! (_MIPS_ISA == _MIPS_ISA_MIPS32)
#define REG_S sw
#define REG_L lw
***************
*** 224,228 ****
#endif
#if (_MIPS_ISA == _MIPS_ISA_MIPS3) || (_MIPS_ISA == _MIPS_ISA_MIPS4) || \
! (_MIPS_ISA == _MIPS_ISA_MIPS5)
#define REG_S sd
#define REG_L ld
--- 236,240 ----
#endif
#if (_MIPS_ISA == _MIPS_ISA_MIPS3) || (_MIPS_ISA == _MIPS_ISA_MIPS4) || \
! (_MIPS_ISA == _MIPS_ISA_MIPS5) || (_MIPS_ISA == _MIPS_ISA_MIPS64)
#define REG_S sd
#define REG_L ld
***************
*** 362,371 ****
* Some cp0 registers were extended to 64bit for MIPS III.
*/
! #if (_MIPS_ISA == _MIPS_ISA_MIPS1) || (_MIPS_ISA == _MIPS_ISA_MIPS2)
#define MFC0 mfc0
#define MTC0 mtc0
#endif
#if (_MIPS_ISA == _MIPS_ISA_MIPS3) || (_MIPS_ISA == _MIPS_ISA_MIPS4) || \
! (_MIPS_ISA == _MIPS_ISA_MIPS5)
#define MFC0 dmfc0
#define MTC0 dmtc0
--- 374,384 ----
* Some cp0 registers were extended to 64bit for MIPS III.
*/
! #if (_MIPS_ISA == _MIPS_ISA_MIPS1) || (_MIPS_ISA == _MIPS_ISA_MIPS2) || \
! (_MIPS_ISA == _MIPS_ISA_MIPS32)
#define MFC0 mfc0
#define MTC0 mtc0
#endif
#if (_MIPS_ISA == _MIPS_ISA_MIPS3) || (_MIPS_ISA == _MIPS_ISA_MIPS4) || \
! (_MIPS_ISA == _MIPS_ISA_MIPS5) || (_MIPS_ISA == _MIPS_ISA_MIPS64)
#define MFC0 dmfc0
#define MTC0 dmtc0
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