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From: James S. <jsi...@us...> - 2001-09-24 18:52:36
|
Update of /cvsroot/linux-mips/linux/arch/mips/configs In directory usw-pr-cvs1:/tmp/cvs-serv25700 Modified Files: defconfig-pb1000 Log Message: Added in sound configuration. Index: defconfig-pb1000 =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips/configs/defconfig-pb1000,v retrieving revision 1.6 retrieving revision 1.7 diff -u -d -r1.6 -r1.7 --- defconfig-pb1000 2001/09/15 17:06:10 1.6 +++ defconfig-pb1000 2001/09/24 18:52:33 1.7 @@ -513,7 +513,26 @@ # # Sound # -# CONFIG_SOUND is not set +CONFIG_SOUND=y +# CONFIG_SOUND_CMPCI is not set +# CONFIG_SOUND_EMU10K1 is not set +# CONFIG_SOUND_FUSION is not set +# CONFIG_SOUND_CS4281 is not set +# CONFIG_SOUND_ES1370 is not set +# CONFIG_SOUND_ES1371 is not set +# CONFIG_SOUND_ESSSOLO1 is not set +# CONFIG_SOUND_MAESTRO is not set +# CONFIG_SOUND_MAESTRO3 is not set +# CONFIG_SOUND_ICH is not set +# CONFIG_SOUND_SONICVIBES is not set +CONFIG_SOUND_AU1000=y +# CONFIG_SOUND_TRIDENT is not set +# CONFIG_SOUND_MSNDCLAS is not set +# CONFIG_SOUND_MSNDPIN is not set +# CONFIG_SOUND_VIA82CXXX is not set +# CONFIG_MIDI_VIA82CXXX is not set +# CONFIG_SOUND_OSS is not set +# CONFIG_SOUND_TVMIXER is not set # # USB support |
|
From: Jun S. <ju...@us...> - 2001-09-22 16:35:18
|
Update of /cvsroot/linux-mips/linux/arch/mips/vr4181/osprey
In directory usw-pr-cvs1:/tmp/cvs-serv5895/arch/mips/vr4181/osprey
Modified Files:
prom.c reset.c
Log Message:
Osprey kernel more or less works now, but very unstable. See TODO file.
Index: prom.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/vr4181/osprey/prom.c,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- prom.c 2001/09/22 04:27:15 1.1
+++ prom.c 2001/09/22 16:35:15 1.2
@@ -31,9 +31,10 @@
*/
void __init prom_init()
{
- strcpy(arcs_cmdline, "ether=0,0x03fe0300,eth0 "
+ strcpy(arcs_cmdline, "ip=bootp ");
+ strcat(arcs_cmdline, "ether=0,0x03fe0300,eth0 ");
// strcpy(arcs_cmdline, "ether=0,0x0300,eth0 "
- "video=vr4181fb:xres:240,yres:320,bpp:8");
+ // strcat(arcs_cmdline, "video=vr4181fb:xres:240,yres:320,bpp:8 ");
mips_machgroup = MACH_GROUP_NEC_VR41XX;
mips_machtype = MACH_NEC_OSPREY;
Index: reset.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/vr4181/osprey/reset.c,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- reset.c 2001/09/22 04:27:15 1.1
+++ reset.c 2001/09/22 16:35:15 1.2
@@ -18,8 +18,8 @@
void nec_osprey_restart(char *command)
{
- set_cp0_status((ST0_BEV | ST0_ERL), (ST0_BEV | ST0_ERL));
- set_cp0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
+ change_cp0_status((ST0_BEV | ST0_ERL), (ST0_BEV | ST0_ERL));
+ change_cp0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
flush_cache_all();
write_32bit_cp0_register(CP0_WIRED, 0);
__asm__ __volatile__("jr\t%0"::"r"(0xbfc00000));
|
|
From: Jun S. <ju...@us...> - 2001-09-22 16:35:18
|
Update of /cvsroot/linux-mips/linux/drivers/net
In directory usw-pr-cvs1:/tmp/cvs-serv5895/drivers/net
Added Files:
ne.c
Log Message:
Osprey kernel more or less works now, but very unstable. See TODO file.
--- NEW FILE: ne.c ---
/* ne.c: A general non-shared-memory NS8390 ethernet driver for linux. */
/*
Written 1992-94 by Donald Becker.
Copyright 1993 United States Government as represented by the
Director, National Security Agency.
This software may be used and distributed according to the terms
of the GNU General Public License, incorporated herein by reference.
The author may be reached as be...@sc..., or C/O
Scyld Computing Corporation, 410 Severn Ave., Suite 210, Annapolis MD 21403
This driver should work with many programmed-I/O 8390-based ethernet
boards. Currently it supports the NE1000, NE2000, many clones,
and some Cabletron products.
Changelog:
Paul Gortmaker : use ENISR_RDC to monitor Tx PIO uploads, made
sanity checks and bad clone support optional.
Paul Gortmaker : new reset code, reset card after probe at boot.
Paul Gortmaker : multiple card support for module users.
Paul Gortmaker : Support for PCI ne2k clones, similar to lance.c
Paul Gortmaker : Allow users with bad cards to avoid full probe.
Paul Gortmaker : PCI probe changes, more PCI cards supported.
rjo...@an... : Changed init order so an interrupt will only
occur after memory is allocated for dev->priv. Deallocated memory
last in cleanup_modue()
Richard Guenther : Added support for ISAPnP cards
Paul Gortmaker : Discontinued PCI support - use ne2k-pci.c instead.
*/
/* Routines for the NatSemi-based designs (NE[12]000). */
static const char version1[] =
"ne.c:v1.10 9/23/94 Donald Becker (be...@sc...)\n";
static const char version2[] =
"Last modified Nov 1, 2000 by Paul Gortmaker\n";
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/errno.h>
#include <linux/isapnp.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <asm/system.h>
#include <asm/io.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include "8390.h"
/* Some defines that people can play with if so inclined. */
/* Do we support clones that don't adhere to 14,15 of the SAprom ? */
#define SUPPORT_NE_BAD_CLONES
/* Do we perform extra sanity checks on stuff ? */
/* #define NE_SANITY_CHECK */
/* Do we implement the read before write bugfix ? */
/* #define NE_RW_BUGFIX */
/* Do we have a non std. amount of memory? (in units of 256 byte pages) */
/* #define PACKETBUF_MEMSIZE 0x40 */
/* A zero-terminated list of I/O addresses to be probed at boot. */
#ifndef MODULE
static unsigned int netcard_portlist[] __initdata = {
0x300, 0x280, 0x320, 0x340, 0x360, 0x380, 0
};
#endif
static struct isapnp_device_id isapnp_clone_list[] __initdata = {
{ ISAPNP_ANY_ID, ISAPNP_ANY_ID,
ISAPNP_VENDOR('E','D','I'), ISAPNP_FUNCTION(0x0216),
(long) "NN NE2000" },
{ ISAPNP_ANY_ID, ISAPNP_ANY_ID,
ISAPNP_VENDOR('P','N','P'), ISAPNP_FUNCTION(0x80d6),
(long) "Generic PNP" },
{ } /* terminate list */
};
MODULE_DEVICE_TABLE(isapnp, isapnp_clone_list);
#ifdef SUPPORT_NE_BAD_CLONES
/* A list of bad clones that we none-the-less recognize. */
static struct { const char *name8, *name16; unsigned char SAprefix[4];}
bad_clone_list[] __initdata = {
{"DE100", "DE200", {0x00, 0xDE, 0x01,}},
{"DE120", "DE220", {0x00, 0x80, 0xc8,}},
{"DFI1000", "DFI2000", {'D', 'F', 'I',}}, /* Original, eh? */
{"EtherNext UTP8", "EtherNext UTP16", {0x00, 0x00, 0x79}},
{"NE1000","NE2000-invalid", {0x00, 0x00, 0xd8}}, /* Ancient real NE1000. */
{"NN1000", "NN2000", {0x08, 0x03, 0x08}}, /* Outlaw no-name clone. */
{"4-DIM8","4-DIM16", {0x00,0x00,0x4d,}}, /* Outlaw 4-Dimension cards. */
{"Con-Intl_8", "Con-Intl_16", {0x00, 0x00, 0x24}}, /* Connect Int'nl */
{"ET-100","ET-200", {0x00, 0x45, 0x54}}, /* YANG and YA clone */
{"COMPEX","COMPEX16",{0x00,0x80,0x48}}, /* Broken ISA Compex cards */
{"E-LAN100", "E-LAN200", {0x00, 0x00, 0x5d}}, /* Broken ne1000 clones */
{"PCM-4823", "PCM-4823", {0x00, 0xc0, 0x6c}}, /* Broken Advantech MoBo */
{"REALTEK", "RTL8019", {0x00, 0x00, 0xe8}}, /* no-name with Realtek chip */
{"LCS-8834", "LCS-8836", {0x04, 0x04, 0x37}}, /* ShinyNet (SET) */
{0,}
};
#endif
/* ---- No user-serviceable parts below ---- */
#define NE_BASE (dev->base_addr)
#define NE_CMD 0x00
#define NE_DATAPORT 0x10 /* NatSemi-defined port window offset. */
#define NE_RESET 0x1f /* Issue a read to reset, a write to clear. */
#define NE_IO_EXTENT 0x20
#define NE1SM_START_PG 0x20 /* First page of TX buffer */
#define NE1SM_STOP_PG 0x40 /* Last page +1 of RX ring */
#define NESM_START_PG 0x40 /* First page of TX buffer */
#define NESM_STOP_PG 0x80 /* Last page +1 of RX ring */
int ne_probe(struct net_device *dev);
static int ne_probe1(struct net_device *dev, int ioaddr);
static int ne_probe_isapnp(struct net_device *dev);
static int ne_open(struct net_device *dev);
static int ne_close(struct net_device *dev);
static void ne_reset_8390(struct net_device *dev);
static void ne_get_8390_hdr(struct net_device *dev, struct e8390_pkt_hdr *hdr,
int ring_page);
static void ne_block_input(struct net_device *dev, int count,
struct sk_buff *skb, int ring_offset);
static void ne_block_output(struct net_device *dev, const int count,
const unsigned char *buf, const int start_page);
/* Probe for various non-shared-memory ethercards.
NEx000-clone boards have a Station Address PROM (SAPROM) in the packet
buffer memory space. NE2000 clones have 0x57,0x57 in bytes 0x0e,0x0f of
the SAPROM, while other supposed NE2000 clones must be detected by their
SA prefix.
Reading the SAPROM from a word-wide card with the 8390 set in byte-wide
mode results in doubled values, which can be detected and compensated for.
The probe is also responsible for initializing the card and filling
in the 'dev' and 'ei_status' structures.
We use the minimum memory size for some ethercard product lines, iff we can't
distinguish models. You can increase the packet buffer size by setting
PACKETBUF_MEMSIZE. Reported Cabletron packet buffer locations are:
E1010 starts at 0x100 and ends at 0x2000.
E1010-x starts at 0x100 and ends at 0x8000. ("-x" means "more memory")
E2010 starts at 0x100 and ends at 0x4000.
E2010-x starts at 0x100 and ends at 0xffff. */
int __init ne_probe(struct net_device *dev)
{
unsigned int base_addr = dev->base_addr;
SET_MODULE_OWNER(dev);
#if defined(CONFIG_NEC_OSPREY)
/* [jsun] Okay, this is a total hack. NE2k on NEC Osprey is
* at 0x03fe0300 (+ VR4181_PORT_BASE). However, the stupid
* include/linux/if.h:ifmap structure cannot handle u32 base value.
* We get the address chopped off.
*
* The real fix is to change ifmap structure. However,
* There are some concerns (from David Miller) as to binary
* compatibility. So I just hack this file for mvista tree only.
*/
if (dev->base_addr == 0x0300) {
base_addr = dev->base_addr = 0x03fe0300;
printk(KERN_WARNING "nec.c : Modify NE2K base addr from 0x300 to 0x03fe0300 for NEC Osprey board!\n");
}
#endif
/* First check any supplied i/o locations. User knows best. <cough> */
if (base_addr > 0x1ff) /* Check a single specified location. */
return ne_probe1(dev, base_addr);
else if (base_addr != 0) /* Don't probe at all. */
return -ENXIO;
/* Then look for any installed ISAPnP clones */
if (isapnp_present() && (ne_probe_isapnp(dev) == 0))
return 0;
#ifndef MODULE
/* Last resort. The semi-risky ISA auto-probe. */
for (base_addr = 0; netcard_portlist[base_addr] != 0; base_addr++) {
int ioaddr = netcard_portlist[base_addr];
if (ne_probe1(dev, ioaddr) == 0)
return 0;
}
#endif
return -ENODEV;
}
static int __init ne_probe_isapnp(struct net_device *dev)
{
int i;
for (i = 0; isapnp_clone_list[i].vendor != 0; i++) {
struct pci_dev *idev = NULL;
while ((idev = isapnp_find_dev(NULL,
isapnp_clone_list[i].vendor,
isapnp_clone_list[i].function,
idev))) {
/* Avoid already found cards from previous calls */
if (idev->prepare(idev))
continue;
if (idev->activate(idev))
continue;
/* if no irq, search for next */
if (idev->irq_resource[0].start == 0)
continue;
/* found it */
dev->base_addr = idev->resource[0].start;
dev->irq = idev->irq_resource[0].start;
printk(KERN_INFO "ne.c: ISAPnP reports %s at i/o %#lx, irq %d.\n",
(char *) isapnp_clone_list[i].driver_data,
dev->base_addr, dev->irq);
if (ne_probe1(dev, dev->base_addr) != 0) { /* Shouldn't happen. */
printk(KERN_ERR "ne.c: Probe of ISAPnP card at %#lx failed.\n", dev->base_addr);
return -ENXIO;
}
ei_status.priv = (unsigned long)idev;
break;
}
if (!idev)
continue;
return 0;
}
return -ENODEV;
}
static int __init ne_probe1(struct net_device *dev, int ioaddr)
{
int i;
unsigned char SA_prom[32];
int wordlength = 2;
const char *name = NULL;
int start_page, stop_page;
int neX000, ctron, copam, bad_card;
int reg0, ret;
static unsigned version_printed;
if (!request_region(ioaddr, NE_IO_EXTENT, dev->name))
return -EBUSY;
reg0 = inb_p(ioaddr);
if (reg0 == 0xFF) {
ret = -ENODEV;
goto err_out;
}
/* Do a preliminary verification that we have a 8390. */
{
int regd;
outb_p(E8390_NODMA+E8390_PAGE1+E8390_STOP, ioaddr + E8390_CMD);
regd = inb_p(ioaddr + 0x0d);
outb_p(0xff, ioaddr + 0x0d);
outb_p(E8390_NODMA+E8390_PAGE0, ioaddr + E8390_CMD);
inb_p(ioaddr + EN0_COUNTER0); /* Clear the counter by reading. */
if (inb_p(ioaddr + EN0_COUNTER0) != 0) {
outb_p(reg0, ioaddr);
outb_p(regd, ioaddr + 0x0d); /* Restore the old values. */
ret = -ENODEV;
goto err_out;
}
}
if (ei_debug && version_printed++ == 0)
printk(KERN_INFO "%s" KERN_INFO "%s", version1, version2);
printk(KERN_INFO "NE*000 ethercard probe at %#3x:", ioaddr);
/* A user with a poor card that fails to ack the reset, or that
does not have a valid 0x57,0x57 signature can still use this
without having to recompile. Specifying an i/o address along
with an otherwise unused dev->mem_end value of "0xBAD" will
cause the driver to skip these parts of the probe. */
bad_card = ((dev->base_addr != 0) && (dev->mem_end == 0xbad));
/* Reset card. Who knows what dain-bramaged state it was left in. */
{
unsigned long reset_start_time = jiffies;
/* DON'T change these to inb_p/outb_p or reset will fail on clones. */
outb(inb(ioaddr + NE_RESET), ioaddr + NE_RESET);
while ((inb_p(ioaddr + EN0_ISR) & ENISR_RESET) == 0)
if (jiffies - reset_start_time > 2*HZ/100) {
if (bad_card) {
printk(" (warning: no reset ack)");
break;
} else {
printk(" not found (no reset ack).\n");
ret = -ENODEV;
goto err_out;
}
}
outb_p(0xff, ioaddr + EN0_ISR); /* Ack all intr. */
}
/* Read the 16 bytes of station address PROM.
We must first initialize registers, similar to NS8390_init(eifdev, 0).
We can't reliably read the SAPROM address without this.
(I learned the hard way!). */
{
struct {unsigned char value, offset; } program_seq[] =
{
{E8390_NODMA+E8390_PAGE0+E8390_STOP, E8390_CMD}, /* Select page 0*/
{0x48, EN0_DCFG}, /* Set byte-wide (0x48) access. */
{0x00, EN0_RCNTLO}, /* Clear the count regs. */
{0x00, EN0_RCNTHI},
{0x00, EN0_IMR}, /* Mask completion irq. */
{0xFF, EN0_ISR},
{E8390_RXOFF, EN0_RXCR}, /* 0x20 Set to monitor */
{E8390_TXOFF, EN0_TXCR}, /* 0x02 and loopback mode. */
{32, EN0_RCNTLO},
{0x00, EN0_RCNTHI},
{0x00, EN0_RSARLO}, /* DMA starting at 0x0000. */
{0x00, EN0_RSARHI},
{E8390_RREAD+E8390_START, E8390_CMD},
};
for (i = 0; i < sizeof(program_seq)/sizeof(program_seq[0]); i++)
outb_p(program_seq[i].value, ioaddr + program_seq[i].offset);
}
for(i = 0; i < 32 /*sizeof(SA_prom)*/; i+=2) {
SA_prom[i] = inb(ioaddr + NE_DATAPORT);
SA_prom[i+1] = inb(ioaddr + NE_DATAPORT);
if (SA_prom[i] != SA_prom[i+1])
wordlength = 1;
}
if (wordlength == 2)
{
for (i = 0; i < 16; i++)
SA_prom[i] = SA_prom[i+i];
/* We must set the 8390 for word mode. */
outb_p(0x49, ioaddr + EN0_DCFG);
start_page = NESM_START_PG;
stop_page = NESM_STOP_PG;
} else {
start_page = NE1SM_START_PG;
stop_page = NE1SM_STOP_PG;
}
neX000 = (SA_prom[14] == 0x57 && SA_prom[15] == 0x57);
ctron = (SA_prom[0] == 0x00 && SA_prom[1] == 0x00 && SA_prom[2] == 0x1d);
copam = (SA_prom[14] == 0x49 && SA_prom[15] == 0x00);
/* Set up the rest of the parameters. */
if (neX000 || bad_card || copam) {
name = (wordlength == 2) ? "NE2000" : "NE1000";
}
else if (ctron)
{
name = (wordlength == 2) ? "Ctron-8" : "Ctron-16";
start_page = 0x01;
stop_page = (wordlength == 2) ? 0x40 : 0x20;
}
else
{
#ifdef SUPPORT_NE_BAD_CLONES
/* Ack! Well, there might be a *bad* NE*000 clone there.
Check for total bogus addresses. */
for (i = 0; bad_clone_list[i].name8; i++)
{
if (SA_prom[0] == bad_clone_list[i].SAprefix[0] &&
SA_prom[1] == bad_clone_list[i].SAprefix[1] &&
SA_prom[2] == bad_clone_list[i].SAprefix[2])
{
if (wordlength == 2)
{
name = bad_clone_list[i].name16;
} else {
name = bad_clone_list[i].name8;
}
break;
}
}
if (bad_clone_list[i].name8 == NULL)
{
printk(" not found (invalid signature %2.2x %2.2x).\n",
SA_prom[14], SA_prom[15]);
ret = -ENXIO;
goto err_out;
}
#else
printk(" not found.\n");
ret = -ENXIO;
goto err_out;
#endif
}
if (dev->irq < 2)
{
unsigned long cookie = probe_irq_on();
outb_p(0x50, ioaddr + EN0_IMR); /* Enable one interrupt. */
outb_p(0x00, ioaddr + EN0_RCNTLO);
outb_p(0x00, ioaddr + EN0_RCNTHI);
outb_p(E8390_RREAD+E8390_START, ioaddr); /* Trigger it... */
mdelay(10); /* wait 10ms for interrupt to propagate */
outb_p(0x00, ioaddr + EN0_IMR); /* Mask it again. */
dev->irq = probe_irq_off(cookie);
if (ei_debug > 2)
printk(" autoirq is %d\n", dev->irq);
} else if (dev->irq == 2)
/* Fixup for users that don't know that IRQ 2 is really IRQ 9,
or don't know which one to set. */
dev->irq = 9;
if (! dev->irq) {
printk(" failed to detect IRQ line.\n");
ret = -EAGAIN;
goto err_out;
}
/* Allocate dev->priv and fill in 8390 specific dev fields. */
if (ethdev_init(dev))
{
printk (" unable to get memory for dev->priv.\n");
ret = -ENOMEM;
goto err_out;
}
/* Snarf the interrupt now. There's no point in waiting since we cannot
share and the board will usually be enabled. */
ret = request_irq(dev->irq, ei_interrupt, 0, name, dev);
if (ret) {
printk (" unable to get IRQ %d (errno=%d).\n", dev->irq, ret);
goto err_out_kfree;
}
dev->base_addr = ioaddr;
for(i = 0; i < ETHER_ADDR_LEN; i++) {
printk(" %2.2x", SA_prom[i]);
dev->dev_addr[i] = SA_prom[i];
}
printk("\n%s: %s found at %#x, using IRQ %d.\n",
dev->name, name, ioaddr, dev->irq);
ei_status.name = name;
ei_status.tx_start_page = start_page;
ei_status.stop_page = stop_page;
ei_status.word16 = (wordlength == 2);
ei_status.rx_start_page = start_page + TX_PAGES;
#ifdef PACKETBUF_MEMSIZE
/* Allow the packet buffer size to be overridden by know-it-alls. */
ei_status.stop_page = ei_status.tx_start_page + PACKETBUF_MEMSIZE;
#endif
ei_status.reset_8390 = &ne_reset_8390;
ei_status.block_input = &ne_block_input;
ei_status.block_output = &ne_block_output;
ei_status.get_8390_hdr = &ne_get_8390_hdr;
ei_status.priv = 0;
dev->open = &ne_open;
dev->stop = &ne_close;
NS8390_init(dev, 0);
return 0;
err_out_kfree:
kfree(dev->priv);
dev->priv = NULL;
err_out:
release_region(ioaddr, NE_IO_EXTENT);
return ret;
}
static int ne_open(struct net_device *dev)
{
ei_open(dev);
return 0;
}
static int ne_close(struct net_device *dev)
{
if (ei_debug > 1)
printk(KERN_DEBUG "%s: Shutting down ethercard.\n", dev->name);
ei_close(dev);
return 0;
}
/* Hard reset the card. This used to pause for the same period that a
8390 reset command required, but that shouldn't be necessary. */
static void ne_reset_8390(struct net_device *dev)
{
unsigned long reset_start_time = jiffies;
if (ei_debug > 1)
printk(KERN_DEBUG "resetting the 8390 t=%ld...", jiffies);
/* DON'T change these to inb_p/outb_p or reset will fail on clones. */
outb(inb(NE_BASE + NE_RESET), NE_BASE + NE_RESET);
ei_status.txing = 0;
ei_status.dmaing = 0;
/* This check _should_not_ be necessary, omit eventually. */
while ((inb_p(NE_BASE+EN0_ISR) & ENISR_RESET) == 0)
if (jiffies - reset_start_time > 2*HZ/100) {
printk(KERN_WARNING "%s: ne_reset_8390() did not complete.\n", dev->name);
break;
}
outb_p(ENISR_RESET, NE_BASE + EN0_ISR); /* Ack intr. */
}
/* Grab the 8390 specific header. Similar to the block_input routine, but
we don't need to be concerned with ring wrap as the header will be at
the start of a page, so we optimize accordingly. */
static void ne_get_8390_hdr(struct net_device *dev, struct e8390_pkt_hdr *hdr, int ring_page)
{
int nic_base = dev->base_addr;
/* This *shouldn't* happen. If it does, it's the last thing you'll see */
if (ei_status.dmaing)
{
printk(KERN_EMERG "%s: DMAing conflict in ne_get_8390_hdr "
"[DMAstat:%d][irqlock:%d].\n",
dev->name, ei_status.dmaing, ei_status.irqlock);
return;
}
ei_status.dmaing |= 0x01;
outb_p(E8390_NODMA+E8390_PAGE0+E8390_START, nic_base+ NE_CMD);
outb_p(sizeof(struct e8390_pkt_hdr), nic_base + EN0_RCNTLO);
outb_p(0, nic_base + EN0_RCNTHI);
outb_p(0, nic_base + EN0_RSARLO); /* On page boundary */
outb_p(ring_page, nic_base + EN0_RSARHI);
outb_p(E8390_RREAD+E8390_START, nic_base + NE_CMD);
if (ei_status.word16)
insw(NE_BASE + NE_DATAPORT, hdr, sizeof(struct e8390_pkt_hdr)>>1);
else
insb(NE_BASE + NE_DATAPORT, hdr, sizeof(struct e8390_pkt_hdr));
outb_p(ENISR_RDC, nic_base + EN0_ISR); /* Ack intr. */
ei_status.dmaing &= ~0x01;
le16_to_cpus(&hdr->count);
}
/* Block input and output, similar to the Crynwr packet driver. If you
are porting to a new ethercard, look at the packet driver source for hints.
The NEx000 doesn't share the on-board packet memory -- you have to put
the packet out through the "remote DMA" dataport using outb. */
static void ne_block_input(struct net_device *dev, int count, struct sk_buff *skb, int ring_offset)
{
#ifdef NE_SANITY_CHECK
int xfer_count = count;
#endif
int nic_base = dev->base_addr;
char *buf = skb->data;
/* This *shouldn't* happen. If it does, it's the last thing you'll see */
if (ei_status.dmaing)
{
printk(KERN_EMERG "%s: DMAing conflict in ne_block_input "
"[DMAstat:%d][irqlock:%d].\n",
dev->name, ei_status.dmaing, ei_status.irqlock);
return;
}
ei_status.dmaing |= 0x01;
outb_p(E8390_NODMA+E8390_PAGE0+E8390_START, nic_base+ NE_CMD);
outb_p(count & 0xff, nic_base + EN0_RCNTLO);
outb_p(count >> 8, nic_base + EN0_RCNTHI);
outb_p(ring_offset & 0xff, nic_base + EN0_RSARLO);
outb_p(ring_offset >> 8, nic_base + EN0_RSARHI);
outb_p(E8390_RREAD+E8390_START, nic_base + NE_CMD);
if (ei_status.word16)
{
insw(NE_BASE + NE_DATAPORT,buf,count>>1);
if (count & 0x01)
{
buf[count-1] = inb(NE_BASE + NE_DATAPORT);
#ifdef NE_SANITY_CHECK
xfer_count++;
#endif
}
} else {
insb(NE_BASE + NE_DATAPORT, buf, count);
}
#ifdef NE_SANITY_CHECK
/* This was for the ALPHA version only, but enough people have
been encountering problems so it is still here. If you see
this message you either 1) have a slightly incompatible clone
or 2) have noise/speed problems with your bus. */
if (ei_debug > 1)
{
/* DMA termination address check... */
int addr, tries = 20;
do {
/* DON'T check for 'inb_p(EN0_ISR) & ENISR_RDC' here
-- it's broken for Rx on some cards! */
int high = inb_p(nic_base + EN0_RSARHI);
int low = inb_p(nic_base + EN0_RSARLO);
addr = (high << 8) + low;
if (((ring_offset + xfer_count) & 0xff) == low)
break;
} while (--tries > 0);
if (tries <= 0)
printk(KERN_WARNING "%s: RX transfer address mismatch,"
"%#4.4x (expected) vs. %#4.4x (actual).\n",
dev->name, ring_offset + xfer_count, addr);
}
#endif
outb_p(ENISR_RDC, nic_base + EN0_ISR); /* Ack intr. */
ei_status.dmaing &= ~0x01;
}
static void ne_block_output(struct net_device *dev, int count,
const unsigned char *buf, const int start_page)
{
int nic_base = NE_BASE;
unsigned long dma_start;
#ifdef NE_SANITY_CHECK
int retries = 0;
#endif
/* Round the count up for word writes. Do we need to do this?
What effect will an odd byte count have on the 8390?
I should check someday. */
if (ei_status.word16 && (count & 0x01))
count++;
/* This *shouldn't* happen. If it does, it's the last thing you'll see */
if (ei_status.dmaing)
{
printk(KERN_EMERG "%s: DMAing conflict in ne_block_output."
"[DMAstat:%d][irqlock:%d]\n",
dev->name, ei_status.dmaing, ei_status.irqlock);
return;
}
ei_status.dmaing |= 0x01;
/* We should already be in page 0, but to be safe... */
outb_p(E8390_PAGE0+E8390_START+E8390_NODMA, nic_base + NE_CMD);
#ifdef NE_SANITY_CHECK
retry:
#endif
#ifdef NE8390_RW_BUGFIX
/* Handle the read-before-write bug the same way as the
Crynwr packet driver -- the NatSemi method doesn't work.
Actually this doesn't always work either, but if you have
problems with your NEx000 this is better than nothing! */
outb_p(0x42, nic_base + EN0_RCNTLO);
outb_p(0x00, nic_base + EN0_RCNTHI);
outb_p(0x42, nic_base + EN0_RSARLO);
outb_p(0x00, nic_base + EN0_RSARHI);
outb_p(E8390_RREAD+E8390_START, nic_base + NE_CMD);
/* Make certain that the dummy read has occurred. */
udelay(6);
#endif
outb_p(ENISR_RDC, nic_base + EN0_ISR);
/* Now the normal output. */
outb_p(count & 0xff, nic_base + EN0_RCNTLO);
outb_p(count >> 8, nic_base + EN0_RCNTHI);
outb_p(0x00, nic_base + EN0_RSARLO);
outb_p(start_page, nic_base + EN0_RSARHI);
outb_p(E8390_RWRITE+E8390_START, nic_base + NE_CMD);
if (ei_status.word16) {
outsw(NE_BASE + NE_DATAPORT, buf, count>>1);
} else {
outsb(NE_BASE + NE_DATAPORT, buf, count);
}
dma_start = jiffies;
#ifdef NE_SANITY_CHECK
/* This was for the ALPHA version only, but enough people have
been encountering problems so it is still here. */
if (ei_debug > 1)
{
/* DMA termination address check... */
int addr, tries = 20;
do {
int high = inb_p(nic_base + EN0_RSARHI);
int low = inb_p(nic_base + EN0_RSARLO);
addr = (high << 8) + low;
if ((start_page << 8) + count == addr)
break;
} while (--tries > 0);
if (tries <= 0)
{
printk(KERN_WARNING "%s: Tx packet transfer address mismatch,"
"%#4.4x (expected) vs. %#4.4x (actual).\n",
dev->name, (start_page << 8) + count, addr);
if (retries++ == 0)
goto retry;
}
}
#endif
while ((inb_p(nic_base + EN0_ISR) & ENISR_RDC) == 0)
if (jiffies - dma_start > 2*HZ/100) { /* 20ms */
printk(KERN_WARNING "%s: timeout waiting for Tx RDC.\n", dev->name);
ne_reset_8390(dev);
NS8390_init(dev,1);
break;
}
outb_p(ENISR_RDC, nic_base + EN0_ISR); /* Ack intr. */
ei_status.dmaing &= ~0x01;
return;
}
#ifdef MODULE
#define MAX_NE_CARDS 4 /* Max number of NE cards per module */
static struct net_device dev_ne[MAX_NE_CARDS];
static int io[MAX_NE_CARDS];
static int irq[MAX_NE_CARDS];
static int bad[MAX_NE_CARDS]; /* 0xbad = bad sig or no reset ack */
MODULE_PARM(io, "1-" __MODULE_STRING(MAX_NE_CARDS) "i");
MODULE_PARM(irq, "1-" __MODULE_STRING(MAX_NE_CARDS) "i");
MODULE_PARM(bad, "1-" __MODULE_STRING(MAX_NE_CARDS) "i");
MODULE_PARM_DESC(io, "NEx000 I/O base address(es),required");
MODULE_PARM_DESC(irq, "NEx000 IRQ number(s)");
MODULE_PARM_DESC(bad, "NEx000 accept bad clone(s)");
/* This is set up so that no ISA autoprobe takes place. We can't guarantee
that the ne2k probe is the last 8390 based probe to take place (as it
is at boot) and so the probe will get confused by any other 8390 cards.
ISA device autoprobes on a running machine are not recommended anyway. */
int init_module(void)
{
int this_dev, found = 0;
for (this_dev = 0; this_dev < MAX_NE_CARDS; this_dev++) {
struct net_device *dev = &dev_ne[this_dev];
dev->irq = irq[this_dev];
dev->mem_end = bad[this_dev];
dev->base_addr = io[this_dev];
dev->init = ne_probe;
if (register_netdev(dev) == 0) {
found++;
continue;
}
if (found != 0) { /* Got at least one. */
return 0;
}
if (io[this_dev] != 0)
printk(KERN_WARNING "ne.c: No NE*000 card found at i/o = %#x\n", io[this_dev]);
else
printk(KERN_NOTICE "ne.c: You must supply \"io=0xNNN\" value(s) for ISA cards.\n");
return -ENXIO;
}
return 0;
}
void cleanup_module(void)
{
int this_dev;
for (this_dev = 0; this_dev < MAX_NE_CARDS; this_dev++) {
struct net_device *dev = &dev_ne[this_dev];
if (dev->priv != NULL) {
void *priv = dev->priv;
struct pci_dev *idev = (struct pci_dev *)ei_status.priv;
if (idev)
idev->deactivate(idev);
free_irq(dev->irq, dev);
release_region(dev->base_addr, NE_IO_EXTENT);
unregister_netdev(dev);
kfree(priv);
}
}
}
#endif /* MODULE */
/*
* Local variables:
* compile-command: "gcc -DKERNEL -Wall -O6 -fomit-frame-pointer -I/usr/src/linux/net/tcp -c ne.c"
* version-control: t
* kept-new-versions: 5
* End:
*/
|
|
From: Jun S. <ju...@us...> - 2001-09-22 16:35:18
|
Update of /cvsroot/linux-mips/linux/arch/mips/vr4181 In directory usw-pr-cvs1:/tmp/cvs-serv5895/arch/mips/vr4181 Added Files: TODO Log Message: Osprey kernel more or less works now, but very unstable. See TODO file. --- NEW FILE: TODO --- ---------------------------------------------------------------------- Osprey: [09/22/2001] Jun Sun, js...@mv... Kernel kind of works now with nfs root fs, very unstable. Choked before reaching userland yet. TODO: . more debugging . remove proprietary serial driver, using the common one . figure out and settle on a nice way to work around ne.c problem See CONFIG_OSPREY in drivers/net/ne.c file. . move to use the new irq . move to use the new time . re-partition the common and osprey part. Note osprey has a debug board which, presumably, other vr4181-based devices do not have. . CODE CLEAN UP! Remove some old vr-ism code. ---------------------------------------------------------------------- |
|
From: Jun S. <ju...@us...> - 2001-09-22 16:35:18
|
Update of /cvsroot/linux-mips/linux/arch/mips/configs In directory usw-pr-cvs1:/tmp/cvs-serv5895/arch/mips/configs Added Files: defconfig-osprey Log Message: Osprey kernel more or less works now, but very unstable. See TODO file. --- NEW FILE: defconfig-osprey --- # # Automatically generated by make menuconfig: don't edit # CONFIG_MIPS=y # CONFIG_SMP is not set # # Code maturity level options # CONFIG_EXPERIMENTAL=y # # Machine selection # # CONFIG_ACER_PICA_61 is not set # CONFIG_ALGOR_P4032 is not set # CONFIG_BAGET_MIPS is not set # CONFIG_COBALT_MICRO_SERVER is not set # CONFIG_DECSTATION is not set # CONFIG_DDB5074 is not set CONFIG_NEC_OSPREY=y # CONFIG_NEC_EAGLE is not set # CONFIG_NEC_KORVA is not set # CONFIG_MIPS_EV96100 is not set # CONFIG_MIPS_EV64120 is not set # CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_NINO is not set # CONFIG_PS2 is not set # CONFIG_MIPS_MAGNUM_4000 is not set # CONFIG_MOMENCO_OCELOT is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set # CONFIG_OLIVETTI_M700 is not set # CONFIG_SGI_IP22 is not set # CONFIG_SNI_RM200_PCI is not set # CONFIG_MIPS_ITE8172 is not set # CONFIG_MIPS_IVR is not set # CONFIG_MIPS_PB1000 is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y # CONFIG_RWSEM_XCHGADD_ALGORITHM is not set # CONFIG_MCA is not set # CONFIG_SBUS is not set CONFIG_CPU_VR41XX=y CONFIG_VR4181=y CONFIG_ISA=y CONFIG_SERIAL=y CONFIG_DUMMY_KEYB=y # CONFIG_SCSI is not set CONFIG_EISA=y # CONFIG_PCI is not set # CONFIG_I8259 is not set # # Loadable module support # CONFIG_MODULES=y # CONFIG_MODVERSIONS is not set CONFIG_KMOD=y # # CPU selection # # CONFIG_CPU_R3000 is not set # CONFIG_CPU_R6000 is not set CONFIG_CPU_VR41XX=y # CONFIG_CPU_R4300 is not set # CONFIG_CPU_R4X00 is not set # CONFIG_CPU_R5000 is not set # CONFIG_CPU_R5432 is not set # CONFIG_CPU_R5900 is not set # CONFIG_CPU_RM7000 is not set # CONFIG_CPU_NEVADA is not set # CONFIG_CPU_R10000 is not set # CONFIG_CPU_SB1 is not set # CONFIG_CPU_MIPS32 is not set # CONFIG_CPU_MIPS64 is not set # CONFIG_CPU_ADVANCED is not set # CONFIG_CPU_HAS_LLSC is not set # CONFIG_CPU_HAS_LLDSCD is not set # CONFIG_CPU_HAS_WB is not set # # General setup # CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_KCORE_ELF=y CONFIG_ELF_KERNEL=y # CONFIG_BINFMT_AOUT is not set CONFIG_BINFMT_ELF=y # CONFIG_BINFMT_MISC is not set CONFIG_NET=y # CONFIG_HOTPLUG is not set # CONFIG_PCMCIA is not set CONFIG_SYSVIPC=y # CONFIG_BSD_PROCESS_ACCT is not set CONFIG_SYSCTL=y # # Plug and Play configuration # # CONFIG_PNP is not set # CONFIG_ISAPNP is not set # CONFIG_PNPBIOS is not set # # Memory Technology Devices (MTD) # # CONFIG_MTD is not set # # Parallel port support # # CONFIG_PARPORT is not set # # Block devices # # CONFIG_BLK_DEV_FD is not set # CONFIG_BLK_DEV_XD is not set # CONFIG_PARIDE is not set # CONFIG_BLK_CPQ_DA is not set # CONFIG_BLK_CPQ_CISS_DA is not set # CONFIG_BLK_DEV_DAC960 is not set # CONFIG_BLK_DEV_LOOP is not set # CONFIG_BLK_DEV_NBD is not set # CONFIG_BLK_DEV_RAM is not set # CONFIG_BLK_DEV_INITRD is not set # # Multi-device support (RAID and LVM) # # CONFIG_MD is not set # CONFIG_BLK_DEV_MD is not set # CONFIG_MD_LINEAR is not set # CONFIG_MD_RAID0 is not set # CONFIG_MD_RAID1 is not set # CONFIG_MD_RAID5 is not set # CONFIG_BLK_DEV_LVM is not set # # Networking options # CONFIG_PACKET=y # CONFIG_PACKET_MMAP is not set # CONFIG_NETLINK is not set # CONFIG_NETFILTER is not set # CONFIG_FILTER is not set CONFIG_UNIX=y CONFIG_INET=y # CONFIG_IP_MULTICAST is not set # CONFIG_IP_ADVANCED_ROUTER is not set CONFIG_IP_PNP=y # CONFIG_IP_PNP_DHCP is not set CONFIG_IP_PNP_BOOTP=y # CONFIG_IP_PNP_RARP is not set # CONFIG_NET_IPIP is not set # CONFIG_NET_IPGRE is not set # CONFIG_INET_ECN is not set # CONFIG_SYN_COOKIES is not set # CONFIG_IPV6 is not set # CONFIG_KHTTPD is not set # CONFIG_ATM is not set # CONFIG_IPX is not set # CONFIG_ATALK is not set # CONFIG_DECNET is not set # CONFIG_BRIDGE is not set # CONFIG_X25 is not set # CONFIG_LAPB is not set # CONFIG_LLC is not set # CONFIG_NET_DIVERT is not set # CONFIG_ECONET is not set # CONFIG_WAN_ROUTER is not set # CONFIG_NET_FASTROUTE is not set # CONFIG_NET_HW_FLOWCONTROL is not set # # QoS and/or fair queueing # # CONFIG_NET_SCHED is not set # # Telephony Support # # CONFIG_PHONE is not set # CONFIG_PHONE_IXJ is not set # # ATA/IDE/MFM/RLL support # # CONFIG_IDE is not set # CONFIG_BLK_DEV_IDE_MODES is not set # CONFIG_BLK_DEV_HD is not set # # SCSI support # # CONFIG_SCSI is not set # # I2O device support # # CONFIG_I2O is not set # CONFIG_I2O_BLOCK is not set # CONFIG_I2O_LAN is not set # CONFIG_I2O_SCSI is not set # CONFIG_I2O_PROC is not set # # Network device support # CONFIG_NETDEVICES=y # # ARCnet devices # # CONFIG_ARCNET is not set # CONFIG_DUMMY is not set # CONFIG_BONDING is not set # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set # # Ethernet (10 or 100Mbit) # CONFIG_NET_ETHERNET=y # CONFIG_ARM_AM79C961A is not set # CONFIG_SUNLANCE is not set # CONFIG_SUNBMAC is not set # CONFIG_SUNQE is not set # CONFIG_SUNLANCE is not set # CONFIG_SUNGEM is not set # CONFIG_NET_VENDOR_3COM is not set # CONFIG_LANCE is not set # CONFIG_NET_VENDOR_SMC is not set # CONFIG_NET_VENDOR_RACAL is not set # CONFIG_AT1700 is not set # CONFIG_DEPCA is not set # CONFIG_HP100 is not set CONFIG_NET_ISA=y # CONFIG_E2100 is not set # CONFIG_EWRK3 is not set # CONFIG_EEXPRESS is not set # CONFIG_EEXPRESS_PRO is not set # CONFIG_HPLAN_PLUS is not set # CONFIG_HPLAN is not set # CONFIG_ETH16I is not set CONFIG_NE2000=y # CONFIG_NET_PCI is not set # CONFIG_NET_POCKET is not set # # Ethernet (1000 Mbit) # # CONFIG_ACENIC is not set # CONFIG_ACENIC_OMIT_TIGON_I is not set # CONFIG_DL2K is not set # CONFIG_MYRI_SBUS is not set # CONFIG_HAMACHI is not set # CONFIG_YELLOWFIN is not set # CONFIG_SK98LIN is not set # CONFIG_FDDI is not set # CONFIG_HIPPI is not set # CONFIG_PLIP is not set # CONFIG_PPP is not set # CONFIG_SLIP is not set # # Wireless LAN (non-hamradio) # # CONFIG_NET_RADIO is not set # # Token Ring devices # # CONFIG_TR is not set # CONFIG_NET_FC is not set # CONFIG_RCPCI is not set # CONFIG_SHAPER is not set # # Wan interfaces # # CONFIG_WAN is not set # # Amateur Radio support # # CONFIG_HAMRADIO is not set # # IrDA (infrared) support # # CONFIG_IRDA is not set # # ISDN subsystem # # CONFIG_ISDN is not set # # Old CD-ROM drivers (not SCSI, not IDE) # # CONFIG_CD_NO_IDESCSI is not set # # Character devices # CONFIG_VT=y # CONFIG_VT_CONSOLE is not set CONFIG_SERIAL=y CONFIG_SERIAL_CONSOLE=y # CONFIG_SERIAL_EXTENDED is not set # CONFIG_SERIAL_NONSTANDARD is not set CONFIG_UNIX98_PTYS=y CONFIG_UNIX98_PTY_COUNT=256 # # I2C support # # CONFIG_I2C is not set # # Mice # # CONFIG_BUSMOUSE is not set # CONFIG_MOUSE is not set # # Joysticks # # CONFIG_JOYSTICK is not set # CONFIG_QIC02_TAPE is not set # # Watchdog Cards # # CONFIG_WATCHDOG is not set # CONFIG_INTEL_RNG is not set # CONFIG_NVRAM is not set # CONFIG_RTC is not set # CONFIG_DTLK is not set # CONFIG_R3964 is not set # CONFIG_APPLICOM is not set # CONFIG_SONYPI is not set # # Ftape, the floppy tape device driver # # CONFIG_FTAPE is not set # CONFIG_AGP is not set # CONFIG_DRM is not set # # Multimedia devices # # CONFIG_VIDEO_DEV is not set # # File systems # # CONFIG_QUOTA is not set # CONFIG_AUTOFS_FS is not set # CONFIG_AUTOFS4_FS is not set # CONFIG_REISERFS_FS is not set # CONFIG_REISERFS_CHECK is not set # CONFIG_ADFS_FS is not set # CONFIG_ADFS_FS_RW is not set # CONFIG_AFFS_FS is not set # CONFIG_HFS_FS is not set # CONFIG_BFS_FS is not set # CONFIG_FAT_FS is not set # CONFIG_MSDOS_FS is not set # CONFIG_UMSDOS_FS is not set # CONFIG_VFAT_FS is not set # CONFIG_EFS_FS is not set # CONFIG_JFFS_FS is not set # CONFIG_JFFS2_FS is not set # CONFIG_CRAMFS is not set # CONFIG_TMPFS is not set # CONFIG_RAMFS is not set # CONFIG_ISO9660_FS is not set # CONFIG_JOLIET is not set # CONFIG_MINIX_FS is not set # CONFIG_VXFS_FS is not set # CONFIG_NTFS_FS is not set # CONFIG_NTFS_RW is not set # CONFIG_HPFS_FS is not set CONFIG_PROC_FS=y # CONFIG_DEVFS_FS is not set # CONFIG_DEVFS_MOUNT is not set # CONFIG_DEVFS_DEBUG is not set CONFIG_DEVPTS_FS=y # CONFIG_QNX4FS_FS is not set # CONFIG_QNX4FS_RW is not set # CONFIG_ROMFS_FS is not set CONFIG_EXT2_FS=y # CONFIG_SYSV_FS is not set # CONFIG_UDF_FS is not set # CONFIG_UDF_RW is not set # CONFIG_UFS_FS is not set # CONFIG_UFS_FS_WRITE is not set # # Network File Systems # # CONFIG_CODA_FS is not set CONFIG_NFS_FS=y # CONFIG_NFS_V3 is not set CONFIG_ROOT_NFS=y CONFIG_NFSD=y # CONFIG_NFSD_V3 is not set CONFIG_SUNRPC=y CONFIG_LOCKD=y # CONFIG_SMB_FS is not set # CONFIG_NCP_FS is not set # CONFIG_NCPFS_PACKET_SIGNING is not set # CONFIG_NCPFS_IOCTL_LOCKING is not set # CONFIG_NCPFS_STRONG is not set # CONFIG_NCPFS_NFS_NS is not set # CONFIG_NCPFS_OS2_NS is not set # CONFIG_NCPFS_SMALLDOS is not set # CONFIG_NCPFS_NLS is not set # CONFIG_NCPFS_EXTRAS is not set # # Partition Types # # CONFIG_PARTITION_ADVANCED is not set CONFIG_MSDOS_PARTITION=y # CONFIG_SMB_NLS is not set # CONFIG_NLS is not set # # Console drivers # # CONFIG_VGA_CONSOLE is not set # CONFIG_MDA_CONSOLE is not set # # Frame-buffer support # # CONFIG_FB is not set # # Sound # # CONFIG_SOUND is not set # # USB support # # CONFIG_USB is not set # # Input core support # # CONFIG_INPUT is not set # # Kernel hacking # CONFIG_CROSSCOMPILE=y # CONFIG_REMOTE_DEBUG is not set # CONFIG_GDB_CONSOLE is not set CONFIG_LL_DEBUG=y # CONFIG_MAGIC_SYSRQ is not set # CONFIG_MIPS_UNCACHED is not set |
|
From: Jun S. <ju...@us...> - 2001-09-22 16:35:18
|
Update of /cvsroot/linux-mips/linux/arch/mips
In directory usw-pr-cvs1:/tmp/cvs-serv5895/arch/mips
Modified Files:
Makefile config.in
Log Message:
Osprey kernel more or less works now, but very unstable. See TODO file.
Index: Makefile
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/Makefile,v
retrieving revision 1.16
retrieving revision 1.17
diff -u -d -r1.16 -r1.17
--- Makefile 2001/09/16 03:28:13 1.16
+++ Makefile 2001/09/22 16:35:15 1.17
@@ -211,9 +211,9 @@
# NEC Osprey (vr4181) board
#
ifdef CONFIG_NEC_OSPREY
-SUBDIRS += arch/mips/vr41xx arch/mips/vr41xx/vr4181
-LIBS += arch/mips/vr41xx/vr41xx.o \
- arch/mips/vr41xx/vr4181/vr4181.o
+SUBDIRS += arch/mips/vr4181/common arch/mips/vr4181/osprey
+LIBS += arch/mips/vr4181/common/vr4181.o \
+ arch/mips/vr4181/osprey/osprey.o
LOADADDR += 0x80014000
endif
Index: config.in
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/config.in,v
retrieving revision 1.22
retrieving revision 1.23
diff -u -d -r1.22 -r1.23
--- config.in 2001/09/12 16:18:23 1.22
+++ config.in 2001/09/22 16:35:15 1.23
@@ -183,6 +183,7 @@
define_bool CONFIG_VR4181 y
define_bool CONFIG_ISA y
define_bool CONFIG_SERIAL y
+ define_bool CONFIG_DUMMY_KEYB y
define_bool CONFIG_SCSI n
fi
if [ "$CONFIG_NEC_EAGLE" = "y" ]; then
|
|
From: Jun S. <ju...@us...> - 2001-09-22 16:35:18
|
Update of /cvsroot/linux-mips/linux/arch/mips/vr4181/common
In directory usw-pr-cvs1:/tmp/cvs-serv5895/arch/mips/vr4181/common
Modified Files:
irq.c Makefile
Log Message:
Osprey kernel more or less works now, but very unstable. See TODO file.
Index: irq.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/vr4181/common/irq.c,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- irq.c 2001/09/22 04:27:15 1.1
+++ irq.c 2001/09/22 16:35:15 1.2
@@ -49,7 +49,7 @@
// it's a cpu interrupt
unsigned short newstatus = read_32bit_cp0_register(CP0_STATUS);
newstatus &= ~((unsigned short)1 << (irq + 8));
- set_cp0_status(ST0_IM, newstatus);
+ change_cp0_status(ST0_IM, newstatus);
} else {
if (irq < 40) {
// it's an ICU interrupt
@@ -79,7 +79,7 @@
// it's a cpu interrupt
unsigned short newstatus = read_32bit_cp0_register(CP0_STATUS);
newstatus |= ((unsigned short)1 << (irq + 8));
- set_cp0_status(ST0_IM, newstatus);
+ change_cp0_status(ST0_IM, newstatus);
} else {
if (irq < 40) {
// it's an ICU interrupt
@@ -120,11 +120,6 @@
static irq_info_t irq_info[VR4181_IRQ_MAX + 1];
-void inline disable_irq_nosync(unsigned int irq)
-{
- disable_irq(irq);
-}
-
void disable_irq(unsigned int irq_nr)
{
unsigned long flags;
@@ -387,7 +382,7 @@
// and finishes bit-processing irq_mask_probe at the same time
save_and_cli(flags);
tmp = read_32bit_cp0_register(CP0_STATUS);
- set_cp0_status(ST0_IM, tmp & irq_mask_probe[0]);
+ change_cp0_status(ST0_IM, tmp & irq_mask_probe[0]);
irq_mask_probe[0] |= tmp;
tmp = *VR4181_MSYSINT1REG;
*VR4181_MSYSINT1REG = tmp & irq_mask_probe[1];
Index: Makefile
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/vr4181/common/Makefile,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- Makefile 2001/09/22 04:27:15 1.1
+++ Makefile 2001/09/22 16:35:15 1.2
@@ -13,6 +13,6 @@
O_TARGET:= vr4181.o
-obj-y := irq.o kbd_no.o serial.o time.o
+obj-y := irq.o serial.o time.o
include $(TOPDIR)/Rules.make
|
|
From: Jun S. <ju...@us...> - 2001-09-22 04:27:19
|
Update of /cvsroot/linux-mips/linux/include/asm-mips/vr41xx In directory usw-pr-cvs1:/tmp/cvs-serv27047/include/asm-mips/vr41xx Removed Files: vr4121.h vr4122.h vr4181.h vr41xx.h Log Message: Initial re-structuring of vr41xx directory. More are coming to actually get Osprey/Eagle building and running. --- vr4121.h DELETED --- --- vr4122.h DELETED --- --- vr4181.h DELETED --- --- vr41xx.h DELETED --- |
|
From: Jun S. <ju...@us...> - 2001-09-22 04:27:19
|
Update of /cvsroot/linux-mips/linux/include/asm-mips/vr4122
In directory usw-pr-cvs1:/tmp/cvs-serv27047/include/asm-mips/vr4122
Added Files:
eagle.h vr4122.h
Log Message:
Initial re-structuring of vr41xx directory. More are coming to
actually get Osprey/Eagle building and running.
--- NEW FILE: eagle.h ---
/*
*
* BRIEF MODULE DESCRIPTION
* Include file for NEC Eagle board.
*
* Copyright 2001 MontaVista Software Inc.
* Author: Yoichi Yuasa
* yy...@mv... or so...@mv...
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef __ASM_NEC_EAGLE_H
#define __ASM_NEC_EAGLE_H
/*
* Memory Mapping
*/
#define VR4122_EXTERNAL_IO_BZSE 0x0a000000
#define VR4122_EXTERNAL_IO_SIZE 0x04000000
#define VR4122_INTERNAL_IO_BASE 0x0f000000
#define VR4122_INTERNAL_IO_SIZE 0x01000000
#define VR4122_PCI_MEM_BASE 0x10000000
#define VR4122_PCI_MEM_SIZE 0x06000000
#define VR4122_PCI_IO_BASE 0x16000000
#define VR4122_PCI_IO_SIZE 0x02000000
#define VR4122_ROM_BASE 0x1c000000
#define VR4122_ROM_SIZE 0x04000000
#define VR4122_IO_PORT_BASE KSEG1ADDR(VR4122_PCI_IO_BASE)
/*
* Interrupt Number
*/
#define VR4122_IRQ_VRC4173 VR4122_IRQ_GPIO1
#define VR4122_IRQ_MQ200 VR4122_IRQ_GPIO4
#define VR4122_IRQ_FPGA VR4122_IRQ_GPIO5
#define VR4122_IRQ_PCI VR4122_IRQ_GPIO5
#define VR4122_IRQ_ETHR VR4122_IRQ_GPIO5
#define VR4122_IRQ_SIO VR4122_IRQ_GPIO8
#define VR4122_IRQ_DCD VR4122_IRQ_GPIO15
/*
* On board Devices I/O Mapping
*/
#define NEC_EAGLE_SIO1RB KSEG1ADDR(0x0DFFFEC0)
#define NEC_EAGLE_SIO1TH KSEG1ADDR(0x0DFFFEC0)
#define NEC_EAGLE_SIO1IE KSEG1ADDR(0x0DFFFEC2)
#define NEC_EAGLE_SIO1IID KSEG1ADDR(0x0DFFFEC4)
#define NEC_EAGLE_SIO1FC KSEG1ADDR(0x0DFFFEC4)
#define NEC_EAGLE_SIO1LC KSEG1ADDR(0x0DFFFEC6)
#define NEC_EAGLE_SIO1MC KSEG1ADDR(0x0DFFFEC8)
#define NEC_EAGLE_SIO1LS KSEG1ADDR(0x0DFFFECA)
#define NEC_EAGLE_SIO1MS KSEG1ADDR(0x0DFFFECC)
#define NEC_EAGLE_SIO1SC KSEG1ADDR(0x0DFFFECE)
#define NEC_EAGLE_SIO2TH KSEG1ADDR(0x0DFFFED0)
#define NEC_EAGLE_SIO2IE KSEG1ADDR(0x0DFFFED2)
#define NEC_EAGLE_SIO2IID KSEG1ADDR(0x0DFFFED4)
#define NEC_EAGLE_SIO2FC KSEG1ADDR(0x0DFFFED4)
#define NEC_EAGLE_SIO2LC KSEG1ADDR(0x0DFFFED6)
#define NEC_EAGLE_SIO2MC KSEG1ADDR(0x0DFFFED8)
#define NEC_EAGLE_SIO2LS KSEG1ADDR(0x0DFFFEDA)
#define NEC_EAGLE_SIO2MS KSEG1ADDR(0x0DFFFEDC)
#define NEC_EAGLE_SIO2SC KSEG1ADDR(0x0DFFFEDE)
#define NEC_EAGLE_PIOPP_DATA KSEG1ADDR(0x0DFFFEE0)
#define NEC_EAGLE_PIOPP_STATUS KSEG1ADDR(0x0DFFFEE2)
#define NEC_EAGLE_PIOPP_CNT KSEG1ADDR(0x0DFFFEE4)
#define NEC_EAGLE_PIOPP_EPPADDR KSEG1ADDR(0x0DFFFEE6)
#define NEC_EAGLE_PIOPP_EPPDATA0 KSEG1ADDR(0x0DFFFEE8)
#define NEC_EAGLE_PIOPP_EPPDATA1 KSEG1ADDR(0x0DFFFEEA)
#define NEC_EAGLE_PIOPP_EPPDATA2 KSEG1ADDR(0x0DFFFEEC)
#define NEC_EAGLE_PIOECP_DATA KSEG1ADDR(0x0DFFFEF0)
#define NEC_EAGLE_PIOECP_CONFIG KSEG1ADDR(0x0DFFFEF2)
#define NEC_EAGLE_PIOECP_EXTCNT KSEG1ADDR(0x0DFFFEF4)
/*
* FLSHCNT Register
*/
#define NEC_EAGLE_FLSHCNT KSEG1ADDR(0x0DFFFFA0)
#define NEC_EAGLE_FLSHCNT_FRDY 0x80
#define NEC_EAGLE_FLSHCNT_VPPE 0x40
#define NEC_EAGLE_FLSHCNT_WP2 0x01
/*
* FLSHBANK Register
*/
#define NEC_EAGLE_FLSHBANK KSEG1ADDR(0x0DFFFFA4)
#define NEC_EAGLE_FLSHBANK_S_BANK2 0x40
#define NEC_EAGLE_FLSHBANK_S_BANK1 0x20
#define NEC_EAGLE_FLSHBANK_BNKQ4 0x10
#define NEC_EAGLE_FLSHBANK_BNKQ3 0x08
#define NEC_EAGLE_FLSHBANK_BNKQ2 0x04
#define NEC_EAGLE_FLSHBANK_BNKQ1 0x02
#define NEC_EAGLE_FLSHBANK_BNKQ0 0x01
/*
* SWITCH Setting Register
*/
#define NEC_EAGLE_SWTCHSET KSEG1ADDR(0x0DFFFFA8)
#define NEC_EAGLE_SWTCHSET_DP2SW4 0x80
#define NEC_EAGLE_SWTCHSET_DP2SW3 0x40
#define NEC_EAGLE_SWTCHSET_DP2SW2 0x20
#define NEC_EAGLE_SWTCHSET_DP2SW1 0x10
#define NEC_EAGLE_SWTCHSET_DP1SW4 0x08
#define NEC_EAGLE_SWTCHSET_DP1SW3 0x04
#define NEC_EAGLE_SWTCHSET_DP1SW2 0x02
#define NEC_EAGLE_SWTCHSET_DP1SW1 0x01
/*
* PPT Parallel Port Device Controller
*/
#define NEC_EAGLE_PPT_WRITE_DATA KSEG1ADDR(0x0DFFFFB0)
#define NEC_EAGLE_PPT_READ_DATA KSEG1ADDR(0x0DFFFFB2)
#define NEC_EAGLE_PPT_CNT KSEG1ADDR(0x0DFFFFB4)
#define NEC_EAGLE_PPT_CNT2 KSEG1ADDR(0x0DFFFFB4)
/* Control Register */
#define NEC_EAGLE_PPT_INTMSK 0x20
#define NEC_EAGLE_PPT_PARIINT 0x10
#define NEC_EAGLE_PPT_SELECTIN 0x08
#define NEC_EAGLE_PPT_INIT 0x04
#define NEC_EAGLE_PPT_AUTOFD 0x02
#define NEC_EAGLE_PPT_STROBE 0x01
/* Control Rgister 2 */
#define NEC_EAGLE_PPT_PAREN 0x80
#define NEC_EAGLE_PPT_AUTOEN 0x20
#define NEC_EAGLE_PPT_BUSY 0x10
#define NEC_EAGLE_PPT_ACK 0x08
#define NEC_EAGLE_PPT_PE 0x04
#define NEC_EAGLE_PPT_SELECT 0x02
#define NEC_EAGLE_PPT_FAULT 0x01
/*
* LEDWR Register
*/
#define NEC_EAGLE_LEDWR1 KSEG1ADDR(0x0DFFFFC0)
#define NEC_EAGLE_LEDWR2 KSEG1ADDR(0x0DFFFFC4)
/*
* SDBINT Register
*/
#define NEC_EAGLE_SDBINT KSEG1ADDR(0x0DFFFFD0)
#define NEC_EAGLE_SDBINT_PARINT 0x20
#define NEC_EAGLE_SDBINT_SIO2INT 0x10
#define NEC_EAGLE_SDBINT_SIO1INT 0x08
#define NEC_EAGLE_SDBINT_ENUM 0x04
#define NEC_EAGLE_SDBINT_DEG 0x02
/*
* SDB INTMSK Register
*/
#define NEC_EAGLE_SDBINTMASK KSEG1ADDR(0x0DFFFFD4)
#define NEC_EAGLE_SDBINTMASK_MSKPAR 0x20
#define NEC_EAGLE_SDBINTMASK_MSKSIO2 0x10
#define NEC_EAGLE_SDBINTMASK_MSKSIO1 0x08
#define NEC_EAGLE_SDBINTMASK_MSKENUM 0x04
#define NEC_EAGLE_SDBINTMASK_MSKDEG 0x02
/*
* RSTREG Register
*/
#define NEC_EAGLE_RSTREG KSEG1ADDR(0x0DFFFFD8)
#define NEC_EAGLE_RST_RSTSW 0x02
#define NEC_EAGLE_RST_LEDOFF 0x01
/*
* PCI INT Rgister
*/
#define NEC_EAGLE_PCIINTREG KSEG1ADDR(0x0DFFFFDC)
#define NEC_EAGLE_PCIINT_LANINT 0x10
#define NEC_EAGLE_PCIINT_CP_INTD 0x08
#define NEC_EAGLE_PCIINT_CP_INTC 0x04
#define NEC_EAGLE_PCIINT_CP_INTB 0x02
#define NEC_EAGLE_PCIINT_CP_INTA 0x01
/*
* PCI INT Mask Register
*/
#define NEC_EAGLE_PCIINTMSKREG KSEG1ADDR(0x0DFFFFE0)
#define NEC_EAGLE_PCIINTMSK_MSKLANINT 0x10
#define NEC_EAGLE_PCIINTMSK_MSKCP_INTD 0x08
#define NEC_EAGLE_PCIINTMSK_MSKCP_INTC 0x04
#define NEC_EAGLE_PCIINTMSK_MSKCP_INTB 0x02
#define NEC_EAGLE_PCIINTMSK_MSKCP_INTA 0x01
/*
* CLK Division Register
*/
#define NEC_EAGLE_CLKDIV KSEG1ADDR(0x0DFFFFE4)
#define NEC_EAGLE_CLKDIV_PCIDIV1 0x10
#define NEC_EAGLE_CLKDIV_PCIDIV0 0x08
#define NEC_EAGLE_CLKDIV_VTDIV2 0x04
#define NEC_EAGLE_CLKDIV_VTDIV1 0x02
#define NEC_EAGLE_CLKDIV_VTDIV0 0x01
/*
* Source Revision Register
*/
#define NEC_EAGLE_REVISION KSEG1ADDR(0x0DFFFFE8)
#endif /* __ASM_NEC_EAGLE_H */
--- NEW FILE: vr4122.h ---
/* $Id: vr4122.h,v 1.1 2001/09/22 04:27:16 junsun Exp $
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1999 by Michael Klar
* Copyright (C) 2000 by Michael R. McDonald
*/
#ifndef __ASM_VR4122_H
#define __ASM_VR4122_H
#include <asm/addrspace.h>
#ifndef _LANGUAGE_ASSEMBLY
#include <asm/io.h>
#endif
/* CPU interrupts */
#define VR4122_IRQ_SW1 0 /* IP0 - Software interrupt */
#define VR4122_IRQ_SW2 1 /* IP1 - Software interrupt */
#define VR4122_IRQ_INT0 2 /* IP2 - All other interrupts */
#define VR4122_IRQ_INT1 3 /* IP3 - RTC Long1 */
#define VR4122_IRQ_INT2 4 /* IP4 - RTC Long2 */
#define VR4122_IRQ_INT3 5 /* IP5 - High Speed Modem */
#define VR4122_IRQ_INT4 6 /* IP6 - Unused */
#define VR4122_IRQ_TIMER 7 /* IP7 - Timer interrupt */
/* Cascaded from VR4122_IRQ_INT0 (ICU mapped interrupts) */
#define VR4122_IRQ_BATTERY 8
#define VR4122_IRQ_POWER 9
#define VR4122_IRQ_RTCL1 10 /* Use VR4122_IRQ_INT1 instead. */
#define VR4122_IRQ_ETIMER 11
#define VR4122_IRQ_RFU12 12
#define VR4122_IRQ_RFU13 13
#define VR4122_IRQ_RFU14 14
#define VR4122_IRQ_RFU15 15
#define VR4122_IRQ_GIU 16 /* This is a cascade to IRQs 40-71. Do not use. */
#define VR4122_IRQ_SIU 17
#define VR4122_IRQ_WRBERR 18
#define VR4122_IRQ_SOFT 19
#define VR4122_IRQ_RFU20 20
#define VR4122_IRQ_DOZEPIU 21
#define VR4122_IRQ_RFU22 22
#define VR4122_IRQ_RFU23 23
#define VR4122_IRQ_RTCL2 24 /* Use VR4122_IRQ_INT2 instead. */
#define VR4122_IRQ_LED 25
#define VR4122_IRQ_HSP 26 /* Use VR4122_IRQ_INT3 instead. */
#define VR4122_IRQ_TCLK 27
#define VR4122_IRQ_FIR 28
#define VR4122_IRQ_DSIU 29
#define VR4122_IRQ_PCIU 30
#define VR4122_IRQ_RFU31 31
#define VR4122_IRQ_RFU32 32
#define VR4122_IRQ_RFU33 33
#define VR4122_IRQ_RFU34 34
#define VR4122_IRQ_RFU35 35
#define VR4122_IRQ_RFU36 36
#define VR4122_IRQ_RFU37 37
#define VR4122_IRQ_RFU38 38
#define VR4122_IRQ_RFU39 39
/* Cascaded from VR4122_IRQ_GIU */
#define VR4122_IRQ_GPIO0 40
#define VR4122_IRQ_GPIO1 41
#define VR4122_IRQ_GPIO2 42
#define VR4122_IRQ_GPIO3 43
#define VR4122_IRQ_GPIO4 44
#define VR4122_IRQ_GPIO5 45
#define VR4122_IRQ_GPIO6 46
#define VR4122_IRQ_GPIO7 47
#define VR4122_IRQ_GPIO8 48
#define VR4122_IRQ_GPIO9 49
#define VR4122_IRQ_GPIO10 50
#define VR4122_IRQ_GPIO11 51
#define VR4122_IRQ_GPIO12 52
#define VR4122_IRQ_GPIO13 53
#define VR4122_IRQ_GPIO14 54
#define VR4122_IRQ_GPIO15 55
#define VR4122_IRQ_GPIO16 56
#define VR4122_IRQ_GPIO17 57
#define VR4122_IRQ_GPIO18 58
#define VR4122_IRQ_GPIO19 59
#define VR4122_IRQ_GPIO20 60
#define VR4122_IRQ_GPIO21 61
#define VR4122_IRQ_GPIO22 62
#define VR4122_IRQ_GPIO23 63
#define VR4122_IRQ_GPIO24 64
#define VR4122_IRQ_GPIO25 65
#define VR4122_IRQ_GPIO26 66
#define VR4122_IRQ_GPIO27 67
#define VR4122_IRQ_GPIO28 68
#define VR4122_IRQ_GPIO29 69
#define VR4122_IRQ_GPIO30 70
#define VR4122_IRQ_GPIO31 71
/* Alternative to above GPIO IRQ defines */
#define VR4122_IRQ_GPIO(pin) ((VR4122_IRQ_GPIO0)ADDR((pin))
#define VR4122_SYSINT1_IRQ_BASE 8
#define VR4122_SYSINT2_IRQ_BASE 24
#define VR4122_GIUINTL_IRQ_BASE 40
#define VR4122_GIUINTH_IRQ_BASE 56
/*
* Embedded CPU peripheral registers
*/
/* Bus Control Unit (BCU) */
#define VR4122_BCUCNTREG1 KSEG1ADDR(0x0F000000) /* BCU Control Register 1 */
#define VR4122_ROMSIZEREG KSEG1ADDR(0x0F000004) /* ROM Size Register */
#define VR4122_ROMSPEEDREG KSEG1ADDR(0x0F000006) /* BCU Access Cycle Change Register */
#define VR4122_BCUSPEEDREG VR4122_ROMSPEEDREG /* BCU Access Cycle Change Register */
#define VR4122_IO0SPEEDREG KSEG1ADDR(0x0F000008) /* I/O Access Cycle Change Register 0 */
#define VR4122_IO1SPEEDREG KSEG1ADDR(0x0F00000A) /* I/O Access Cycle Change Register 1 */
#define VR4122_REVIDREG KSEG1ADDR(0x0F000010) /* Revision ID Register */
#define VR4122_CLKSPEEDREG KSEG1ADDR(0x0F000014) /* Clock Speed Register */
#define VR4122_BCUCNTREG3 KSEG1ADDR(0x0F000016) /* BCU Control Register 3 */
#define VR4122_BCUCACHECNTREG KSEG1ADDR(0x0F000018) /* BCU Cache Control Register */
/* DMA Address Unit (DMAAU) */
#define VR4122_CSIIBALREG KSEG1ADDR(0x0F000020) /* CSI reception DMA base address register low */
#define VR4122_CSIIBAHREG KSEG1ADDR(0x0F000022) /* CSI reception DMA base address register high */
#define VR4122_CSIIALREG KSEG1ADDR(0x0F000024) /* CSI reception DMA address register low */
#define VR4122_CSIIAHREG KSEG1ADDR(0x0F000026) /* CSI reception DMA address register high */
#define VR4122_CSIOBALREG KSEG1ADDR(0x0F000028) /* CSI transmission DMA base address register low */
#define VR4122_CSIOBAHREG KSEG1ADDR(0x0F00002A) /* CSI transmission DMA base address register high */
#define VR4122_CSIOALREG KSEG1ADDR(0x0F00002C) /* CSI transmission DMA address register low */
#define VR4122_CSIOAHREG KSEG1ADDR(0x0F00002E) /* CSI transmission DMA address register high */
#define VR4122_FIRBALREG KSEG1ADDR(0x0F000030) /* FIR DMA Base Address Register Low */
#define VR4122_FIRBAHREG KSEG1ADDR(0x0F000032) /* FIR DMA Base Address Register High */
#define VR4122_FIRALREG KSEG1ADDR(0x0F000034) /* FIR DMA Address Register Low */
#define VR4122_FIRAHREG KSEG1ADDR(0x0F000036) /* FIR DMA Address Register High */
#define VR4122_RAMBALREG KSEG1ADDR(0x0F0001E0) /* RAM base address lower address between IO space and RAM */
#define VR4122_RAMBAHREG KSEG1ADDR(0x0F0001E2) /* RAM base address higher address between IO space and RAM */
#define VR4122_RAMALREG KSEG1ADDR(0x0F0001E4) /* RAM address lower address between IO space and RAM */
#define VR4122_RAMAHREG KSEG1ADDR(0x0F0001E6) /* RAM address higher address between IO space and RAM */
#define VR4122_IOBALREG KSEG1ADDR(0x0F0001E8) /* IO base address lower address between IO space and RAM */
#define VR4122_IOBAHREG KSEG1ADDR(0x0F0001EA) /* IO base address higher address between IO space and RAM */
#define VR4122_IOALREG KSEG1ADDR(0x0F0001EC) /* IO address lower address between IO space and RAM */
#define VR4122_IOAHREG KSEG1ADDR(0x0F0001EE) /* IO address higher address between IO space and RAM */
/* DMA Control Unit (DCU) */
#define VR4122_DMARSTREG KSEG1ADDR(0x0F000040) /* DMA Reset Register */
#define VR4122_DMAIDLEREG KSEG1ADDR(0x0F000042) /* DMA Idle Register */
#define VR4122_DMASENREG KSEG1ADDR(0x0F000044) /* DMA Sequencer Enable Register */
#define VR4122_DMAMSKREG KSEG1ADDR(0x0F000046) /* DMA Mask Register */
#define VR4122_DMAREQREG KSEG1ADDR(0x0F000048) /* DMA Request Register */
#define VR4122_TDREG KSEG1ADDR(0x0F00004A) /* Transfer Direction Register */
#define VR4122_DMAABITREG KSEG1ADDR(0x0F00004C) /* DMA arbitration protocol selection register */
#define VR4122_CONTROLREG KSEG1ADDR(0x0F00004E) /* DMA control register */
#define VR4122_BASSCNTLREG KSEG1ADDR(0x0F000050) /* DMA transfer byte size register low */
#define VR4122_BASSCNTHREG KSEG1ADDR(0x0F000052) /* DMA transfer byte size register high */
#define VR4122_CURRENTCNTLREG KSEG1ADDR(0x0F000054) /* DMA remaining transfer byte size register low */
#define VR4122_CURRENTCNTHREG KSEG1ADDR(0x0F000056) /* DMA remaining transfer byte size register high */
#define VR4122_TCINTR KSEG1ADDR(0x0F000058) /* Terminal count interrupt request */
/* Clock Mask Unit (CMU) */
#define VR4122_CMUCLKMSK KSEG1ADDR(0x0F000060) /* CMU Clock Mask Register */
#define VR4122_CMUCLKMSK_MSKSIU 0x0002
#define VR4122_CMUCLKMSK_MSKSSIU 0x0100
#define VR4122_CMUCLKMSK_MSKDSIU 0x0800
#define VR4122_CMUCLKMSK_MSKPCIU 0x2000
#ifndef _LANGUAGE_ASSEMBLY
extern void vr4122_clock_supply(unsigned short mask);
extern void vr4122_clock_mask(unsigned short mask);
#endif
/* Interrupt Control Unit (ICU) */
#define VR4122_SYSINT1REG KSEG1ADDR(0x0F000080) /* Level 1 System interrupt register 1 */
#define VR4122_GIUINTLREG KSEG1ADDR(0x0F000088) /* Level 2 GIU interrupt register Low */
#define VR4122_DSIUINTREG KSEG1ADDR(0x0F00008A) /* Level 2 DSIU interrupt register */
#define VR4122_MSYSINT1REG KSEG1ADDR(0x0F00008C) /* Level 1 mask system interrupt register 1 */
#define VR4122_MGIUINTLREG KSEG1ADDR(0x0F000094) /* Level 2 mask GIU interrupt register Low */
#define VR4122_MDSIUINTREG KSEG1ADDR(0x0F000096) /* Level 2 mask DSIU interrupt register */
#define VR4122_NMIREG KSEG1ADDR(0x0F000098) /* NMI register */
#define VR4122_SOFTINTREG KSEG1ADDR(0x0F00009A) /* Software interrupt register */
#define VR4122_SYSINT2REG KSEG1ADDR(0x0F0000A0) /* Level 1 System interrupt register 2 */
#define VR4122_GIUINTHREG KSEG1ADDR(0x0F0000A2) /* Level 2 GIU interrupt register High */
#define VR4122_FIRINTREG KSEG1ADDR(0x0F0000A4) /* Level 2 FIR interrupt register */
#define VR4122_MSYSINT2REG KSEG1ADDR(0x0F0000A6) /* Level 1 mask system interrupt register 2 */
#define VR4122_MGIUINTHREG KSEG1ADDR(0x0F0000A8) /* Level 2 mask GIU interrupt register High */
#define VR4122_MFIRINTREG KSEG1ADDR(0x0F0000AA) /* Level 2 mask FIR interrupt register */
#define VR4122_PCIINTREG KSEG1ADDR(0x0F0000AC) /* Level 2 PCI interrupt register */
#define VR4122_SCUINTREG KSEG1ADDR(0x0F0000AE) /* Level 2 SCU interrupt register */
#define VR4122_CSIINTREG KSEG1ADDR(0x0F0000B0) /* Level 2 CSI interrupt register */
#define VR4122_MPCIINTREG KSEG1ADDR(0x0F0000B2) /* Level 2 mask PCI interrupt register */
#define VR4122_MSCUINTREG KSEG1ADDR(0x0F0000B4) /* Level 2 mask SCU interrupt register */
#define VR4122_MCSIINTREG KSEG1ADDR(0x0F0000B6) /* Level 2 mask CSI interrupt register */
/* Power Management Unit (PMU) */
#define VR4122_PMUINTREG KSEG1ADDR(0x0F0000C0) /* PMU Status Register */
#define VR4122_PMUINT_POWERSW 0x1 /* Power switch */
#define VR4122_PMUINT_BATT 0x2 /* Low batt during normal operation */
#define VR4122_PMUINT_DEADMAN 0x4 /* Deadman's switch */
#define VR4122_PMUINT_RESET 0x8 /* Reset switch */
#define VR4122_PMUINT_RTCRESET 0x10 /* RTC Reset */
#define VR4122_PMUINT_TIMEOUT 0x20 /* HAL Timer Reset */
#define VR4122_PMUINT_BATTLOW 0x100 /* Battery low */
#define VR4122_PMUINT_RTC 0x200 /* RTC Alarm */
#define VR4122_PMUINT_DCD 0x400 /* DCD# */
#define VR4122_PMUINT_GPIO0 0x1000 /* GPIO0 */
#define VR4122_PMUINT_GPIO1 0x2000 /* GPIO1 */
#define VR4122_PMUINT_GPIO2 0x4000 /* GPIO2 */
#define VR4122_PMUINT_GPIO3 0x8000 /* GPIO3 */
#define VR4122_PMUCNTREG KSEG1ADDR(0x0F0000C2) /* PMU Control Register */
#define VR4122_PMUINT2REG KSEG1ADDR(0x0F0000C4) /* PMU Interrupt/Status 2 Register */
#define VR4122_PMUCNT2REG KSEG1ADDR(0x0F0000C6) /* PMU Control 2 Resister */
#define VR4122_PMUWAITREG KSEG1ADDR(0x0F0000C8) /* PMU Wait Counter Register */
#define VR4122_PMUTCLKDIVREG KSEG1ADDR(0x0F0000CC) /* PMU Tclk Div mode register */
#define VR4122_PMUINTRCLKDIVREG KSEG1ADDR(0x0F0000CE) /* PMU INT clock Div mode register */
#define VR4122_PMUCLKRUNREG KSEG1ADDR(0x0F0000D6) /* PMU CLKRUN control register */
/* Real Time Clock Unit (RTC) */
#define VR4122_ETIMELREG KSEG1ADDR(0x0F000100) /* Elapsed Time L Register */
#define VR4122_ETIMEMREG KSEG1ADDR(0x0F000102) /* Elapsed Time M Register */
#define VR4122_ETIMEHREG KSEG1ADDR(0x0F000104) /* Elapsed Time H Register */
#define VR4122_ECMPLREG KSEG1ADDR(0x0F000108) /* Elapsed Compare L Register */
#define VR4122_ECMPMREG KSEG1ADDR(0x0F00010A) /* Elapsed Compare M Register */
#define VR4122_ECMPHREG KSEG1ADDR(0x0F00010C) /* Elapsed Compare H Register */
#define VR4122_RTCL1LREG KSEG1ADDR(0x0F000110) /* RTC Long 1 L Register */
#define VR4122_RTCL1HREG KSEG1ADDR(0x0F000112) /* RTC Long 1 H Register */
#define VR4122_RTCL1CNTLREG KSEG1ADDR(0x0F000114) /* RTC Long 1 Count L Register */
#define VR4122_RTCL1CNTHREG KSEG1ADDR(0x0F000116) /* RTC Long 1 Count H Register */
#define VR4122_RTCL2LREG KSEG1ADDR(0x0F000118) /* RTC Long 2 L Register */
#define VR4122_RTCL2HREG KSEG1ADDR(0x0F00011A) /* RTC Long 2 H Register */
#define VR4122_RTCL2CNTLREG KSEG1ADDR(0x0F00011C) /* RTC Long 2 Count L Register */
#define VR4122_RTCL2CNTHREG KSEG1ADDR(0x0F00011E) /* RTC Long 2 Count H Register */
#define VR4122_TCLKLREG KSEG1ADDR(0x0F000120) /* TCLK L Register */
#define VR4122_TCLKHREG KSEG1ADDR(0x0F000122) /* TCLK H Register */
#define VR4122_TCLKCNTLREG KSEG1ADDR(0x0F000124) /* TCLK Count L Register */
#define VR4122_TCLKCNTHREG KSEG1ADDR(0x0F000126) /* TCLK Count H Register */
#define VR4122_RTCINTREG KSEG1ADDR(0x0F00013E) /* RTC Interrupt Register */
/* General Purpose I/O Unit (GIU) */
#define VR4122_GIUIOSELL KSEG1ADDR(0x0F000140) /* GPIO Input/Output Select Register L */
#define VR4122_GIUIOSELH KSEG1ADDR(0x0F000142) /* GPIO Input/Output Select Register H */
#define VR4122_GIUPIODL KSEG1ADDR(0x0F000144) /* GPIO Port Input/Output Data Register L */
#define VR4122_GIUPIODL_GPIO15 0x8000
#define VR4122_GIUPIODL_GPIO14 0x4000
#define VR4122_GIUPIODL_GPIO13 0x2000
#define VR4122_GIUPIODL_GPIO12 0x1000
#define VR4122_GIUPIODL_GPIO11 0x0800
#define VR4122_GIUPIODL_GPIO10 0x0400
#define VR4122_GIUPIODL_GPIO9 0x0200
#define VR4122_GIUPIODL_GPIO8 0x0100
#define VR4122_GIUPIODL_GPIO7 0x0080
#define VR4122_GIUPIODL_GPIO6 0x0040
#define VR4122_GIUPIODL_GPIO5 0x0020
#define VR4122_GIUPIODL_GPIO4 0x0010
#define VR4122_GIUPIODL_GPIO3 0x0008
#define VR4122_GIUPIODL_GPIO2 0x0004
#define VR4122_GIUPIODL_GPIO1 0x0002
#define VR4122_GIUPIODL_GPIO0 0x0001
#define VR4122_GIUPIODH KSEG1ADDR(0x0F000146) /* GPIO Port Input/Output Data Register H */
#define VR4122_GIUPIODH_GPIO31 0x8000
#define VR4122_GIUPIODH_GPIO30 0x4000
#define VR4122_GIUPIODH_GPIO29 0x2000
#define VR4122_GIUPIODH_GPIO28 0x1000
#define VR4122_GIUPIODH_GPIO27 0x0800
#define VR4122_GIUPIODH_GPIO26 0x0400
#define VR4122_GIUPIODH_GPIO25 0x0200
#define VR4122_GIUPIODH_GPIO24 0x0100
#define VR4122_GIUPIODH_GPIO23 0x0080
#define VR4122_GIUPIODH_GPIO22 0x0040
#define VR4122_GIUPIODH_GPIO21 0x0020
#define VR4122_GIUPIODH_GPIO20 0x0010
#define VR4122_GIUPIODH_GPIO19 0x0008
#define VR4122_GIUPIODH_GPIO18 0x0004
#define VR4122_GIUPIODH_GPIO17 0x0002
#define VR4122_GIUPIODH_GPIO16 0x0001
#define VR4122_GIUINTSTATL KSEG1ADDR(0x0F000148) /* GPIO Interrupt Status Register L */
#define VR4122_GIUINTSTATH KSEG1ADDR(0x0F00014A) /* GPIO Interrupt Status Register H */
#define VR4122_GIUINTENL KSEG1ADDR(0x0F00014C) /* GPIO Interrupt Enable Register L */
#define VR4122_GIUINTENH KSEG1ADDR(0x0F00014E) /* GPIO Interrupt Enable Register H */
#define VR4122_GIUINTTYPL KSEG1ADDR(0x0F000150) /* GPIO Interrupt Type (Edge or Level) Select Register */
#define VR4122_GIUINTTYPH KSEG1ADDR(0x0F000152) /* GPIO Interrupt Type (Edge or Level) Select Register */
#define VR4122_GIUINTALSELL KSEG1ADDR(0x0F000154) /* GPIO Interrupt Active Level Select Register L */
#define VR4122_GIUINTALSELH KSEG1ADDR(0x0F000156) /* GPIO Interrupt Active Level Select Register H */
#define VR4122_GIUINTHTSELL KSEG1ADDR(0x0F000158) /* GPIO Interrupt Hold/Through Select Register L */
#define VR4122_GIUINTHTSELH KSEG1ADDR(0x0F00015A) /* GPIO Interrupt Hold/Through Select Register H */
#define VR4122_GIUPODATEN KSEG1ADDR(0x0F00015C) /* GPIO Port Output Data Enable Register */
#define VR4122_GIUPODATL KSEG1ADDR(0x0F00015E) /* GPIO Port Output Data Register L */
#define VR4122_GIUPODATL_GPIO47 0x8000
#define VR4122_GIUPODATL_GPIO46 0x4000
#define VR4122_GIUPODATL_GPIO45 0x2000
#define VR4122_GIUPODATL_GPIO44 0x1000
#define VR4122_GIUPODATL_GPIO43 0x0800
#define VR4122_GIUPODATL_GPIO42 0x0400
#define VR4122_GIUPODATL_GPIO41 0x0200
#define VR4122_GIUPODATL_GPIO40 0x0100
#define VR4122_GIUPODATL_GPIO39 0x0080
#define VR4122_GIUPODATL_GPIO38 0x0040
#define VR4122_GIUPODATL_GPIO37 0x0020
#define VR4122_GIUPODATL_GPIO36 0x0010
#define VR4122_GIUPODATL_GPIO35 0x0008
#define VR4122_GIUPODATL_GPIO34 0x0004
#define VR4122_GIUPODATL_GPIO33 0x0002
#define VR4122_GIUPODATL_GPIO32 0x0001
#define VR4122_GIUPODATL_PODAT15 0x8000
#define VR4122_GIUPODATL_PODAT14 0x4000
#define VR4122_GIUPODATL_PODAT13 0x2000
#define VR4122_GIUPODATL_PODAT12 0x1000
#define VR4122_GIUPODATL_PODAT11 0x0800
#define VR4122_GIUPODATL_PODAT10 0x0400
#define VR4122_GIUPODATL_PODAT9 0x0200
#define VR4122_GIUPODATL_PODAT8 0x0100
#define VR4122_GIUPODATL_PODAT7 0x0080
#define VR4122_GIUPODATL_PODAT6 0x0040
#define VR4122_GIUPODATL_PODAT5 0x0020
#define VR4122_GIUPODATL_PODAT4 0x0010
#define VR4122_GIUPODATL_PODAT3 0x0008
#define VR4122_GIUPODATL_PODAT2 0x0004
#define VR4122_GIUPODATL_PODAT1 0x0002
#define VR4122_GIUPODATL_PODAT0 0x0001
#define VR4122_SECIRQMASKL VR4122_GIUINTENL
#define VR4122_SECIRQMASKH VR4122_GIUINTENH
#ifndef _LANGUAGE_ASSEMBLY
extern __inline__ unsigned char vr4122_read_gpio_bit(int bit)
{
if (bit < 16) {
return (readw(VR4122_GIUPIODL) & (1 << bit)) ? 1 : 0;
}
else if (bit < 32) {
bit -= 16;
return (readw(VR4122_GIUPIODH) & (1 << bit)) ? 1 : 0;
}
return 0;
}
extern __inline__ void vr4122_write_gpio_bit(unsigned char val, int bit)
{
unsigned short d;
if (bit < 16) {
if (val == 0) {
d = readw(VR4122_GIUPIODL);
d &= ~(1 << bit);
writew(d, VR4122_GIUPIODL);
}
else {
d = readw(VR4122_GIUPIODL);
d |= (1 << bit);
writew(d, VR4122_GIUPIODL);
}
}
else if (bit < 32) {
bit -= 16;
if (val == 0){
d = readw(VR4122_GIUPIODH);
d &= ~(1 << bit);
writew(d, VR4122_GIUPIODH);
}
else {
d = readw(VR4122_GIUPIODH);
d |= (1 << bit);
writew(d, VR4122_GIUPIODH);
}
}
}
extern __inline__ unsigned short vr4122_read_gpio_low(void)
{
return readw(VR4122_GIUPIODL);
}
extern __inline__ unsigned short vr4122_read_gpio_high(void)
{
return readw(VR4122_GIUPIODH);
}
extern __inline__ void vr4122_write_gpio_low(unsigned short val)
{
writew(val, VR4122_GIUPIODL);
}
extern __inline__ void vr4122_write_gpio_high(unsigned short val)
{
writew(val, VR4122_GIUPIODH);
}
#endif
/* SDRAM Control Unit (SDRAMU) */
#define VR4122_SDRAMMODEREG KSEG1ADDR(0x0F000400) /* SDRAM mode register */
#define VR4122_SDRAMCNTREG KSEG1ADDR(0x0F000402) /* SDRAM control register */
#define VR4122_BCURFCNTREG KSEG1ADDR(0x0F000404) /* BCU refresh control register */
#define VR4122_BCURFCOUNTREG KSEG1ADDR(0x0F000406) /* BCU refresh cycle count register */
#define VR4122_RAMSIZEREG KSEG1ADDR(0x0F000408) /* DRAM size register */
/* Debug Serial Interface Unit (DSIU) */
#define VR4122_DSIURB KSEG1ADDR(0x0F000820) /* Receive buffer register (read) */
#define VR4122_DSIUTH KSEG1ADDR(0x0F000820) /* Transmission hold register (write) */
#define VR4122_DSIUDLL KSEG1ADDR(0x0F000820) /* Division rate lower register (LCR7=1) */
#define VR4122_DSIUIE KSEG1ADDR(0x0F000821) /* Interrupt enable register */
#define VR4122_DSIUDLM KSEG1ADDR(0x0F000821) /* Division rate higher register (LCR7=1) */
#define VR4122_DSIUIID KSEG1ADDR(0x0F000822) /* Interrupt indication register (read) */
#define VR4122_DSIUFC KSEG1ADDR(0x0F000822) /* FIFO control register (write) */
#define VR4122_DSIULC KSEG1ADDR(0x0F000823) /* Line control register */
#define VR4122_DSIUMC KSEG1ADDR(0x0F000824) /* MODEM control register */
#define VR4122_DSIULS KSEG1ADDR(0x0F000825) /* Line status register */
#define VR4122_DSIUMS KSEG1ADDR(0x0F000826) /* MODEM status register */
#define VR4122_DSIUSC KSEG1ADDR(0x0F000827) /* Scratch register */
/* LED Control Unit (LED) */
#define VR4122_LEDHTSREG KSEG1ADDR(0x0F000180) /* LED H Time Set register */
#define VR4122_LEDLTSREG KSEG1ADDR(0x0F000182) /* LED L Time Set register */
#define VR4122_LEDCNTREG KSEG1ADDR(0x0F000188) /* LED Control register */
#define VR4122_LEDASTCREG KSEG1ADDR(0x0F00018A) /* LED Auto Stop Time Count register */
#define VR4122_LEDINTREG KSEG1ADDR(0x0F00018C) /* LED Interrupt register */
/* Serial Interface Unit (SIU) */
#define VR4122_SIURB KSEG1ADDR(0x0F000800) /* Receiver Buffer Register (Read) DLAB = 0 */
#define VR4122_SIUTH KSEG1ADDR(0x0F000800) /* Transmitter Holding Register (Write) DLAB = 0 */
#define VR4122_SIUDLL KSEG1ADDR(0x0F000800) /* Divisor Latch (Least Significant Byte) DLAB = 1 */
#define VR4122_SIUIE KSEG1ADDR(0x0F000801) /* Interrupt Enable DLAB = 0 */
#define VR4122_SIUDLM KSEG1ADDR(0x0F000801) /* Divisor Latch (Most Significant Byte) DLAB = 1 */
#define VR4122_SIUIID KSEG1ADDR(0x0F000802) /* Interrupt Identification Register (Read) */
#define VR4122_SIUFC KSEG1ADDR(0x0F000802) /* FIFO Control Register (Write) */
#define VR4122_SIULC KSEG1ADDR(0x0F000803) /* Line Control Register */
#define VR4122_SIUMC KSEG1ADDR(0x0F000804) /* MODEM Control Register */
#define VR4122_SIULS KSEG1ADDR(0x0F000805) /* Line Status Register */
#define VR4122_SIUMS KSEG1ADDR(0x0F000806) /* MODEM Status Register */
#define VR4122_SIUSC KSEG1ADDR(0x0F000807) /* Scratch Register */
#define VR4122_SIUIRSEL KSEG1ADDR(0x0F000808) /* SIU/FIR IrDA Selector */
#define VR4122_SIUIRSEL_SIRSEL 0x0001
#define VR4122_SIURESET KSEG1ADDR(0x0F000809) /* SIU Reset Register */
#define VR4122_SIUCSEL KSEG1ADDR(0x0F00080A) /* SIU Echo-Back Control Register */
/* Fast IrDA Interface Unit (FIR) */
#define VR4122_FRSTR KSEG1ADDR(0x0F000840) /* FIR Reset register */
#define VR4122_DPINTR KSEG1ADDR(0x0F000842) /* DMA Page Interrupt register */
#define VR4122_DPCNTR KSEG1ADDR(0x0F000844) /* DMA Control register */
#define VR4122_TDR KSEG1ADDR(0x0F000850) /* Transmit Data register */
#define VR4122_RDR KSEG1ADDR(0x0F000852) /* Receive Data register */
#define VR4122_IMR KSEG1ADDR(0x0F000854) /* Interrupt Mask register */
#define VR4122_FSR KSEG1ADDR(0x0F000856) /* FIFO Setup register */
#define VR4122_IRSR1 KSEG1ADDR(0x0F000858) /* Infrared Setup register 1 */
#define VR4122_CRCSR KSEG1ADDR(0x0F00085C) /* CRC Setup register */
#define VR4122_FIRCR KSEG1ADDR(0x0F00085E) /* FIR Control register */
#define VR4122_MIRCR KSEG1ADDR(0x0F000860) /* MIR Control register */
#define VR4122_DMACR KSEG1ADDR(0x0F000862) /* DMA Control register */
#define VR4122_DMAER KSEG1ADDR(0x0F000864) /* DMA Enable register */
#define VR4122_TXIR KSEG1ADDR(0x0F000866) /* Transmit Indication register */
#define VR4122_RXIR KSEG1ADDR(0x0F000868) /* Receive Indication register */
#define VR4122_IFR KSEG1ADDR(0x0F00086A) /* Interrupt Flag register */
#define VR4122_RXSTS KSEG1ADDR(0x0F00086C) /* Receive Status */
#define VR4122_TXFL KSEG1ADDR(0x0F00086E) /* Transmit Frame Length */
#define VR4122_MRXF KSEG1ADDR(0x0F000870) /* Maximum Receive Frame Length */
#define VR4122_RXFL KSEG1ADDR(0x0F000874) /* Receive Frame Length */
/* PCI Interface Unit (PCIU) */
#define VR4122_PCIMMAW1REG KSEG1ADDR(0x0F000C00)
#define VR4122_PCIMMAW2REG KSEG1ADDR(0x0F000C04)
#define VR4122_PCITAW1REG KSEG1ADDR(0x0F000C08)
#define VR4122_PCITAW2REG KSEG1ADDR(0x0F000C0C)
#define VR4122_PCIMIOAWREG KSEG1ADDR(0x0F000C10)
#define VR4122_PCICONFDREG KSEG1ADDR(0x0F000C14)
#define VR4122_PCICONFAREG KSEG1ADDR(0x0F000C18)
#define VR4122_PCIMAILREG KSEG1ADDR(0x0F000C1C)
#define VR4122_BUSERRADREG KSEG1ADDR(0x0F000C24)
#define VR4122_INTCNTSTAREG KSEG1ADDR(0x0F000C28)
#define VR4122_PCIEXACCREG KSEG1ADDR(0x0F000C2C)
#define VR4122_PCIRECONTREG KSEG1ADDR(0x0F000C30)
#define VR4122_PCIENREG KSEG1ADDR(0x0F000C34)
#define VR4122_PCICLKSELREG KSEG1ADDR(0x0F000C38)
#define VR4122_PCITRDYVREG KSEG1ADDR(0x0F000C3C)
#define VR4122_PCICLKRUNREG KSEG1ADDR(0x0F000C60)
#define VR4122_PCIVENDORIDREG KSEG1ADDR(0x0F000D00)
#define VR4122_PCIDEVICEIDREG KSEG1ADDR(0x0F000D02)
#define VR4122_PCICOMMANDREG KSEG1ADDR(0x0F000D04)
#define VR4122_PCIREVREG KSEG1ADDR(0x0F000D08)
#define VR4122_PCICACHELSREG KSEG1ADDR(0x0F000D0C)
#define VR4122_PCIMAILBAREG KSEG1ADDR(0x0F000D10)
#define VR4122_PCIMBA1REG KSEG1ADDR(0x0F000D14)
#define VR4122_PCIMBA2REG KSEG1ADDR(0x0F000D18)
#define VR4122_PCIINTLINEREG KSEG1ADDR(0x0F000D3C)
#define VR4122_PCIRETVALREG KSEG1ADDR(0x0F000D40)
#endif /* __ASM_MIPS_VR4122_H */
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From: Jun S. <ju...@us...> - 2001-09-22 04:27:19
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Update of /cvsroot/linux-mips/linux/arch/mips/vr41xx/vr4181 In directory usw-pr-cvs1:/tmp/cvs-serv27047/arch/mips/vr41xx/vr4181 Removed Files: Makefile int_handler.S prom.c setup.c Log Message: Initial re-structuring of vr41xx directory. More are coming to actually get Osprey/Eagle building and running. --- Makefile DELETED --- --- int_handler.S DELETED --- --- prom.c DELETED --- --- setup.c DELETED --- |
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From: Jun S. <ju...@us...> - 2001-09-22 04:27:19
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Update of /cvsroot/linux-mips/linux/include/asm-mips/vr4181 In directory usw-pr-cvs1:/tmp/cvs-serv27047/include/asm-mips/vr4181 Added Files: vr4181.h Log Message: Initial re-structuring of vr41xx directory. More are coming to actually get Osprey/Eagle building and running. --- NEW FILE: vr4181.h --- /* $Id: vr4181.h,v 1.1 2001/09/22 04:27:16 junsun Exp $ * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * * Copyright (C) 1999 by Michael Klar * Copyright (C) 2001 Monta Vista Software, js...@mv... */ #ifndef __ASM_MIPS_VR4181_H #define __ASM_MIPS_VR4181_H #include <asm/addrspace.h> // CPU interrupts #define VR4181_IRQ_SW1 0 // IP0 - Software interrupt #define VR4181_IRQ_SW2 1 // IP1 - Software interrupt #define VR4181_IRQ_INT0 2 // IP2 - All but battery, high speed modem, and real time clock #define VR4181_IRQ_INT1 3 // IP3 - RTC Long1 (system timer) #define VR4181_IRQ_INT2 4 // IP4 - RTC Long2 #define VR4181_IRQ_INT3 5 // IP5 - High Speed Modem (unused on VR4181) #define VR4181_IRQ_INT4 6 // IP6 - Unused #define VR4181_IRQ_TIMER 7 // IP7 - Timer interrupt from CPO_COMPARE (Note: RTC Long1 is the system timer.) // Cascaded from VR4181_IRQ_INT0 (ICU mapped interrupts) #define VR4181_IRQ_BATTERY 8 #define VR4181_IRQ_POWER 9 #define VR4181_IRQ_RTCL1 10 // Use VR4181_IRQ_INT1 instead. #define VR4181_IRQ_ETIMER 11 #define VR4181_IRQ_RFU12 12 #define VR4181_IRQ_PIU 13 #define VR4181_IRQ_AIU 14 #define VR4181_IRQ_KIU 15 #define VR4181_IRQ_GIU 16 // This is a cascade to IRQs 40-71. Do not use. #define VR4181_IRQ_SIU 17 #define VR4181_IRQ_RFU18 18 #define VR4181_IRQ_SOFT 19 #define VR4181_IRQ_RFU20 20 #define VR4181_IRQ_DOZEPIU 21 #define VR4181_IRQ_RFU22 22 #define VR4181_IRQ_RFU23 23 #define VR4181_IRQ_RTCL2 24 // Use VR4181_IRQ_INT2 instead. #define VR4181_IRQ_LED 25 #define VR4181_IRQ_ECU 26 // (CompactFlash) #define VR4181_IRQ_CSU 27 #define VR4181_IRQ_USB 28 #define VR4181_IRQ_DMA 29 #define VR4181_IRQ_LCD 30 #define VR4181_IRQ_RFU31 31 #define VR4181_IRQ_RFU32 32 #define VR4181_IRQ_RFU33 33 #define VR4181_IRQ_RFU34 34 #define VR4181_IRQ_RFU35 35 #define VR4181_IRQ_RFU36 36 #define VR4181_IRQ_RFU37 37 #define VR4181_IRQ_RFU38 38 #define VR4181_IRQ_RFU39 39 // Note: Still need to do the extra VR4181 IRQ definitions // Cascaded from VR4181_IRQ_GIU #define VR4181_IRQ_GPIO0 40 #define VR4181_IRQ_GPIO1 41 #define VR4181_IRQ_GPIO2 42 #define VR4181_IRQ_GPIO3 43 #define VR4181_IRQ_GPIO4 44 #define VR4181_IRQ_GPIO5 45 #define VR4181_IRQ_GPIO6 46 #define VR4181_IRQ_GPIO7 47 #define VR4181_IRQ_GPIO8 48 #define VR4181_IRQ_GPIO9 49 #define VR4181_IRQ_GPIO10 50 #define VR4181_IRQ_GPIO11 51 #define VR4181_IRQ_GPIO12 52 #define VR4181_IRQ_GPIO13 53 #define VR4181_IRQ_GPIO14 54 #define VR4181_IRQ_GPIO15 55 // Alternative to above GPIO IRQ defines #define VR4181_IRQ_GPIO(pin) ((VR4181_IRQ_GPIO0) + (pin)) #define VR4181_IRQ_MAX 55 #ifndef _LANGUAGE_ASSEMBLY #define __preg8 (volatile unsigned char*) #define __preg16 (volatile unsigned short*) #define __preg32 (volatile unsigned int*) #else #define __preg8 #define __preg16 #define __preg32 #endif // Embedded CPU peripheral registers // Note that many of the registers have different physical address for VR4181 // Bus Control Unit (BCU) #define VR4181_BCUCNTREG1 __preg16(KSEG1 + 0x0A000000) /* BCU control register 1 (R/W) */ #define VR4181_CMUCLKMSK __preg16(KSEG1 + 0x0A000004) /* Clock mask register (R/W) */ #define VR4181_CMUCLKMSK_MSKCSUPCLK 0x0040 #define VR4181_CMUCLKMSK_MSKAIUPCLK 0x0020 #define VR4181_CMUCLKMSK_MSKPIUPCLK 0x0010 #define VR4181_CMUCLKMSK_MSKADUPCLK 0x0008 #define VR4181_CMUCLKMSK_MSKSIU18M 0x0004 #define VR4181_CMUCLKMSK_MSKADU18M 0x0002 #define VR4181_CMUCLKMSK_MSKUSB 0x0001 #define VR4181_CMUCLKMSK_MSKSIU VR4181_CMUCLKMSK_MSKSIU18M #define VR4181_BCUSPEEDREG __preg16(KSEG1 + 0x0A00000C) /* BCU access time parameter (R/W) */ #define VR4181_BCURFCNTREG __preg16(KSEG1 + 0x0A000010) /* BCU refresh control register (R/W) */ #define VR4181_REVIDREG __preg16(KSEG1 + 0x0A000014) /* Revision ID register (R) */ #define VR4181_CLKSPEEDREG __preg16(KSEG1 + 0x0A000018) /* Clock speed register (R) */ #define VR4181_EDOMCYTREG __preg16(KSEG1 + 0x0A000300) /* Memory cycle timing register (R/W) */ #define VR4181_MEMCFG_REG __preg16(KSEG1 + 0x0A000304) /* Memory configuration register (R/W) */ #define VR4181_MODE_REG __preg16(KSEG1 + 0x0A000308) /* SDRAM mode register (R/W) */ #define VR4181_SDTIMINGREG __preg16(KSEG1 + 0x0A00030C) /* SDRAM timing register (R/W) */ // DMA Control Unit (DCU) #define VR4181_MICDEST1REG1 __preg16(KSEG1 + 0x0A000020) /* Microphone destination 1 address register 1 (R/W) */ #define VR4181_MICDEST1REG2 __preg16(KSEG1 + 0x0A000022) /* Microphone destination 1 address register 2 (R/W) */ #define VR4181_MICDEST2REG1 __preg16(KSEG1 + 0x0A000024) /* Microphone destination 2 address register 1 (R/W) */ #define VR4181_MICDEST2REG2 __preg16(KSEG1 + 0x0A000026) /* Microphone destination 2 address register 2 (R/W) */ #define VR4181_SPKRRC1REG1 __preg16(KSEG1 + 0x0A000028) /* Speaker Source 1 address register 1 (R/W) */ #define VR4181_SPKRRC1REG2 __preg16(KSEG1 + 0x0A00002A) /* Speaker Source 1 address register 2 (R/W) */ #define VR4181_SPKRRC2REG1 __preg16(KSEG1 + 0x0A00002C) /* Speaker Source 2 address register 1 (R/W) */ #define VR4181_SPKRRC2REG2 __preg16(KSEG1 + 0x0A00002E) /* Speaker Source 2 address register 2 (R/W) */ #define VR4181_DMARSTREG __preg16(KSEG1 + 0x0A000040) /* DMA Reset register (R/W) */ #define VR4181_AIUDMAMSKREG __preg16(KSEG1 + 0x0A000046) /* Audio DMA mask register (R/W) */ #define VR4181_USBDMAMSKREG __preg16(KSEG1 + 0x0A000600) /* USB DMA Mask register (R/W) */ #define VR4181_USBRXS1AREG1 __preg16(KSEG1 + 0x0A000602) /* USB Rx source 1 address register 1 (R/W) */ #define VR4181_USBRXS1AREG2 __preg16(KSEG1 + 0x0A000604) /* USB Rx source 1 address register 2 (R/W) */ #define VR4181_USBRXS2AREG1 __preg16(KSEG1 + 0x0A000606) /* USB Rx source 2 address register 1 (R/W) */ #define VR4181_USBRXS2AREG2 __preg16(KSEG1 + 0x0A000608) /* USB Rx source 2 address register 2 (R/W) */ #define VR4181_USBTXS1AREG1 __preg16(KSEG1 + 0x0A00060A) /* USB Tx source 1 address register 1 (R/W) */ #define VR4181_USBTXS1AREG2 __preg16(KSEG1 + 0x0A00060C) /* USB Tx source 1 address register 2 (R/W) */ #define VR4181_USBTXS2AREG1 __preg16(KSEG1 + 0x0A00060E) /* USB Tx source 2 address register 1 (R/W) */ #define VR4181_USBTXS2AREG2 __preg16(KSEG1 + 0x0A000610) /* USB Tx source 2 address register 2 (R/W) */ #define VR4181_USBRXD1AREG1 __preg16(KSEG1 + 0x0A00062A) /* USB Rx destination 1 address register 1 (R/W) */ #define VR4181_USBRXD1AREG2 __preg16(KSEG1 + 0x0A00062C) /* USB Rx destination 1 address register 2 (R/W) */ #define VR4181_USBRXD2AREG1 __preg16(KSEG1 + 0x0A00062E) /* USB Rx destination 2 address register 1 (R/W) */ #define VR4181_USBRXD2AREG2 __preg16(KSEG1 + 0x0A000630) /* USB Rx destination 2 address register 2 (R/W) */ #define VR4181_USBTXD1AREG1 __preg16(KSEG1 + 0x0A000632) /* USB Tx destination 1 address register 1 (R/W) */ #define VR4181_USBTXD1AREG2 __preg16(KSEG1 + 0x0A000634) /* USB Tx destination 1 address register 2 (R/W) */ #define VR4181_USBTXD2AREG1 __preg16(KSEG1 + 0x0A000636) /* USB Tx destination 2 address register 1 (R/W) */ #define VR4181_USBTXD2AREG2 __preg16(KSEG1 + 0x0A000638) /* USB Tx destination 2 address register 2 (R/W) */ #define VR4181_RxRCLENREG __preg16(KSEG1 + 0x0A000652) /* USB Rx record length register (R/W) */ #define VR4181_TxRCLENREG __preg16(KSEG1 + 0x0A000654) /* USB Tx record length register (R/W) */ #define VR4181_MICRCLENREG __preg16(KSEG1 + 0x0A000658) /* Microphone record length register (R/W) */ #define VR4181_SPKRCLENREG __preg16(KSEG1 + 0x0A00065A) /* Speaker record length register (R/W) */ #define VR4181_USBCFGREG __preg16(KSEG1 + 0x0A00065C) /* USB configuration register (R/W) */ #define VR4181_MICDMACFGREG __preg16(KSEG1 + 0x0A00065E) /* Microphone DMA configuration register (R/W) */ #define VR4181_SPKDMACFGREG __preg16(KSEG1 + 0x0A000660) /* Speaker DMA configuration register (R/W) */ #define VR4181_DMAITRQREG __preg16(KSEG1 + 0x0A000662) /* DMA interrupt request register (R/W) */ #define VR4181_DMACLTREG __preg16(KSEG1 + 0x0A000664) /* DMA control register (R/W) */ #define VR4181_DMAITMKREG __preg16(KSEG1 + 0x0A000666) /* DMA interrupt mask register (R/W) */ // ISA Bridge #define VR4181_ISABRGCTL __preg16(KSEG1 + 0x0B0002C0) /* ISA Bridge Control Register (R/W) */ #define VR4181_ISABRGSTS __preg16(KSEG1 + 0x0B0002C2) /* ISA Bridge Status Register (R/W) */ #define VR4181_XISACTL __preg16(KSEG1 + 0x0B0002C4) /* External ISA Control Register (R/W) */ // Clocked Serial Interface (CSI) #define VR4181_CSIMODE __preg16(KSEG1 + 0x0B000900) /* CSI Mode Register (R/W) */ #define VR4181_CSIRXDATA __preg16(KSEG1 + 0x0B000902) /* CSI Receive Data Register (R) */ #define VR4181_CSITXDATA __preg16(KSEG1 + 0x0B000904) /* CSI Transmit Data Register (R/W) */ #define VR4181_CSILSTAT __preg16(KSEG1 + 0x0B000906) /* CSI Line Status Register (R/W) */ #define VR4181_CSIINTMSK __preg16(KSEG1 + 0x0B000908) /* CSI Interrupt Mask Register (R/W) */ #define VR4181_CSIINTSTAT __preg16(KSEG1 + 0x0B00090a) /* CSI Interrupt Status Register (R/W) */ #define VR4181_CSITXBLEN __preg16(KSEG1 + 0x0B00090c) /* CSI Transmit Burst Length Register (R/W) */ #define VR4181_CSIRXBLEN __preg16(KSEG1 + 0x0B00090e) /* CSI Receive Burst Length Register (R/W) */ // Interrupt Control Unit (ICU) #define VR4181_SYSINT1REG __preg16(KSEG1 + 0x0A000080) /* Level 1 System interrupt register 1 (R) */ #define VR4181_MSYSINT1REG __preg16(KSEG1 + 0x0A00008C) /* Level 1 mask system interrupt register 1 (R/W) */ #define VR4181_NMIREG __preg16(KSEG1 + 0x0A000098) /* NMI register (R/W) */ #define VR4181_SOFTINTREG __preg16(KSEG1 + 0x0A00009A) /* Software interrupt register (R/W) */ #define VR4181_SYSINT2REG __preg16(KSEG1 + 0x0A000200) /* Level 1 System interrupt register 2 (R) */ #define VR4181_MSYSINT2REG __preg16(KSEG1 + 0x0A000206) /* Level 1 mask system interrupt register 2 (R/W) */ #define VR4181_PIUINTREGro __preg16(KSEG1 + 0x0B000082) /* Level 2 PIU interrupt register (R) */ #define VR4181_AIUINTREG __preg16(KSEG1 + 0x0B000084) /* Level 2 AIU interrupt register (R) */ #define VR4181_MPIUINTREG __preg16(KSEG1 + 0x0B00008E) /* Level 2 mask PIU interrupt register (R/W) */ #define VR4181_MAIUINTREG __preg16(KSEG1 + 0x0B000090) /* Level 2 mask AIU interrupt register (R/W) */ #define VR4181_MKIUINTREG __preg16(KSEG1 + 0x0B000092) /* Level 2 mask KIU interrupt register (R/W) */ #define VR4181_KIUINTREG __preg16(KSEG1 + 0x0B000198) /* Level 2 KIU interrupt register (R) */ // Power Management Unit (PMU) #define VR4181_PMUINTREG __preg16(KSEG1 + 0x0B0000A0) /* PMU Status Register (R/W) */ #define VR4181_PMUINT_POWERSW 0x1 /* Power switch */ #define VR4181_PMUINT_BATT 0x2 /* Low batt during normal operation */ #define VR4181_PMUINT_DEADMAN 0x4 /* Deadman's switch */ #define VR4181_PMUINT_RESET 0x8 /* Reset switch */ #define VR4181_PMUINT_RTCRESET 0x10 /* RTC Reset */ #define VR4181_PMUINT_TIMEOUT 0x20 /* HAL Timer Reset */ #define VR4181_PMUINT_BATTLOW 0x100 /* Battery low */ #define VR4181_PMUINT_RTC 0x200 /* RTC Alarm */ #define VR4181_PMUINT_DCD 0x400 /* DCD# */ #define VR4181_PMUINT_GPIO0 0x1000 /* GPIO0 */ #define VR4181_PMUINT_GPIO1 0x2000 /* GPIO1 */ #define VR4181_PMUINT_GPIO2 0x4000 /* GPIO2 */ #define VR4181_PMUINT_GPIO3 0x8000 /* GPIO3 */ #define VR4181_PMUCNTREG __preg16(KSEG1 + 0x0B0000A2) /* PMU Control Register (R/W) */ #define VR4181_PMUWAITREG __preg16(KSEG1 + 0x0B0000A8) /* PMU Wait Counter Register (R/W) */ #define VR4181_PMUDIVREG __preg16(KSEG1 + 0x0B0000AC) /* PMU Divide Mode Register (R/W) */ #define VR4181_DRAMHIBCTL __preg16(KSEG1 + 0x0B0000B2) /* DRAM Hibernate Control Register (R/W) */ // Real Time Clock Unit (RTC) #define VR4181_ETIMELREG __preg16(KSEG1 + 0x0B0000C0) /* Elapsed Time L Register (R/W) */ #define VR4181_ETIMEMREG __preg16(KSEG1 + 0x0B0000C2) /* Elapsed Time M Register (R/W) */ #define VR4181_ETIMEHREG __preg16(KSEG1 + 0x0B0000C4) /* Elapsed Time H Register (R/W) */ #define VR4181_ECMPLREG __preg16(KSEG1 + 0x0B0000C8) /* Elapsed Compare L Register (R/W) */ #define VR4181_ECMPMREG __preg16(KSEG1 + 0x0B0000CA) /* Elapsed Compare M Register (R/W) */ #define VR4181_ECMPHREG __preg16(KSEG1 + 0x0B0000CC) /* Elapsed Compare H Register (R/W) */ #define VR4181_RTCL1LREG __preg16(KSEG1 + 0x0B0000D0) /* RTC Long 1 L Register (R/W) */ #define VR4181_RTCL1HREG __preg16(KSEG1 + 0x0B0000D2) /* RTC Long 1 H Register (R/W) */ #define VR4181_RTCL1CNTLREG __preg16(KSEG1 + 0x0B0000D4) /* RTC Long 1 Count L Register (R) */ #define VR4181_RTCL1CNTHREG __preg16(KSEG1 + 0x0B0000D6) /* RTC Long 1 Count H Register (R) */ #define VR4181_RTCL2LREG __preg16(KSEG1 + 0x0B0000D8) /* RTC Long 2 L Register (R/W) */ #define VR4181_RTCL2HREG __preg16(KSEG1 + 0x0B0000DA) /* RTC Long 2 H Register (R/W) */ #define VR4181_RTCL2CNTLREG __preg16(KSEG1 + 0x0B0000DC) /* RTC Long 2 Count L Register (R) */ #define VR4181_RTCL2CNTHREG __preg16(KSEG1 + 0x0B0000DE) /* RTC Long 2 Count H Register (R) */ #define VR4181_RTCINTREG __preg16(KSEG1 + 0x0B0001DE) /* RTC Interrupt Register (R/W) */ // Deadman's Switch Unit (DSU) #define VR4181_DSUCNTREG __preg16(KSEG1 + 0x0B0000E0) /* DSU Control Register (R/W) */ #define VR4181_DSUSETREG __preg16(KSEG1 + 0x0B0000E2) /* DSU Dead Time Set Register (R/W) */ #define VR4181_DSUCLRREG __preg16(KSEG1 + 0x0B0000E4) /* DSU Clear Register (W) */ #define VR4181_DSUTIMREG __preg16(KSEG1 + 0x0B0000E6) /* DSU Elapsed Time Register (R/W) */ // General Purpose I/O Unit (GIU) #define VR4181_GPMD0REG __preg16(KSEG1 + 0x0B000300) /* GPIO Mode 0 Register (R/W) */ #define VR4181_GPMD1REG __preg16(KSEG1 + 0x0B000302) /* GPIO Mode 1 Register (R/W) */ #define VR4181_GPMD2REG __preg16(KSEG1 + 0x0B000304) /* GPIO Mode 2 Register (R/W) */ #define VR4181_GPMD3REG __preg16(KSEG1 + 0x0B000306) /* GPIO Mode 3 Register (R/W) */ #define VR4181_GPDATHREG __preg16(KSEG1 + 0x0B000308) /* GPIO Data High Register (R/W) */ #define VR4181_GPDATHREG_GPIO16 0x0001 #define VR4181_GPDATHREG_GPIO17 0x0002 #define VR4181_GPDATHREG_GPIO18 0x0004 #define VR4181_GPDATHREG_GPIO19 0x0008 #define VR4181_GPDATHREG_GPIO20 0x0010 #define VR4181_GPDATHREG_GPIO21 0x0020 #define VR4181_GPDATHREG_GPIO22 0x0040 #define VR4181_GPDATHREG_GPIO23 0x0080 #define VR4181_GPDATHREG_GPIO24 0x0100 #define VR4181_GPDATHREG_GPIO25 0x0200 #define VR4181_GPDATHREG_GPIO26 0x0400 #define VR4181_GPDATHREG_GPIO27 0x0800 #define VR4181_GPDATHREG_GPIO28 0x1000 #define VR4181_GPDATHREG_GPIO29 0x2000 #define VR4181_GPDATHREG_GPIO30 0x4000 #define VR4181_GPDATHREG_GPIO31 0x8000 #define VR4181_GPDATLREG __preg16(KSEG1 + 0x0B00030A) /* GPIO Data Low Register (R/W) */ #define VR4181_GPDATLREG_GPIO0 0x0001 #define VR4181_GPDATLREG_GPIO1 0x0002 #define VR4181_GPDATLREG_GPIO2 0x0004 #define VR4181_GPDATLREG_GPIO3 0x0008 #define VR4181_GPDATLREG_GPIO4 0x0010 #define VR4181_GPDATLREG_GPIO5 0x0020 #define VR4181_GPDATLREG_GPIO6 0x0040 #define VR4181_GPDATLREG_GPIO7 0x0080 #define VR4181_GPDATLREG_GPIO8 0x0100 #define VR4181_GPDATLREG_GPIO9 0x0200 #define VR4181_GPDATLREG_GPIO10 0x0400 #define VR4181_GPDATLREG_GPIO11 0x0800 #define VR4181_GPDATLREG_GPIO12 0x1000 #define VR4181_GPDATLREG_GPIO13 0x2000 #define VR4181_GPDATLREG_GPIO14 0x4000 #define VR4181_GPDATLREG_GPIO15 0x8000 #define VR4181_GPINTEN __preg16(KSEG1 + 0x0B00030C) /* GPIO Interrupt Enable Register (R/W) */ #define VR4181_GPINTMSK __preg16(KSEG1 + 0x0B00030E) /* GPIO Interrupt Mask Register (R/W) */ #define VR4181_GPINTTYPH __preg16(KSEG1 + 0x0B000310) /* GPIO Interrupt Type High Register (R/W) */ #define VR4181_GPINTTYPL __preg16(KSEG1 + 0x0B000312) /* GPIO Interrupt Type Low Register (R/W) */ #define VR4181_GPINTSTAT __preg16(KSEG1 + 0x0B000314) /* GPIO Interrupt Status Register (R/W) */ #define VR4181_GPHIBSTH __preg16(KSEG1 + 0x0B000316) /* GPIO Hibernate Pin State High Register (R/W) */ #define VR4181_GPHIBSTL __preg16(KSEG1 + 0x0B000318) /* GPIO Hibernate Pin State Low Register (R/W) */ #define VR4181_GPSICTL __preg16(KSEG1 + 0x0B00031A) /* GPIO Serial Interface Control Register (R/W) */ #define VR4181_KEYEN __preg16(KSEG1 + 0x0B00031C) /* Keyboard Scan Pin Enable Register (R/W) */ #define VR4181_PCS0STRA __preg16(KSEG1 + 0x0B000320) /* Programmable Chip Select [0] Start Address Register (R/W) */ #define VR4181_PCS0STPA __preg16(KSEG1 + 0x0B000322) /* Programmable Chip Select [0] Stop Address Register (R/W) */ #define VR4181_PCS0HIA __preg16(KSEG1 + 0x0B000324) /* Programmable Chip Select [0] High Address Register (R/W) */ #define VR4181_PCS1STRA __preg16(KSEG1 + 0x0B000326) /* Programmable Chip Select [1] Start Address Register (R/W) */ #define VR4181_PCS1STPA __preg16(KSEG1 + 0x0B000328) /* Programmable Chip Select [1] Stop Address Register (R/W) */ #define VR4181_PCS1HIA __preg16(KSEG1 + 0x0B00032A) /* Programmable Chip Select [1] High Address Register (R/W) */ #define VR4181_PCSMODE __preg16(KSEG1 + 0x0B00032C) /* Programmable Chip Select Mode Register (R/W) */ #define VR4181_LCDGPMODE __preg16(KSEG1 + 0x0B00032E) /* LCD General Purpose Mode Register (R/W) */ #define VR4181_MISCREG0 __preg16(KSEG1 + 0x0B000330) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */ #define VR4181_MISCREG1 __preg16(KSEG1 + 0x0B000332) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */ #define VR4181_MISCREG2 __preg16(KSEG1 + 0x0B000334) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */ #define VR4181_MISCREG3 __preg16(KSEG1 + 0x0B000336) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */ #define VR4181_MISCREG4 __preg16(KSEG1 + 0x0B000338) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */ #define VR4181_MISCREG5 __preg16(KSEG1 + 0x0B00033A) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */ #define VR4181_MISCREG6 __preg16(KSEG1 + 0x0B00033C) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */ #define VR4181_MISCREG7 __preg16(KSEG1 + 0x0B00033D) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */ #define VR4181_MISCREG8 __preg16(KSEG1 + 0x0B000340) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */ #define VR4181_MISCREG9 __preg16(KSEG1 + 0x0B000342) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */ #define VR4181_MISCREG10 __preg16(KSEG1 + 0x0B000344) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */ #define VR4181_MISCREG11 __preg16(KSEG1 + 0x0B000346) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */ #define VR4181_MISCREG12 __preg16(KSEG1 + 0x0B000348) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */ #define VR4181_MISCREG13 __preg16(KSEG1 + 0x0B00034A) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */ #define VR4181_MISCREG14 __preg16(KSEG1 + 0x0B00034C) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */ #define VR4181_MISCREG15 __preg16(KSEG1 + 0x0B00034E) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */ #define VR4181_SECIRQMASKL VR4181_GPINTEN // No SECIRQMASKH for VR4181 // Touch Panel Interface Unit (PIU) #define VR4181_PIUCNTREG __preg16(KSEG1 + 0x0B000122) /* PIU Control register (R/W) */ #define VR4181_PIUCNTREG_PIUSEQEN 0x0004 #define VR4181_PIUCNTREG_PIUPWR 0x0002 #define VR4181_PIUCNTREG_PADRST 0x0001 #define VR4181_PIUINTREG __preg16(KSEG1 + 0x0B000124) /* PIU Interrupt cause register (R/W) */ #define VR4181_PIUINTREG_OVP 0x8000 #define VR4181_PIUINTREG_PADCMD 0x0040 #define VR4181_PIUINTREG_PADADP 0x0020 #define VR4181_PIUINTREG_PADPAGE1 0x0010 #define VR4181_PIUINTREG_PADPAGE0 0x0008 #define VR4181_PIUINTREG_PADDLOST 0x0004 #define VR4181_PIUINTREG_PENCHG 0x0001 #define VR4181_PIUSIVLREG __preg16(KSEG1 + 0x0B000126) /* PIU Data sampling interval register (R/W) */ #define VR4181_PIUSTBLREG __preg16(KSEG1 + 0x0B000128) /* PIU A/D converter start delay register (R/W) */ #define VR4181_PIUCMDREG __preg16(KSEG1 + 0x0B00012A) /* PIU A/D command register (R/W) */ #define VR4181_PIUASCNREG __preg16(KSEG1 + 0x0B000130) /* PIU A/D port scan register (R/W) */ #define VR4181_PIUAMSKREG __preg16(KSEG1 + 0x0B000132) /* PIU A/D scan mask register (R/W) */ #define VR4181_PIUCIVLREG __preg16(KSEG1 + 0x0B00013E) /* PIU Check interval register (R) */ #define VR4181_PIUPB00REG __preg16(KSEG1 + 0x0B0002A0) /* PIU Page 0 Buffer 0 register (R/W) */ #define VR4181_PIUPB01REG __preg16(KSEG1 + 0x0B0002A2) /* PIU Page 0 Buffer 1 register (R/W) */ #define VR4181_PIUPB02REG __preg16(KSEG1 + 0x0B0002A4) /* PIU Page 0 Buffer 2 register (R/W) */ #define VR4181_PIUPB03REG __preg16(KSEG1 + 0x0B0002A6) /* PIU Page 0 Buffer 3 register (R/W) */ #define VR4181_PIUPB10REG __preg16(KSEG1 + 0x0B0002A8) /* PIU Page 1 Buffer 0 register (R/W) */ #define VR4181_PIUPB11REG __preg16(KSEG1 + 0x0B0002AA) /* PIU Page 1 Buffer 1 register (R/W) */ #define VR4181_PIUPB12REG __preg16(KSEG1 + 0x0B0002AC) /* PIU Page 1 Buffer 2 register (R/W) */ #define VR4181_PIUPB13REG __preg16(KSEG1 + 0x0B0002AE) /* PIU Page 1 Buffer 3 register (R/W) */ #define VR4181_PIUAB0REG __preg16(KSEG1 + 0x0B0002B0) /* PIU A/D scan Buffer 0 register (R/W) */ #define VR4181_PIUAB1REG __preg16(KSEG1 + 0x0B0002B2) /* PIU A/D scan Buffer 1 register (R/W) */ #define VR4181_PIUAB2REG __preg16(KSEG1 + 0x0B0002B4) /* PIU A/D scan Buffer 2 register (R/W) */ #define VR4181_PIUAB3REG __preg16(KSEG1 + 0x0B0002B6) /* PIU A/D scan Buffer 3 register (R/W) */ #define VR4181_PIUPB04REG __preg16(KSEG1 + 0x0B0002BC) /* PIU Page 0 Buffer 4 register (R/W) */ #define VR4181_PIUPB14REG __preg16(KSEG1 + 0x0B0002BE) /* PIU Page 1 Buffer 4 register (R/W) */ // Audio Interface Unit (AIU) #define VR4181_SODATREG __preg16(KSEG1 + 0x0B000166) /* Speaker Output Data Register (R/W) */ #define VR4181_SCNTREG __preg16(KSEG1 + 0x0B000168) /* Speaker Output Control Register (R/W) */ #define VR4181_MIDATREG __preg16(KSEG1 + 0x0B000170) /* Mike Input Data Register (R/W) */ #define VR4181_MCNTREG __preg16(KSEG1 + 0x0B000172) /* Mike Input Control Register (R/W) */ #define VR4181_DVALIDREG __preg16(KSEG1 + 0x0B000178) /* Data Valid Register (R/W) */ #define VR4181_SEQREG __preg16(KSEG1 + 0x0B00017A) /* Sequential Register (R/W) */ #define VR4181_INTREG __preg16(KSEG1 + 0x0B00017C) /* Interrupt Register (R/W) */ #define VR4181_SDMADATREG __preg16(KSEG1 + 0x0B000160) /* Speaker DMA Data Register (R/W) */ #define VR4181_MDMADATREG __preg16(KSEG1 + 0x0B000162) /* Microphone DMA Data Register (R/W) */ #define VR4181_DAVREF_SETUP __preg16(KSEG1 + 0x0B000164) /* DAC Vref setup register (R/W) */ #define VR4181_SCNVC_END __preg16(KSEG1 + 0x0B00016E) /* Speaker sample rate control (R/W) */ #define VR4181_MIDATREG __preg16(KSEG1 + 0x0B000170) /* Microphone Input Data Register (R/W) */ #define VR4181_MCNTREG __preg16(KSEG1 + 0x0B000172) /* Microphone Input Control Register (R/W) */ #define VR4181_MCNVC_END __preg16(KSEG1 + 0x0B00017E) /* Microphone sample rate control (R/W) */ // Keyboard Interface Unit (KIU) #define VR4181_KIUDAT0 __preg16(KSEG1 + 0x0B000180) /* KIU Data0 Register (R/W) */ #define VR4181_KIUDAT1 __preg16(KSEG1 + 0x0B000182) /* KIU Data1 Register (R/W) */ #define VR4181_KIUDAT2 __preg16(KSEG1 + 0x0B000184) /* KIU Data2 Register (R/W) */ #define VR4181_KIUDAT3 __preg16(KSEG1 + 0x0B000186) /* KIU Data3 Register (R/W) */ #define VR4181_KIUDAT4 __preg16(KSEG1 + 0x0B000188) /* KIU Data4 Register (R/W) */ #define VR4181_KIUDAT5 __preg16(KSEG1 + 0x0B00018A) /* KIU Data5 Register (R/W) */ #define VR4181_KIUSCANREP __preg16(KSEG1 + 0x0B000190) /* KIU Scan/Repeat Register (R/W) */ #define VR4181_KIUSCANREP_KEYEN 0x8000 #define VR4181_KIUSCANREP_SCANSTP 0x0008 #define VR4181_KIUSCANREP_SCANSTART 0x0004 #define VR4181_KIUSCANREP_ATSTP 0x0002 #define VR4181_KIUSCANREP_ATSCAN 0x0001 #define VR4181_KIUSCANS __preg16(KSEG1 + 0x0B000192) /* KIU Scan Status Register (R) */ #define VR4181_KIUWKS __preg16(KSEG1 + 0x0B000194) /* KIU Wait Keyscan Stable Register (R/W) */ #define VR4181_KIUWKI __preg16(KSEG1 + 0x0B000196) /* KIU Wait Keyscan Interval Register (R/W) */ #define VR4181_KIUINT __preg16(KSEG1 + 0x0B000198) /* KIU Interrupt Register (R/W) */ #define VR4181_KIUINT_KDATLOST 0x0004 #define VR4181_KIUINT_KDATRDY 0x0002 #define VR4181_KIUINT_SCANINT 0x0001 #define VR4181_KIUDAT6 __preg16(KSEG1 + 0x0B00018C) /* Scan Line 6 Key Data Register (R) */ #define VR4181_KIUDAT7 __preg16(KSEG1 + 0x0B00018E) /* Scan Line 7 Key Data Register (R) */ // CompactFlash Controller #define VR4181_PCCARDINDEX __preg8(KSEG1 + 0x0B0008E0) /* PC Card Controller Index Register */ #define VR4181_PCCARDDATA __preg8(KSEG1 + 0x0B0008E1) /* PC Card Controller Data Register */ #define VR4181_INTSTATREG __preg16(KSEG1 + 0x0B0008F8) /* Interrupt Status Register (R/W) */ #define VR4181_INTMSKREG __preg16(KSEG1 + 0x0B0008FA) /* Interrupt Mask Register (R/W) */ #define VR4181_CFG_REG_1 __preg16(KSEG1 + 0x0B0008FE) /* Configuration Register 1 */ // LED Control Unit (LED) #define VR4181_LEDHTSREG __preg16(KSEG1 + 0x0B000240) /* LED H Time Set register (R/W) */ #define VR4181_LEDLTSREG __preg16(KSEG1 + 0x0B000242) /* LED L Time Set register (R/W) */ #define VR4181_LEDCNTREG __preg16(KSEG1 + 0x0B000248) /* LED Control register (R/W) */ #define VR4181_LEDASTCREG __preg16(KSEG1 + 0x0B00024A) /* LED Auto Stop Time Count register (R/W) */ #define VR4181_LEDINTREG __preg16(KSEG1 + 0x0B00024C) /* LED Interrupt register (R/W) */ // Serial Interface Unit (SIU / SIU1 and SIU2) #define VR4181_SIURB __preg8(KSEG1 + 0x0C000010) /* Receiver Buffer Register (Read) DLAB = 0 (R) */ #define VR4181_SIUTH __preg8(KSEG1 + 0x0C000010) /* Transmitter Holding Register (Write) DLAB = 0 (W) */ #define VR4181_SIUDLL __preg8(KSEG1 + 0x0C000010) /* Divisor Latch (Least Significant Byte) DLAB = 1 (R/W) */ #define VR4181_SIUIE __preg8(KSEG1 + 0x0C000011) /* Interrupt Enable DLAB = 0 (R/W) */ #define VR4181_SIUDLM __preg8(KSEG1 + 0x0C000011) /* Divisor Latch (Most Significant Byte) DLAB = 1 (R/W) */ #define VR4181_SIUIID __preg8(KSEG1 + 0x0C000012) /* Interrupt Identification Register (Read) (R) */ #define VR4181_SIUFC __preg8(KSEG1 + 0x0C000012) /* FIFO Control Register (Write) (W) */ #define VR4181_SIULC __preg8(KSEG1 + 0x0C000013) /* Line Control Register (R/W) */ #define VR4181_SIUMC __preg8(KSEG1 + 0x0C000014) /* MODEM Control Register (R/W) */ #define VR4181_SIULS __preg8(KSEG1 + 0x0C000015) /* Line Status Register (R/W) */ #define VR4181_SIUMS __preg8(KSEG1 + 0x0C000016) /* MODEM Status Register (R/W) */ #define VR4181_SIUSC __preg8(KSEG1 + 0x0C000017) /* Scratch Register (R/W) */ #define VR4181_SIURESET __preg8(KSEG1 + 0x0C000019) /* SIU Reset Register (R/W) */ #define VR4181_SIUACTMSK __preg8(KSEG1 + 0x0C00001C) /* SIU Activity Mask (R/W) */ #define VR4181_SIUACTTMR __preg8(KSEG1 + 0x0C00001E) /* SIU Activity Timer (R/W) */ #define VR4181_SIURB_2 __preg8(KSEG1 + 0x0C000000) /* Receive Buffer Register (Read) (R) */ #define VR4181_SIUTH_2 __preg8(KSEG1 + 0x0C000000) /* Transmitter Holding Register (Write) (W) */ #define VR4181_SIUDLL_2 __preg8(KSEG1 + 0x0C000000) /* Divisor Latch (Least Significant Byte) (R/W) */ #define VR4181_SIUIE_2 __preg8(KSEG1 + 0x0C000001) /* Interrupt Enable (DLAB = 0) (R/W) */ #define VR4181_SIUDLM_2 __preg8(KSEG1 + 0x0C000001) /* Divisor Latch (Most Significant Byte) (DLAB = 1) (R/W) */ #define VR4181_SIUIID_2 __preg8(KSEG1 + 0x0C000002) /* Interrupt Identification Register (Read) (R) */ #define VR4181_SIUFC_2 __preg8(KSEG1 + 0x0C000002) /* FIFO Control Register (Write) (W) */ #define VR4181_SIULC_2 __preg8(KSEG1 + 0x0C000003) /* Line Control Register (R/W) */ #define VR4181_SIUMC_2 __preg8(KSEG1 + 0x0C000004) /* Modem Control Register (R/W) */ #define VR4181_SIULS_2 __preg8(KSEG1 + 0x0C000005) /* Line Status Register (R/W) */ #define VR4181_SIUMS_2 __preg8(KSEG1 + 0x0C000006) /* Modem Status Register (R/W) */ #define VR4181_SIUSC_2 __preg8(KSEG1 + 0x0C000007) /* Scratch Register (R/W) */ #define VR4181_SIUIRSEL_2 __preg8(KSEG1 + 0x0C000008) /* SIU IrDA Selectot (R/W) */ #define VR4181_SIURESET_2 __preg8(KSEG1 + 0x0C000009) /* SIU Reset Register (R/W) */ #define VR4181_SIUCSEL_2 __preg8(KSEG1 + 0x0C00000A) /* IrDA Echo-back Control (R/W) */ #define VR4181_SIUACTMSK_2 __preg8(KSEG1 + 0x0C00000C) /* SIU Activity Mask Register (R/W) */ #define VR4181_SIUACTTMR_2 __preg8(KSEG1 + 0x0C00000E) /* SIU Activity Timer Register (R/W) */ // USB Module #define VR4181_USBINFIFO __preg16(KSEG1 + 0x0B000780) /* USB Bulk Input FIFO (Bulk In End Point) (W) */ #define VR4181_USBOUTFIFO __preg16(KSEG1 + 0x0B000782) /* USB Bulk Output FIFO (Bulk Out End Point) (R) */ #define VR4181_USBCTLFIFO __preg16(KSEG1 + 0x0B000784) /* USB Control FIFO (Control End Point) (W) */ #define VR4181_USBSTAT __preg16(KSEG1 + 0x0B000786) /* Interrupt Status Register (R/W) */ #define VR4181_USBINTMSK __preg16(KSEG1 + 0x0B000788) /* Interrupt Mask Register (R/W) */ #define VR4181_USBCTLREG __preg16(KSEG1 + 0x0B00078A) /* Control Register (R/W) */ #define VR4181_USBSTPREG __preg16(KSEG1 + 0x0B00078C) /* USB Transfer Stop Register (R/W) */ // LCD Controller #define VR4181_HRTOTALREG __preg16(KSEG1 + 0x0A000400) /* Horizontal total Register (R/W) */ #define VR4181_HRVISIBREG __preg16(KSEG1 + 0x0A000402) /* Horizontal Visible Register (R/W) */ #define VR4181_LDCLKSTREG __preg16(KSEG1 + 0x0A000404) /* Load clock start Register (R/W) */ #define VR4181_LDCLKNDREG __preg16(KSEG1 + 0x0A000406) /* Load clock end Register (R/W) */ #define VR4181_VRTOTALREG __preg16(KSEG1 + 0x0A000408) /* Vertical Total Register (R/W) */ #define VR4181_VRVISIBREG __preg16(KSEG1 + 0x0A00040A) /* Vertical Visible Register (R/W) */ #define VR4181_FVSTARTREG __preg16(KSEG1 + 0x0A00040C) /* FLM vertical start Register (R/W) */ #define VR4181_FVENDREG __preg16(KSEG1 + 0x0A00040E) /* FLM vertical end Register (R/W) */ #define VR4181_LCDCTRLREG __preg16(KSEG1 + 0x0A000410) /* LCD control Register (R/W) */ #define VR4181_LCDINRQREG __preg16(KSEG1 + 0x0A000412) /* LCD Interrupt request Register (R/W) */ #define VR4181_LCDCFGREG0 __preg16(KSEG1 + 0x0A000414) /* LCD Configuration Register 0 (R/W) */ #define VR4181_LCDCFGREG1 __preg16(KSEG1 + 0x0A000416) /* LCD Configuration Register 1 (R/W) */ #define VR4181_FBSTAD1REG __preg16(KSEG1 + 0x0A000418) /* Frame Buffer Start Address 1 Register (R/W) */ #define VR4181_FBSTAD2REG __preg16(KSEG1 + 0x0A00041A) /* Frame Buffer Start Address 2 Register (R/W) */ #define VR4181_FBNDAD1REG __preg16(KSEG1 + 0x0A000420) /* Frame Buffer End Address 1 Register (R/W) */ #define VR4181_FBNDAD2REG __preg16(KSEG1 + 0x0A000422) /* Frame Buffer End Address 2 register (R/W) */ #define VR4181_FHSTARTREG __preg16(KSEG1 + 0x0A000424) /* FLM horizontal Start Register (R/W) */ #define VR4181_FHENDREG __preg16(KSEG1 + 0x0A000426) /* FLM horizontal End Register (R/W) */ #define VR4181_PWRCONREG1 __preg16(KSEG1 + 0x0A000430) /* Power Control register 1 (R/W) */ #define VR4181_PWRCONREG2 __preg16(KSEG1 + 0x0A000432) /* Power Control register 2 (R/W) */ #define VR4181_LCDIMSKREG __preg16(KSEG1 + 0x0A000434) /* LCD Interrupt Mask register (R/W) */ #define VR4181_CPINDCTREG __preg16(KSEG1 + 0x0A00047E) /* Color palette Index and control Register (R/W) */ #define VR4181_CPALDATREG __preg32(KSEG1 + 0x0A000480) /* Color palette data register (32bits Register) (R/W) */ // physical address spaces #define VR4181_LCD 0x0a000000 #define VR4181_INTERNAL_IO_2 0x0b000000 #define VR4181_INTERNAL_IO_1 0x0c000000 #define VR4181_ISA_MEM 0x10000000 #define VR4181_ISA_IO 0x14000000 #define VR4181_ROM 0x18000000 // This is the base address for IO port decoding to which the 16 bit IO port address // is added. Defining it to 0 will usually cause a kernel oops any time port IO is // attempted, which can be handy for turning up parts of the kernel that make // incorrect architecture assumptions (by assuming that everything acts like a PC), // but we need it correctly defined to use the PCMCIA/CF controller: #define VR4181_PORT_BASE (KSEG1 + VR4181_ISA_IO) #define VR4181_ISAMEM_BASE (KSEG1 + VR4181_ISA_MEM) #endif /* __ASM_MIPS_VR4181_H */ |
|
From: Jun S. <ju...@us...> - 2001-09-22 04:27:18
|
Update of /cvsroot/linux-mips/linux/arch/mips/vr4181/common
In directory usw-pr-cvs1:/tmp/cvs-serv27047/arch/mips/vr4181/common
Added Files:
Makefile irq.c serial.c time.c
Log Message:
Initial re-structuring of vr41xx directory. More are coming to
actually get Osprey/Eagle building and running.
--- NEW FILE: Makefile ---
#
# Makefile for common code of NEC vr4181 based boards
#
# Note! Dependencies are done automagically by 'make dep', which also
# removes any old dependencies. DON'T put your own dependencies here
# unless it's something special (ie not a .c file).
#
.S.s:
$(CPP) $(CFLAGS) $< -o $*.s
.S.o:
$(CC) $(CFLAGS) -c $< -o $*.o
O_TARGET:= vr4181.o
obj-y := irq.o kbd_no.o serial.o time.o
include $(TOPDIR)/Rules.make
--- NEW FILE: irq.c ---
/*
* linux/arch/mips/vr41xx/irq.c
*
* Code to handle VR4181 IRQs plus some generic interrupt stuff.
*
* Copyright (C) 1992 Linus Torvalds
* Copyright (C) 1994, 1995, 1996, 1997 Ralf Baechle
* Copyright (C) 1999 Bradley D. LaRonde
* Copyright (C) 1999, 2000 Michael Klar
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
*/
#include <linux/init.h>
#include <linux/kernel_stat.h>
#include <linux/signal.h>
#include <linux/sched.h>
#include <linux/interrupt.h>
#include <linux/malloc.h>
#include <linux/random.h>
#include <linux/pm.h>
#include <asm/irq.h>
#include <asm/mipsregs.h>
#include <asm/gdb-stub.h>
#include <asm/vr4181/vr4181.h>
/* [jsun] HACK */
#define CONFIG_CPU_VR4181 y
#define DEVICE_IRQ_MASKL 0xffff
extern asmlinkage void vr41xx_handle_irq(void);
extern void breakpoint(void);
// This is used elsewhere
unsigned long spurious_count = 0;
static unsigned short irq_mask_probe[(VR4181_IRQ_MAX + 9)/16];
#define BIT_MASK(bit) ( 1 << (bit) )
#define MAKE_CP0_STATUS_IRQ_MASK(irq) ( BIT_MASK( (irq) + 8))
static inline void mask_irq(unsigned int irq)
{
if (irq < 8) {
// it's a cpu interrupt
unsigned short newstatus = read_32bit_cp0_register(CP0_STATUS);
newstatus &= ~((unsigned short)1 << (irq + 8));
set_cp0_status(ST0_IM, newstatus);
} else {
if (irq < 40) {
// it's an ICU interrupt
if (irq < 24) {
*VR4181_MSYSINT1REG &= ~((unsigned short)1 << (irq - 8));
} else {
*VR4181_MSYSINT2REG &= ~((unsigned short)1 << (irq - 24));
}
} else {
// it's a GPIO interrupt
#ifdef CONFIG_CPU_VR4181
*VR4181_GPINTMSK |= (unsigned short)1 << (irq - 40);
#else
if (irq < 56) {
*VR4181_MGIUINTLREG &= ~((unsigned short)1 << (irq - 40));
} else {
*VR4181_MGIUINTHREG &= ~((unsigned short)1 << (irq - 56));
}
#endif
}
}
}
static inline void unmask_irq(unsigned int irq)
{
if (irq < 8) {
// it's a cpu interrupt
unsigned short newstatus = read_32bit_cp0_register(CP0_STATUS);
newstatus |= ((unsigned short)1 << (irq + 8));
set_cp0_status(ST0_IM, newstatus);
} else {
if (irq < 40) {
// it's an ICU interrupt
if (irq < 24) {
*VR4181_MSYSINT1REG |= (unsigned short)1 << (irq - 8);
} else {
*VR4181_MSYSINT2REG |= (unsigned short)1 << (irq - 24);
}
} else {
// it's a GPIO interrupt (also ack edge-triggered or hold ints)
#ifdef CONFIG_CPU_VR4181
if (!((irq < 48 ? *VR4181_GPINTTYPL : *VR4181_GPINTTYPH) &
((unsigned short)2 << ((irq & 0x7) * 2))))
*VR4181_GPINTSTAT = (unsigned short)1 << (irq - 40);
*VR4181_GPINTMSK &= ~((unsigned short)1 << (irq - 40));
#else
if (irq < 56) {
if (*VR4181_GIUINTHTSELL & ((unsigned short)1 << (irq - 40)))
*VR4181_GIUINTSTATL = (unsigned short)1 << (irq - 40);
*VR4181_MGIUINTLREG |= (unsigned short)1 << (irq - 40);
} else {
if (*VR4181_GIUINTHTSELH & ((unsigned short)1 << (irq - 56)))
*VR4181_GIUINTSTATH = (unsigned short)1 << (irq - 56);
*VR4181_MGIUINTHREG |= (unsigned short)1 << (irq - 56);
}
#endif
}
}
}
/*
* Per-IRQ information, by not initializing, this gets filled with NULLs:
*/
typedef struct {
struct irqaction* irq_action; // info on low-level handler
int depth; // < 0: enabled, >= 0: disabled
} irq_info_t;
static irq_info_t irq_info[VR4181_IRQ_MAX + 1];
void inline disable_irq_nosync(unsigned int irq)
{
disable_irq(irq);
}
void disable_irq(unsigned int irq_nr)
{
unsigned long flags;
if (++irq_info[irq_nr].depth >= 0) {
save_and_cli(flags);
mask_irq(irq_nr);
restore_flags(flags);
}
}
void enable_irq(unsigned int irq_nr)
{
unsigned long flags;
#ifdef CONFIG_CPU_VR4122
if (irq_nr == VR4181_IRQ_GPIO14)
return;
#endif
if (--irq_info[irq_nr].depth < 0) {
save_and_cli(flags);
unmask_irq(irq_nr);
restore_flags(flags);
}
}
int get_irq_list(char *buf)
{
// make a human-readable list of irq actions
// used by /proc/interrupts
int i, len = 0;
struct irqaction *action;
for (i = 0; i <= VR4181_IRQ_MAX; i++) {
action = irq_info[i].irq_action;
if (!action)
continue;
len += sprintf(buf + len, "%2d: %8d %c %s",
i, kstat.irqs[0][i],
(action->flags & SA_INTERRUPT) ? '+' : ' ',
action->name);
for (action = action->next; action; action = action->next) {
len += sprintf(buf + len, ",%s %s",
(action->flags & SA_INTERRUPT) ? " +" : "",
action->name);
}
len += sprintf(buf + len, "\n");
}
return len;
}
atomic_t __mips_bh_counter;
asmlinkage void do_IRQ(int irq, struct pt_regs *regs)
{
// This handles all IRQ's that have been installed.
// It is called from int-handler.S.
// Actions without SA_INTERRUPT run with interrupts enabled
// and use the full signal-handling return.
// Actions with SA_INTERRUPT run with interrupts disabled.
struct irqaction *action;
int cpu = smp_processor_id();
irq_enter(cpu, irq);
kstat.irqs[cpu][irq]++;
// don't interrupt on this same irq again until we're finished
// also, it gets left masked if there is no action (see below)
mask_irq(irq);
action = irq_info[irq].irq_action;
if (action != 0) {
unsigned long flags = 0;
if (!(action->flags & SA_INTERRUPT))
__sti();
do {
// handle it
action->handler(irq, action->dev_id, regs);
flags |= action->flags;
action = action->next;
} while (action);
if (flags & SA_SAMPLE_RANDOM)
add_interrupt_randomness(irq);
__cli();
unmask_irq(irq);
}
irq_exit(cpu, irq);
// Unmasking and softirq handling is done for us
// currently by ret_from_irq in entry.S.
}
int add_irq_action(int irq, struct irqaction *new)
{
// put the specified action (new) at the end of the list of actions for this irq
int shared = 0;
struct irqaction *old, **p;
unsigned long flags;
p = &irq_info[irq].irq_action;
if ((old = *p) != NULL) {
if (!(old->flags & new->flags & SA_SHIRQ))
return -EBUSY;
// Shared interrupts must be all same type
if ((old->flags ^ new->flags) & SA_INTERRUPT)
return -EBUSY;
do {
p = &old->next;
old = *p;
} while (old);
shared = 1;
}
if (new->flags & SA_SAMPLE_RANDOM)
rand_initialize_irq(irq);
save_and_cli(flags);
*p = new;
if (!shared) {
irq_info[irq].depth = -1;
unmask_irq(irq);
}
restore_flags(flags);
return 0;
}
int request_irq(unsigned int irq,
void (*handler)(int, void *, struct pt_regs *),
unsigned long irqflags,
const char *devname,
void *dev_id)
{
int retval;
struct irqaction *action;
// some assertiveness
if (irq > VR4181_IRQ_MAX)
return -EINVAL;
if (!handler)
return -EINVAL;
// allocate a new action struct
action = (struct irqaction *) kmalloc(sizeof(struct irqaction), GFP_KERNEL);
if (!action)
return -ENOMEM;
// initialize it
action->handler = handler;
action->flags = irqflags;
action->mask = 0;
action->name = devname;
action->next = NULL;
action->dev_id = dev_id;
// add it to the list of actions for this irq
retval = add_irq_action(irq, action);
if (retval)
kfree(action);
return retval;
}
void free_irq(unsigned int irq, void *dev_id)
{
struct irqaction *action, **p;
unsigned long flags;
if (irq > VR4181_IRQ_MAX) {
printk("Error - trying to free invalid IRQ %d\n", irq);
return;
}
for (p = &irq_info[irq].irq_action; (action = *p) != NULL; p = &action->next) {
if (action->dev_id != dev_id)
continue;
// Found it - now free it
save_and_cli(flags);
*p = action->next;
if (!irq_info[irq].irq_action) {
irq_info[irq].depth = 0;
mask_irq(irq);
}
restore_flags(flags);
kfree(action);
return;
}
}
unsigned long probe_irq_on(void)
{
int i;
unsigned long delay;
// Note the lower 8 bits of irq_mask_probe[0] are not used. Also,
// we don't probe for IRQ 0, since no way to report (0 = no IRQ found)
irq_mask_probe[0] = read_32bit_cp0_register(CP0_STATUS);
irq_mask_probe[1] = *VR4181_MSYSINT1REG;
irq_mask_probe[2] = *VR4181_MSYSINT2REG;
#ifdef CONFIG_CPU_VR4181
irq_mask_probe[3] = ~*VR4181_GPINTMSK;
#else
irq_mask_probe[3] = *VR4181_MGIUINTLREG;
irq_mask_probe[4] = *VR4181_MGIUINTHREG;
#endif
for (i = VR4181_IRQ_MAX; i > 0; i--)
if (!irq_info[i].irq_action && i != VR4181_IRQ_TIMER)
enable_irq(i);
// Wait for spurious interrupts to mask themselves out again...
for (delay = jiffies + HZ/10; time_before(jiffies, delay); )
barrier(); // about 100ms of delay
irq_mask_probe[0] |= ~read_32bit_cp0_register(CP0_STATUS);
irq_mask_probe[1] |= ~*VR4181_MSYSINT1REG;
irq_mask_probe[2] |= ~*VR4181_MSYSINT2REG;
#ifdef CONFIG_CPU_VR4181
irq_mask_probe[3] |= *VR4181_GPINTMSK;
#else
irq_mask_probe[3] |= ~*VR4181_MGIUINTLREG;
irq_mask_probe[4] |= ~*VR4181_MGIUINTHREG;
#endif
return 0x12345678;
}
int probe_irq_off(unsigned long unused)
{
int i, irq_found, nr_irqs;
unsigned short tmp;
unsigned long flags;
if (unused != 0x12345678)
printk("Bad IRQ probe detected\n");
// The following mess unmasks the interrupts we enabled to autoprobe
// and finishes bit-processing irq_mask_probe at the same time
save_and_cli(flags);
tmp = read_32bit_cp0_register(CP0_STATUS);
set_cp0_status(ST0_IM, tmp & irq_mask_probe[0]);
irq_mask_probe[0] |= tmp;
tmp = *VR4181_MSYSINT1REG;
*VR4181_MSYSINT1REG = tmp & irq_mask_probe[1];
irq_mask_probe[1] |= tmp;
tmp = *VR4181_MSYSINT2REG;
*VR4181_MSYSINT2REG = tmp & irq_mask_probe[2];
irq_mask_probe[2] |= tmp;
#ifdef CONFIG_CPU_VR4181
tmp = ~*VR4181_GPINTMSK;
*VR4181_GPINTMSK = ~(tmp & irq_mask_probe[3]);
irq_mask_probe[3] |= tmp;
#else
tmp = *VR4181_MGIUINTLREG;
*VR4181_MGIUINTLREG = tmp & irq_mask_probe[3];
irq_mask_probe[3] |= tmp;
tmp = *VR4181_MGIUINTHREG;
*VR4181_MGIUINTHREG = tmp & irq_mask_probe[4];
irq_mask_probe[4] |= tmp;
#endif
restore_flags(flags);
nr_irqs = 0;
irq_found = 0;
for (i = VR4181_IRQ_MAX; i > 0; i--)
if (!(irq_mask_probe[(i + 8)/16] & ((unsigned short)1 << ((i + 8) & 15)))) {
irq_found = i;
nr_irqs++;
}
if (nr_irqs > 1)
irq_found = -irq_found;
return irq_found;
}
#ifdef CONFIG_PM
//
// Unlike the real pm_request callbacks, this one doesn't get registered
// with PM, and only gets called from do_hibernate and do_wakeup, because
// it has to happen in a certain order. It also assumes ints disabled.
//
void do_pm_irq_request(pm_request_t rqst)
{
static unsigned short irq_mask[(VR4181_IRQ_MAX + 9)/16];
unsigned int status;
switch (rqst) {
case PM_RESUME:
status = read_32bit_cp0_register(CP0_STATUS) & 0xffff00ff;
write_32bit_cp0_register(CP0_STATUS, status | irq_mask[0]);
*VR4181_MSYSINT1REG = irq_mask[1];
*VR4181_MSYSINT2REG = irq_mask[2];
#ifdef CONFIG_CPU_VR4181
*VR4181_GPINTMSK = irq_mask[3];
#else
*VR4181_MGIUINTLREG = irq_mask[3];
*VR4181_MGIUINTHREG = irq_mask[4];
#endif
break;
case PM_SUSPEND:
irq_mask[0] = read_32bit_cp0_register(CP0_STATUS) & 0xff00;
irq_mask[1] = *VR4181_MSYSINT1REG;
irq_mask[2] = *VR4181_MSYSINT2REG;
#ifdef CONFIG_CPU_VR4181
irq_mask[3] = *VR4181_GPINTMSK;
#else
irq_mask[3] = *VR4181_MGIUINTLREG;
irq_mask[4] = *VR4181_MGIUINTHREG;
#endif
break;
}
}
#endif // CONFIG_PM
static struct irqaction cascade = { NULL, SA_INTERRUPT, 0, "cascade", NULL, NULL };
static struct irqaction reserved = { NULL, SA_INTERRUPT, 0, "reserved", NULL, NULL };
void __init init_IRQ(void)
{
set_except_vector(0, vr41xx_handle_irq);
// Default all ICU IRQs to off ...
*VR4181_MSYSINT1REG = 0;
*VR4181_MSYSINT2REG = 0;
// We initialize the level 2 ICU registers to all bits disabled.
// After this, these registers are the resposibility of whatever
// driver requests the IRQ of the corresponding level 1 ICU bit.
// (except GIU, where each level 2 bit has its own IRQ)
#ifdef CONFIG_CPU_VR4122
*VR4181_MPCIINTREG = 0;
*VR4181_MSCUINTREG = 0;
*VR4181_MCSIINTREG = 0;
#else
*VR4181_MPIUINTREG = 0;
*VR4181_MAIUINTREG = 0;
*VR4181_MKIUINTREG = 0;
#endif
#ifdef CONFIG_CPU_VR4181
*VR4181_GPINTMSK = 0xffff;
#else
*VR4181_MGIUINTLREG = 0;
*VR4181_MDSIUINTREG = 0;
*VR4181_MGIUINTHREG = 0;
*VR4181_MFIRINTREG = 0;
#endif
barrier();
//
// NOTE: This may break autodetection on some devices. If so, an IRQ mask needs
// to be defined in vr41xx-platdep.h to disable some GPIO lines from interrupting,
// or the broken autodetect IRQ needs to be defined explicitly. This define is
// for documentation purposes, only turn it off for test/debug:
//
#define LET_ALL_GPIO_INPUTS_CAUSE_INTERRUPTS
#ifdef LET_ALL_GPIO_INPUTS_CAUSE_INTERRUPTS
// Initialize secondary IRQ mask to enable any GPIO line configured as an input.
// Note that the int won't be active until enabled in the primary mask, too.
#ifdef CONFIG_CPU_VR4181
{
unsigned int bits;
bits = (unsigned int)(*VR4181_GPMD1REG | 0xaaaa) << 16;
bits |= *VR4181_GPMD0REG | 0xaaaa;
bits &= bits >> 1;
bits |= 0xcccccccc;
bits &= bits >> 2;
bits |= 0xf0f0f0f0;
bits &= bits >> 4;
bits |= 0xff00;
bits &= bits >> 8;
*VR4181_SECIRQMASKL = ~bits & DEVICE_IRQ_MASKL;
}
#else
*VR4181_SECIRQMASKL = ~*VR4181_GIUIOSELL & DEVICE_IRQ_MASKL;
*VR4181_SECIRQMASKH = ~*VR4181_GIUIOSELH & DEVICE_IRQ_MASKH;
#endif
#endif // LET_ALL_GPIO_INPUTS_CAUSE_INTERRUPTS
// These don't really add handlers, these IRQs are never reported by the int
// vector handler. What these do is register the IRQ as non-sharable
add_irq_action(VR4181_IRQ_INT0, &cascade);
add_irq_action(VR4181_IRQ_GIU, &cascade);
add_irq_action(VR4181_IRQ_RTCL1, &reserved);
add_irq_action(VR4181_IRQ_RTCL2, &reserved);
#ifdef CONFIG_REMOTE_DEBUG
printk("Setting debug traps - please connect the remote debugger.\n");
set_debug_traps();
// you may move this line to whereever you want
breakpoint();
#endif
}
#ifdef CONFIG_PCMCIA
/*
* dummy functions needed for PCMCIA support for non-ISA systems (vr4122) - mikemac
*
*/
/*
* Return a mask of triggered interrupts (this
* can handle only legacy ISA interrupts).
*/
unsigned int
probe_irq_mask(unsigned long val)
{
return val;
}
#ifndef CONFIG_ISA
#define CS_IN_USE 0x1e
int try_irq(u_int Attributes, int irq, int specific)
{
return CS_IN_USE;
}
#endif /* CONFIG_ISA */
#endif /* CONFIG_PCMCIA */
--- NEW FILE: serial.c ---
/*
* linux/drivers/char/serial.c
* Serial (SIU) driver for NEC VR41xx CPUs, VR4102 and up only.
*
* Based almost entirely on linux/drivers/char/serial.c
* Modified for VR41xx by Michael Klar, mf...@po...
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
*/
#include <linux/config.h>
#include <linux/version.h>
/* [jsun] HACK */
#define MAX_VR_PORT 2
[...3799 lines suppressed...]
char mygetDebugChar(void)
{
if (!initialized) { /* need to init device first */
DbgInitSerial();
initialized = 1;
}
while ( !(*VR4181_SIULS & UART_LSR_DR) ) ;
barrier();
return(*VR4181_SIURB);
}
/*
Local variables:
compile-command: "gcc -D__KERNEL__ -I../../include -Wall -Wstrict-prototypes -O2 -fomit-frame-pointer -fno-strict-aliasing -D__SMP__ -pipe -fno-strength-reduce -march=i686 -DMODULE -DMODVERSIONS -include ../../include/linux/modversions.h -DEXPORT_SYMTAB -c serial.c"
End:
*/
--- NEW FILE: time.c ---
/*
* linux/arch/mips/vr41xx/time.c
*
* VR4181 timer interrupt using real-time clock.
*
* Copyright (C) 1991, 1992, 1995 Linus Torvalds
* Copyright (C) 1999 Bradley D. LaRonde
* Copyright (C) 2000 Michael Klar
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
*/
#include <linux/config.h>
#include <linux/init.h>
#include <linux/sched.h>
#include <linux/interrupt.h>
#include <linux/timex.h>
#include <linux/pm.h>
#include <asm/vr4181/vr4181.h>
extern int add_irq_action(int irq, struct irqaction *new);
extern volatile unsigned long wall_jiffies;
extern rwlock_t xtime_lock;
#define USECS_PER_JIFFY (1000000/HZ)
#define COUNTS_PER_JIFFY ((32768 + HZ/2) / HZ)
spinlock_t rtc_lock = SPIN_LOCK_UNLOCKED;
#ifdef CONFIG_RTC
unsigned long epoch_adj;
#else
#define epoch_adj 0
#endif
// per VR41xx docs, bad data can be read if between 2 counts
static inline unsigned short read_time_reg(volatile unsigned short *reg)
{
unsigned short value;
do {
value = *reg;
barrier();
} while (value != *reg);
return value;
}
unsigned long get_rtc_time(volatile unsigned short *reg)
{
unsigned short regh, regm, regl;
// why this crazy order, you ask? to guarantee that neither m
// nor l wrap before all 3 read
do {
regm = read_time_reg(reg + 1);
barrier();
regh = read_time_reg(reg + 2);
barrier();
regl = read_time_reg(reg);
} while (regm != read_time_reg(reg + 1));
return ((regh << 17) | (regm << 1) | (regl >> 15)) + epoch_adj;
}
void set_rtc_time(unsigned long settime, volatile unsigned short *reg)
{
unsigned short intreg;
unsigned long flags, timeval = settime - epoch_adj;
spin_lock_irqsave(&rtc_lock, flags);
intreg = *VR4181_RTCINTREG & 0x05;
barrier();
*reg = timeval << 15;
*(reg + 1) = timeval >> 1;
*(reg + 2) = timeval >> 17;
barrier();
// assume that any ints that just triggered are invalid, since the
// time value is written non-atomically in 3 separate regs
*VR4181_RTCINTREG = 0x05 ^ intreg;
spin_unlock_irqrestore(&rtc_lock, flags);
}
// must be called with ints disabled:
//
static unsigned long do_gettimeoffset(void)
{
unsigned short count;
unsigned long offset;
count = read_time_reg(VR4181_RTCL1CNTLREG);
if (count == 1)
offset = 0;
else
offset = (COUNTS_PER_JIFFY - count + 1) * 1000000 / 32768;
// detect if the counter wrapped, but int not serviced yet, being
// careful not to adjust if int happen after count was read just now
if (*VR4181_RTCINTREG & 0x0002 && (jiffies == wall_jiffies) && count != 2)
offset += USECS_PER_JIFFY;
return offset;
}
// This version of gettimeofday has about 30us resolution
void do_gettimeofday(struct timeval *tv)
{
unsigned long flags, lost;
read_lock_irqsave(&xtime_lock, flags);
*tv = xtime;
tv->tv_usec += do_gettimeoffset();
// xtime is atomically updated in timer_bh, wall_jiffies is
// updated in timer_bh, jiffies is updated in timer int, so this
// will be nonzero if the timer bottom half hasn't executed yet:
lost = jiffies - wall_jiffies;
read_unlock_irqrestore(&xtime_lock, flags);
while (lost--)
tv->tv_usec += USECS_PER_JIFFY;
while (tv->tv_usec >= 1000000) {
tv->tv_usec -= 1000000;
tv->tv_sec++;
}
}
void do_settimeofday(struct timeval *tv)
{
write_lock_irq(&xtime_lock);
// undo whatever correction gettimeofday would have done
tv->tv_usec -= do_gettimeoffset();
tv->tv_usec -= (jiffies - wall_jiffies) * USECS_PER_JIFFY;
if (tv->tv_usec < 0) {
tv->tv_usec += 1000000;
tv->tv_sec--;
}
xtime = *tv;
time_adjust = 0; // stop active adjtime()
time_status |= STA_UNSYNC;
time_maxerror = NTP_PHASE_LIMIT;
time_esterror = NTP_PHASE_LIMIT;
write_unlock_irq(&xtime_lock);
}
static unsigned long last_rtc_update;
/*
* timer_interrupt() needs to keep up the real-time clock,
* as well as call the "do_timer()" routine every clocktick
*/
static void timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
{
// Clear the interrupt.
*VR4181_RTCINTREG = 0x2;
do_timer(regs);
// If we have an externally synchronized Linux clock, then update
// CMOS clock accordingly every ~11 minutes.
if ((time_status & STA_UNSYNC) == 0 &&
xtime.tv_sec > last_rtc_update + 660) {
set_rtc_time(xtime.tv_sec, VR4181_ETIMELREG);
last_rtc_update = xtime.tv_sec;
}
}
struct irqaction timer_action = {
timer_interrupt, SA_INTERRUPT, 0,
"timer", NULL, NULL
};
#ifdef CONFIG_PM
static int pm_time_request(struct pm_dev *dev, pm_request_t rqst, void *data)
{
unsigned long flags;
switch (rqst) {
case PM_SUSPEND:
disable_irq(VR4181_IRQ_INT1);
break;
case PM_RESUME:
write_lock_irqsave(&xtime_lock, flags);
enable_irq(VR4181_IRQ_INT1);
xtime.tv_sec = get_rtc_time(VR4181_ETIMELREG);
xtime.tv_usec = 0;
// this shouldn't be necessary, but just to be safe...
*VR4181_RTCL1LREG = COUNTS_PER_JIFFY;
*VR4181_RTCL1HREG = 0;
write_unlock_irqrestore(&xtime_lock, flags);
break;
}
return 0;
}
static int __init pm_time_init(void)
{
pm_register(PM_SYS_DEV, PM_SYS_UNKNOWN, pm_time_request);
return 0;
}
__initcall(pm_time_init);
#endif
void __init time_init(void)
{
// Set default time near beginning of Linux VR epoch.
xtime.tv_sec = get_rtc_time(VR4181_ETIMELREG);
xtime.tv_usec = 0;
// Use RTCLong1 for the system timer.
// It has it's own cpu interrupt, is not T-Clock dependent,
// and has sufficient resolution.
// Set the RTCLong1 counter (32.768kHz) to expire in 1 / HZ second
*VR4181_RTCL1LREG = COUNTS_PER_JIFFY;
*VR4181_RTCL1HREG = 0;
// and ack any pending ints
*VR4181_RTCINTREG = 0x2;
// Grab the IRQ for the cpu interrupt, not the ICU interrupt
// The RTCLong1 ICU interrupt is always left unmasked
// This can't use request_irq() because it's too early for kmalloc
add_irq_action(VR4181_IRQ_INT1, &timer_action);
}
|
|
From: Jun S. <ju...@us...> - 2001-09-22 04:27:18
|
Update of /cvsroot/linux-mips/linux/arch/mips/vr4122/eagle
In directory usw-pr-cvs1:/tmp/cvs-serv27047/arch/mips/vr4122/eagle
Added Files:
Makefile irq.c pci.c prom.c setup.c
Log Message:
Initial re-structuring of vr41xx directory. More are coming to
actually get Osprey/Eagle building and running.
--- NEW FILE: Makefile ---
#
# Copyright 2001 MontaVista Software Inc.
# Author: Yoichi Yuasa
# yy...@mv... or so...@mv...
#
# Makefile for the NEC Eagle specific parts of the kernel
#
# Note! Dependencies are done automagically by 'make dep', which also
# removes any old dependencies. DON'T put your own dependencies here
# unless it's something special (ie not a .c file).
#
.S.s:
$(CPP) $(AFLAGS) $< -o $@
.S.o:
$(CC) $(AFLAGS) -c $< -o $@
O_TARGET := eagle.o
all: eagle.o
obj-y := irq.o pci.o prom.o setup.o
include $(TOPDIR)/Rules.make
--- NEW FILE: irq.c ---
/*
* BRIEF MODULE DESCRIPTION
* NEC Eagle interrupt routines.
*
* Copyright 2001 MontaVista Software Inc.
* Author: Yoichi Yuasa
* yy...@mv... or so...@mv...
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/spinlock.h>
#include <asm/io.h>
#include <asm/mipsregs.h>
#include <asm/vr4122/vr4122.h>
#include <asm/vr4122/eagle.h>
#ifdef CONFIG_REMOTE_DEBUG
extern void set_debug_traps(void);
extern void breakpoint(void);
#endif
extern asmlinkage void vr4122_handle_int(void);
extern void __init init_generic_irq(void);
spinlock_t vr4122_icu_lock = SPIN_LOCK_UNLOCKED;
static void enable_cpucore_irq(unsigned int irq)
{
unsigned long flags, status;
spin_lock_irqsave(&vr4122_icu_lock, flags);
status = read_32bit_cp0_register(CP0_STATUS);
status |= (1UL << (irq + 8));
set_cp0_status(ST0_IM, status);
spin_unlock_irqrestore(&vr4122_icu_lock, flags);
}
static void disable_cpucore_irq(unsigned int irq)
{
unsigned long flags, status;
spin_lock_irqsave(&vr4122_icu_lock, flags);
status = read_32bit_cp0_register(CP0_STATUS);
status &= ~(1UL << (irq + 8));
set_cp0_status(ST0_IM, status);
spin_unlock_irqrestore(&vr4122_icu_lock, flags);
}
static unsigned int startup_cpucore_irq(unsigned int irq)
{
enable_cpucore_irq(irq);
return 0; /* never anything pending */
}
#define shutdown_cpucore_irq disable_cpucore_irq
#define mask_and_ack_cpucore_irq disable_cpucore_irq
static void end_cpucore_irq(unsigned int irq)
{
if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
enable_cpucore_irq(irq);
}
static struct hw_interrupt_type cpucore_irq_type = {
"CPU CORE",
startup_cpucore_irq,
shutdown_cpucore_irq,
enable_cpucore_irq,
disable_cpucore_irq,
mask_and_ack_cpucore_irq,
end_cpucore_irq,
NULL
};
/*=======================================================================*/
static void enable_sysint1_irq(unsigned int irq)
{
unsigned long flags;
unsigned short val;
spin_lock_irqsave(&vr4122_icu_lock, flags);
val = readw(VR4122_MSYSINT1REG);
val |= (u16)1 << (irq - 8);
writew(val, VR4122_MSYSINT1REG);
spin_unlock_irqrestore(&vr4122_icu_lock, flags);
}
static void disable_sysint1_irq(unsigned int irq)
{
unsigned long flags;
unsigned short val;
spin_lock_irqsave(&vr4122_icu_lock, flags);
val = readw(VR4122_MSYSINT1REG);
val &= ~((u16)1 << (irq - 8));
writew(val, VR4122_MSYSINT1REG);
spin_unlock_irqrestore(&vr4122_icu_lock, flags);
}
static unsigned int startup_sysint1_irq(unsigned int irq)
{
enable_sysint1_irq(irq);
return 0; /* never anything pending */
}
#define shutdown_sysint1_irq disable_sysint1_irq
#define mask_and_ack_sysint1_irq disable_sysint1_irq
static void end_sysint1_irq(unsigned int irq)
{
if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
enable_sysint1_irq(irq);
}
static struct hw_interrupt_type sysint1_irq_type = {
"SYSINT1",
startup_sysint1_irq,
shutdown_sysint1_irq,
enable_sysint1_irq,
disable_sysint1_irq,
mask_and_ack_sysint1_irq,
end_sysint1_irq,
NULL
};
/*=======================================================================*/
static void enable_sysint2_irq(unsigned int irq)
{
unsigned long flags;
unsigned short val;
spin_lock_irqsave(&vr4122_icu_lock, flags);
if (irq == VR4122_IRQ_DSIU) {
val = readw(VR4122_MDSIUINTREG);
val |= 0x0800;
writew(val, VR4122_MDSIUINTREG);
}
val = readw(VR4122_MSYSINT2REG);
val |= (u16)1 << (irq - 24);
writew(val, VR4122_MSYSINT2REG);
spin_unlock_irqrestore(&vr4122_icu_lock, flags);
}
static void disable_sysint2_irq(unsigned int irq)
{
unsigned long flags;
unsigned short val;
spin_lock_irqsave(&vr4122_icu_lock, flags);
if (irq == VR4122_IRQ_DSIU) {
writew(0, VR4122_MDSIUINTREG);
}
val = readw(VR4122_MSYSINT2REG);
val &= ~((u16)1 << (irq - 24));
writew(val, VR4122_MSYSINT2REG);
spin_unlock_irqrestore(&vr4122_icu_lock, flags);
}
static unsigned int startup_sysint2_irq(unsigned int irq)
{
enable_sysint2_irq(irq);
return 0; /* never anything pending */
}
#define shutdown_sysint2_irq disable_sysint2_irq
#define mask_and_ack_sysint2_irq disable_sysint2_irq
static void end_sysint2_irq(unsigned int irq)
{
if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
enable_sysint2_irq(irq);
}
static struct hw_interrupt_type sysint2_irq_type = {
"SYSINT2",
startup_sysint2_irq,
shutdown_sysint2_irq,
enable_sysint2_irq,
disable_sysint2_irq,
mask_and_ack_sysint2_irq,
end_sysint2_irq,
NULL
};
/*=======================================================================*/
static void enable_giuintl_irq(unsigned int irq)
{
unsigned long flags;
unsigned short val, mask;
spin_lock_irqsave(&vr4122_icu_lock, flags);
if (irq == VR4122_IRQ_GPIO5)
*(volatile unsigned char *)KSEG1ADDR(0x0dffffe0) |= 0x10;
mask = (u16)1 << (irq - 40);
writew(mask, VR4122_GIUINTSTATL);
val = readw(VR4122_MGIUINTLREG);
val |= mask;
writew(val, VR4122_MGIUINTLREG);
val = readw(VR4122_GIUINTENL);
val |= mask;
writew(val, VR4122_GIUINTENL);
spin_unlock_irqrestore(&vr4122_icu_lock, flags);
}
static void disable_giuintl_irq(unsigned int irq)
{
unsigned long flags;
unsigned short val, mask;
spin_lock_irqsave(&vr4122_icu_lock, flags);
if (irq == 45)
*(volatile unsigned char *)KSEG1ADDR(0x0dffffe0) &= ~0x10;
mask = (u16)1 << (irq - 40);
val = readw(VR4122_GIUINTENL);
val &= ~mask;
writew(val, VR4122_GIUINTENL);
val = readw(VR4122_MGIUINTLREG);
val &= ~mask;
writew(val, VR4122_MGIUINTLREG);
writew(mask, VR4122_GIUINTSTATL);
spin_unlock_irqrestore(&vr4122_icu_lock, flags);
}
static unsigned int startup_giuintl_irq(unsigned int irq)
{
enable_giuintl_irq(irq);
return 0; /* never anything pending */
}
#define shutdown_giuintl_irq disable_giuintl_irq
#define mask_and_ack_giuintl_irq disable_giuintl_irq
static void end_giuintl_irq(unsigned int irq)
{
if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
enable_giuintl_irq(irq);
}
static struct hw_interrupt_type giuintl_irq_type = {
"GIUINTL",
startup_giuintl_irq,
shutdown_giuintl_irq,
enable_giuintl_irq,
disable_giuintl_irq,
mask_and_ack_giuintl_irq,
end_giuintl_irq,
NULL
};
/*=======================================================================*/
static void enable_giuinth_irq(unsigned int irq)
{
unsigned long flags;
unsigned short val, mask;
spin_lock_irqsave(&vr4122_icu_lock, flags);
mask = (u16)1 << (irq - 56);
writew(mask, VR4122_GIUINTSTATH);
val = readw(VR4122_MGIUINTHREG);
val |= mask;
writew(val, VR4122_MGIUINTHREG);
val = readw(VR4122_GIUINTENH);
val |= mask;
writew(val, VR4122_GIUINTENH);
spin_unlock_irqrestore(&vr4122_icu_lock, flags);
}
static void disable_giuinth_irq(unsigned int irq)
{
unsigned long flags;
unsigned short val, mask;
spin_lock_irqsave(&vr4122_icu_lock, flags);
mask = (u16)1 << (irq - 56);
val= readw(VR4122_GIUINTENH);
val &= ~mask;
writew(val, VR4122_GIUINTENH);
val = readw(VR4122_MGIUINTHREG);
val &= ~mask;
writew(val, VR4122_MGIUINTHREG);
writew(mask, VR4122_GIUINTSTATH);
spin_unlock_irqrestore(&vr4122_icu_lock, flags);
}
static unsigned int startup_giuinth_irq(unsigned int irq)
{
enable_giuinth_irq(irq);
return 0; /* never anything pending */
}
#define shutdown_giuinth_irq disable_giuinth_irq
#define mask_and_ack_giuinth_irq disable_giuinth_irq
static void end_giuinth_irq(unsigned int irq)
{
if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
enable_giuinth_irq(irq);
}
static struct hw_interrupt_type giuinth_irq_type = {
"GIUINTH",
startup_giuinth_irq,
shutdown_giuinth_irq,
enable_giuinth_irq,
disable_giuinth_irq,
mask_and_ack_giuinth_irq,
end_giuinth_irq,
NULL
};
/*=======================================================================*/
void __init init_vr4122_icu_irqs(void)
{
unsigned long flags;
int i;
spin_lock_irqsave(&vr4122_icu_lock, flags);
/* Default all ICU IRQs to off ... */
writew(0, VR4122_MSYSINT1REG);
writew(0, VR4122_MGIUINTLREG);
writew(0, VR4122_MDSIUINTREG);
writew(0, VR4122_MSYSINT2REG);
writew(0, VR4122_MGIUINTHREG);
writew(0, VR4122_MFIRINTREG);
writew(0, VR4122_MPCIINTREG);
writew(0, VR4122_MSCUINTREG);
writew(0, VR4122_MCSIINTREG);
#if 0
writew(0, VR4122_MBCUINTREG);
#endif
writew(0, VR4122_GIUINTENL);
writew(0, VR4122_GIUINTENH);
writew(0xffff, VR4122_GIUINTSTATL);
writew(0xffff, VR4122_GIUINTSTATH);
barrier();
for (i = 0; i < NR_IRQS; i++) {
irq_desc[i].status = IRQ_DISABLED;
irq_desc[i].action = 0;
irq_desc[i].depth = 1;
if (i < 8)
irq_desc[i].handler = &cpucore_irq_type;
else if (i < 24)
irq_desc[i].handler = &sysint1_irq_type;
else if (i < 40)
irq_desc[i].handler = &sysint2_irq_type;
else if (i < 56)
irq_desc[i].handler = &giuintl_irq_type;
else if (i < 72)
irq_desc[i].handler = &giuinth_irq_type;
}
spin_unlock_irqrestore(&vr4122_icu_lock, flags);
}
static struct irqaction cascade = {
no_action, 0, 0, "cascade", NULL, NULL
};
static struct irqaction reserved = {
no_action, 0, 0, "reserved", NULL, NULL
};
void __init init_IRQ(void)
{
memset(irq_desc, 0, sizeof(irq_desc));
init_generic_irq();
init_vr4122_icu_irqs();
setup_irq(VR4122_IRQ_INT0, &cascade);
setup_irq(VR4122_IRQ_GIU, &cascade);
setup_irq(VR4122_IRQ_RTCL1, &reserved);
setup_irq(VR4122_IRQ_RTCL2, &reserved);
set_except_vector(0, vr4122_handle_int);
#ifdef CONFIG_REMOTE_DEBUG
set_debug_traps();
/* you may move this line to whereever you want */
breakpoint();
#endif
}
--- NEW FILE: pci.c ---
/*
* THIS CODE AND INFORMATION IS PROVIDED "AS IS" WITHOUT WARRANTY OF
* ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR FITNESS FOR A
* PARTICULAR PURPOSE.
* Copyright (C) NEC Corporation 2001.
*/
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pci.h>
#include <linux/ioport.h>
#include <asm/types.h>
#include <asm/vr4122/vr4122.h>
#include <asm/vr4122/eagle.h>
#ifdef CONFIG_EAGLE_REV1
#define EAGLE_REV1_ON { \
unsigned short val; \
val = readw(VR4122_GIUPIODL); \
val |= VR4122_GIUPIODL_GPIO9; \
writew(val, VR4122_GIUPIODL); }
#define EAGLE_REV1_OFF { \
unsigned short val; \
val = readw(VR4122_GIUPIODL); \
val &= VR4122_GIUPIODL_GPIO9; \
writew(val, VR4122_GIUPIODL); }
#else
#define EAGLE_REV1_ON
#define EAGLE_REV1_OFF
#endif
#define MAX_PCI_DEV 64
extern struct pci_ops vr4122_pci_ops;
extern void vr4122_pcibios_init(void);
static unsigned long memstart = 0x10200000;
static unsigned long memlimit = 0x15ffffff;
static unsigned long iostart = 0x00010000;
static unsigned long iolimit = 0x01ffffff;
static int pcidevs = 0;
static unsigned long ReadConfig32(int bus, int dev, int func, int reg)
{
unsigned long config;
if (bus == 0) {
/* type 0 configuration */
if (dev < 11 || dev >= 32 || func >= 8 || reg >= 256)
return 0xffffffff;
EAGLE_REV1_ON;
writel((reg & 0xfc) | (func << 8) | (1 << dev), VR4122_PCICONFAREG);
}
else {
/* type 1 configuration */
if (bus >= 256 || dev >= 32 || func >= 8 || reg >= 256)
return 0xffffffff;
EAGLE_REV1_OFF;
writel(1 | (reg & 0xfc) | (func << 8) | (dev << 11) | (bus << 16),
VR4122_PCICONFAREG);
}
config = readl(VR4122_PCICONFDREG);
EAGLE_REV1_ON;
return config;
}
static void WriteConfig32(int bus, int dev, int func, int reg, unsigned long data)
{
if (bus == 0) {
/* type 0 configuration */
if (dev<11 || dev>=32 || func>=8 || reg>=256)
return;
EAGLE_REV1_ON;
writel((reg & 0xfc) | (func << 8) | (1 << dev),VR4122_PCICONFAREG);
}
else {
/* type 1 configuration */
if (bus>=256 || dev>=32 || func>=8 || reg>=256)
return;
EAGLE_REV1_OFF;
writel(1 | (reg & 0xfc) | (func << 8) | (dev << 11) | (bus << 16),
VR4122_PCICONFAREG);
}
writel(data, VR4122_PCICONFDREG);
EAGLE_REV1_ON;
}
static void map_resource(int bus, int dev, int func, int nbase)
{
unsigned long val, reg, next, req, base, size;
/* Scan all base registers */
next = 0x10;
while (next < 0x10 + nbase * 4) {
reg = next;
next = reg + 4;
WriteConfig32(bus, dev, func, reg, 0xFFFFFFFF);
val = ReadConfig32(bus, dev, func, reg);
if (val & 1) {
req = ~(val & 0xFFFFFFFC)+1;
if (req & (req - 1))
continue;
if (req == 0)
continue;
size = req > 0x1000 ? req : 0x1000;
base = (iostart + size - 1) & ~(size - 1);
if ((base + size - 1) > iolimit)
continue;
iostart = base + size;
}
else {
req = ~(val & 0xFFFFFFF0) + 1;
if (req & (req - 1))
continue;
if (req == 0)
continue;
switch (val & 0x00000006) {
case 0:
break;
case 2:
continue;
case 4:
WriteConfig32(bus, dev, func, reg + 4, 0);
next += 4;
break;
case 6:
continue;
}
size = req > 0x1000 ? req : 0x1000;
base = (memstart + size - 1) & ~(size - 1);
if ((base + size - 1) > memlimit)
continue;
memstart = base + size;
}
WriteConfig32(bus, dev, func, reg, base);
}
}
static int __init eagle_pcidev_init(int bus, int dev, int func)
{
u32 id, status, bhlc;
int nbase = 0;
/* Probe device */
writel(0xff00ff00, VR4122_INTCNTSTAREG);
id = ReadConfig32(bus, dev, func, PCI_VENDOR_ID);
status = readl(VR4122_INTCNTSTAREG);
writel(0xff00ff00, VR4122_INTCNTSTAREG);
if (status & 0x000000ff)
return 1;
if ((id & 0xffff) == 0xffff)
return 1;
if (pcidevs >= MAX_PCI_DEV)
return 1;
pcidevs++;
bhlc = ReadConfig32(bus, dev, func, PCI_CACHE_LINE_SIZE);
switch ((bhlc >> 16) & 0x7f) {
case 0:
nbase = 6;
break;
case 1:
nbase = 2;
break;
case 2:
nbase = 1;
break;
default:
}
map_resource(bus, dev, func, nbase);
/* Set master latency timer and cache line size */
WriteConfig32(bus, dev, func, PCI_CACHE_LINE_SIZE, 0x8004);
/* Enable device and clear all status */
WriteConfig32(bus, dev, func, PCI_COMMAND,
ReadConfig32(bus, dev, func, PCI_COMMAND) | 0xffff0000 |
PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
PCI_COMMAND_SERR);
return 0;
}
static void __init eagle_pcibus_init(int bus)
{
int dev, func;
unsigned long type;
for (dev = 0; dev < 32; dev++) {
for (func = 0; func < 8; func++) {
if (eagle_pcidev_init(bus, dev, func)) {
type = ReadConfig32(bus, dev, func,
PCI_CACHE_LINE_SIZE);
if ((type & 0x00800000) == 0)
break;
}
}
}
}
void __init pcibios_update_irq(struct pci_dev *dev, int irq)
{
/* assume it's a generic PCI interrupt */
dev->irq = VR4122_IRQ_PCI;
/* if it's wired differently, correct the assumption */
switch (dev->vendor) {
case PCI_VENDOR_ID_NEC:
switch (dev->device) {
case PCI_DEVICE_ID_NEC_VRC4173_BCU:
case PCI_DEVICE_ID_NEC_VRC4173_AC97:
case PCI_DEVICE_ID_NEC_VRC4173_CARDU:
case PCI_DEVICE_ID_NEC_VRC4173_USB: /* all three share the same IRQ */
dev->irq = VR4122_IRQ_VRC4173;
break;
}
break;
case PCI_VENDOR_ID_MEDIAQ:
if (dev->device == PCI_DEVICE_ID_MEDIAQ_MQ200)
dev->irq = VR4122_IRQ_MQ200;
break;
}
}
static void __init pcibios_fixup_irqs(void)
{
struct pci_dev *dev;
int slot_num;
int cnt = 0;
pci_for_each_dev(dev) {
slot_num = PCI_SLOT(dev->devfn);
pcibios_update_irq(dev, cnt++);
}
}
void __init pcibios_fixup_bus(struct pci_bus *b)
{
}
void pcibios_update_resource(struct pci_dev *dev, struct resource *root,
struct resource *res, int resource)
{
}
void __init pcibios_init(void)
{
vr4122_pcibios_init();
ioport_resource.start = 0;
ioport_resource.end = VR4122_PCI_IO_SIZE;
iomem_resource.start = VR4122_PCI_MEM_BASE;
iomem_resource.end = VR4122_PCI_MEM_BASE + VR4122_PCI_MEM_SIZE;
eagle_pcibus_init(0);
(void)pci_scan_bus(0, &vr4122_pci_ops, NULL);
pcibios_fixup_irqs();
}
int __init pcibios_enable_device(struct pci_dev *dev)
{
/* Not needed, sine we enable all devices at startup */
return 0;
}
void __init pcibios_align_resource(void *data, struct resource *res,
unsigned long size)
{
/* Nothing to do. */
}
char * __init pcibios_setup(char *str)
{
/* Nothing to do for now. */
return str;
}
struct pci_fixup pcibios_fixups[] = { { 0 } };
--- NEW FILE: prom.c ---
/*
* BRIEF MODULE DESCRIPTION
* PROM library initialisation code for NEC Vr4122.
*
* Copyright 2001 MontaVista Software Inc.
* Author: Yoichi Yuasa
* yy...@mv... or so...@mv...
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/config.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/string.h>
#include <asm/bootinfo.h>
char arcs_cmdline[COMMAND_LINE_SIZE];
/* Do basic initialization */
void __init prom_init(int argc, char **argv,
unsigned long magic, int *prom_vec)
{
int mem_size = CONFIG_NEC_EAGLE_MEM_SIZE;
int i;
/*
* collect args and prepare cmd_line
*/
for (i = 1; i < argc; i++) {
strcat(arcs_cmdline, argv[i]);
if (i < (argc - 1))
strcat(arcs_cmdline, " ");
}
#if defined(CONFIG_SERIAL_CONSOLE)
/* to use 38400 ttyS0 serial console */
strcat(arcs_cmdline, " console=ttyS0,38400");
#endif
mips_machgroup = MACH_GROUP_NEC_VR41XX;
#ifdef CONFIG_NEC_EAGLE
mips_machtype = MACH_NEC_EAGLE;
#endif
/* Add memory region */
switch (mem_size) {
case 32:
add_memory_region(0, 32 << 20, BOOT_MEM_RAM);
break;
case 64:
add_memory_region(0, 64 << 20, BOOT_MEM_RAM);
break;
default:
panic("Memory size error\n");
}
}
void __init prom_free_prom_memory (void)
{
}
--- NEW FILE: setup.c ---
/*
* BRIEF MODULE DESCRIPTION
* Setup for NEC Eagle board.
*
* Copyright 2001 MontaVista Software Inc.
* Author: Yoichi Yuasa
* yy...@mv... or so...@mv...
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/init.h>
#include <linux/console.h>
#include <asm/addrspace.h>
#include <asm/io.h>
#include <asm/reboot.h>
#include <asm/time.h>
#include <asm/vr4122/vr4122.h>
#include <asm/vr4122/eagle.h>
extern void vr4122_restart(char *command);
extern void vr4122_halt(void);
extern void vr4122_power_off(void);
extern void vr4122_time_init(void);
extern void vr4122_timer_setup(struct irqaction *irq);
void __init nec_eagle_setup(void)
{
unsigned long clock;
unsigned short val;
val = readw(VR4122_CLKSPEEDREG);
clock = (18432000 * 98) / (val & 0x1f);
printk("PClock: %ldHz\n", clock);
clock = clock / ((val & 0x700) >> 8);
printk("VTClock: %ldHz\n", clock);
clock = clock / (2 << ((val & 0x1000) >> 12));
printk("TClock: %ldHz\n", clock);
mips_counter_frequency = clock / 4;
mips_io_port_base = VR4122_IO_PORT_BASE;
_machine_restart = vr4122_restart;
_machine_halt = vr4122_halt;
_machine_power_off = vr4122_power_off;
board_time_init = vr4122_time_init;
board_timer_setup = vr4122_timer_setup;
#ifdef CONFIG_FB
conswitchp = &dummy_con;
#endif
/* Select RS-232C */
val = readw(VR4122_SIUIRSEL);
val &= ~VR4122_SIUIRSEL_SIRSEL;
writew(val, VR4122_SIUIRSEL);
/* Supply DSIU and SIU clock */
vr4122_clock_supply(VR4122_CMUCLKMSK_MSKSIU);
vr4122_clock_supply(VR4122_CMUCLKMSK_MSKDSIU);
vr4122_clock_supply(VR4122_CMUCLKMSK_MSKSSIU);
}
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From: Jun S. <ju...@us...> - 2001-09-22 04:27:18
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Update of /cvsroot/linux-mips/linux/arch/mips/vr4181/osprey
In directory usw-pr-cvs1:/tmp/cvs-serv27047/arch/mips/vr4181/osprey
Added Files:
Makefile dbg_io.c int_handler.S prom.c reset.c setup.c
Log Message:
Initial re-structuring of vr41xx directory. More are coming to
actually get Osprey/Eagle building and running.
--- NEW FILE: Makefile ---
#
# Makefile for common code of NEC Osprey board
#
# Note! Dependencies are done automagically by 'make dep', which also
# removes any old dependencies. DON'T put your own dependencies here
# unless it's something special (ie not a .c file).
#
.S.s:
$(CPP) $(CFLAGS) $< -o $*.s
.S.o:
$(CC) $(CFLAGS) -c $< -o $*.o
O_TARGET:= osprey.o
obj-y := setup.o prom.o reset.o int_handler.o dbg_io.o
include $(TOPDIR)/Rules.make
--- NEW FILE: dbg_io.c ---
#include <linux/config.h>
#if defined(CONFIG_REMOTE_DEBUG)
/* --- CONFIG --- */
typedef unsigned char uint8;
typedef unsigned int uint32;
/* --- END OF CONFIG --- */
#define UART16550_BAUD_2400 2400
#define UART16550_BAUD_4800 4800
#define UART16550_BAUD_9600 9600
#define UART16550_BAUD_19200 19200
#define UART16550_BAUD_38400 38400
#define UART16550_BAUD_57600 57600
#define UART16550_BAUD_115200 115200
#define UART16550_PARITY_NONE 0
#define UART16550_PARITY_ODD 0x08
#define UART16550_PARITY_EVEN 0x18
#define UART16550_PARITY_MARK 0x28
#define UART16550_PARITY_SPACE 0x38
#define UART16550_DATA_5BIT 0x0
#define UART16550_DATA_6BIT 0x1
#define UART16550_DATA_7BIT 0x2
#define UART16550_DATA_8BIT 0x3
#define UART16550_STOP_1BIT 0x0
#define UART16550_STOP_2BIT 0x4
/* ----------------------------------------------------- */
/* === CONFIG === */
/* [jsun] we use the debug board serial port for kdb */
#define BASE 0xb7fffff0
#define MAX_BAUD 115200
#define REG_OFFSET 1
static int remoteDebugInitialized = 1;
/* === END OF CONFIG === */
/* register offset */
#define OFS_RCV_BUFFER 0
#define OFS_TRANS_HOLD 0
#define OFS_SEND_BUFFER 0
#define OFS_INTR_ENABLE (1*REG_OFFSET)
#define OFS_INTR_ID (2*REG_OFFSET)
#define OFS_DATA_FORMAT (3*REG_OFFSET)
#define OFS_LINE_CONTROL (3*REG_OFFSET)
#define OFS_MODEM_CONTROL (4*REG_OFFSET)
#define OFS_RS232_OUTPUT (4*REG_OFFSET)
#define OFS_LINE_STATUS (5*REG_OFFSET)
#define OFS_MODEM_STATUS (6*REG_OFFSET)
#define OFS_RS232_INPUT (6*REG_OFFSET)
#define OFS_SCRATCH_PAD (7*REG_OFFSET)
#define OFS_DIVISOR_LSB (0*REG_OFFSET)
#define OFS_DIVISOR_MSB (1*REG_OFFSET)
/* memory-mapped read/write of the port */
#define UART16550_READ(y) (*((volatile uint8*)(BASE + y)))
#define UART16550_WRITE(y, z) ((*((volatile uint8*)(BASE + y))) = z)
void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop)
{
/* disable interrupts */
UART16550_WRITE(OFS_INTR_ENABLE, 0);
/* set up buad rate */
{
uint32 divisor;
/* set DIAB bit */
UART16550_WRITE(OFS_LINE_CONTROL, 0x80);
/* set divisor */
divisor = MAX_BAUD / baud;
UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff);
UART16550_WRITE(OFS_DIVISOR_MSB, (divisor & 0xff00) >> 8);
/* clear DIAB bit */
UART16550_WRITE(OFS_LINE_CONTROL, 0x0);
}
/* set data format */
UART16550_WRITE(OFS_DATA_FORMAT, data | parity | stop);
}
uint8 getDebugChar(void)
{
if (!remoteDebugInitialized) {
remoteDebugInitialized = 1;
debugInit(UART16550_BAUD_38400,
UART16550_DATA_8BIT,
UART16550_PARITY_NONE, UART16550_STOP_1BIT);
}
while ((UART16550_READ(OFS_LINE_STATUS) & 0x1) == 0);
return UART16550_READ(OFS_RCV_BUFFER);
}
int putDebugChar(uint8 byte)
{
if (!remoteDebugInitialized) {
remoteDebugInitialized = 1;
debugInit(UART16550_BAUD_38400,
UART16550_DATA_8BIT,
UART16550_PARITY_NONE, UART16550_STOP_1BIT);
}
while ((UART16550_READ(OFS_LINE_STATUS) & 0x20) == 0);
UART16550_WRITE(OFS_SEND_BUFFER, byte);
return 1;
}
#endif
--- NEW FILE: int_handler.S ---
/*
* linux/arch/mips/vr41xx/int-handler.S
*
* Copyright (C) 1995, 1996, 1997 Paul M. Antoine and Harald Koerfgen
*
* Written by Ralf Baechle and Andreas Busse, modified for DECStation
* support by Paul Antoine and Harald Koerfgen.
*
* completly rewritten:
* Copyright (C) 1998 Harald Koerfgen
*
* Adapted to the VR4181 and almost entirely rewritten:
* Copyright (C) 1999 Bradley D. LaRonde and Michael Klar
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
*/
#include <asm/asm.h>
#include <asm/regdef.h>
#include <asm/mipsregs.h>
#include <asm/stackframe.h>
#include <asm/vr4181/vr4181.h>
/* jsun HACK */
#define CONFIG_CPU_VR4181 y
.text
.set noreorder
/*
* Interrupt handler for VR41xx based devices
*
* In a zealous attempt to save CPU cycles, we don't worry about making the code
* readable and instead optimize for the most frequently occurring ints (the
* timer int IRQ 3 and the ICU ints that cascade off IRQ 2), while keeping a
* priority scheme that actually makes some sense:
*
* Highest ---- CPU IP3 - Int1: RTClong1 IRQ 3
* CPU IP4 - Int2: RTClong2 IRQ 4
* CPU IP5 - Int3: HSP IRQ 5
* CPU IP6 - Int4: unused IRQ 6
* CPU IP7 - counter IRQ 7
* ICU SYSINT1REG bit 0 IRQ 8
* ...
* ICU SYSINT1REG bit 7 IRQ 15
* GPIO 0 IRQ 40
* ...
* GPIO 31 IRQ 71
* ICU SYSINT1REG bit 9 IRQ 17
* ...
* ICU SYSINT1REG bit 15 IRQ 23
* ICU SYSINT2REG bit 0 IRQ 24
* ...
* ICU SYSINT2REG bit 15 IRQ 39
* CPU IP0 - software 1 IRQ 0
* Lowest --- CPU IP1 - software 2 IRQ 1
*
* IRQ 2 is the cascade to the ICU (CPU IP2, Int0)
*
* then we just return, if multiple IRQs are pending then we will just take
* another exception immediately.
*
*/
.align 5
NESTED(vr41xx_handle_irq, PT_SIZE, ra)
.set noat
SAVE_ALL
CLI
.set at
.set noreorder
// Get the pending interrupts
mfc0 t0,CP0_CAUSE
// Isolate the allowed ones by anding with irq mask
mfc0 t2,CP0_STATUS
andi t0,0xff00
and t0,t2
andi t1,t0,0x0800 // check for IRQ 3
bnez t1,handle_it
li a0,3
andi t1,t0,0xf000 // check for IRQ 4-7
bnez t1,1f
andi t1,t0,0x0400 // check for IRQ 2
bnez t1,icu_int
lui t3,%hi(VR4181_SYSINT1REG)
beqz t0,go_spurious // check for IRQ 0-1
li a0,-1
sll t0,4
1: andi t1,t0,0x1000
srl t0,1
beqz t1,1b
addiu a0,1
b handle_it
nop
/*
* In the interest of speed, we implement a 3 tier check for which bit
* in the ICU level 1 interrupt registers is active. First, we determine
* which 16-bit register (1 or 2). Second, we narrow it down to which
* group of 4 bits, then we get the exact bit. a0 holds the IRQ number.
* Since we always add both 4 and 1 to a0, we initalize it to 5 less than
* the lowest IRQ number for each ICU level 1 register
*/
icu_int: // see delay slot instruction from branch that got us here
lhu t0,%lo(VR4181_SYSINT1REG)(t3)
lhu t2,%lo(VR4181_MSYSINT1REG)(t3)
/*
* OK, this next instruction deserves some explanation. The timer interrupt
* (a few others are similar, but the timer interrupt happens... well... all
* the time) comes in on both CPU int1 (IRQ 3) and ICU SYSINT1 bit 2 (IRQ 10),
* and since we check IRQ 3 before even loading the value of SYSINT1, it is
* possible for a timer interrupt to occur between the time we load CP0_STATUS to
* check IRQ 3 and the time we load SYSINT1REG to check IRQ 10. This will only
* happen when we're in the middle of servicing another interrupt, so we just
* ignore IRQ 10 (and a few others that behave similarly) and keep looking for
* the interrupt that actually caused the exception. When we re-enable
* interrupts, the timer int will immediately re-trigger and be detected as IRQ 3.
*/
and t0,0xfffb
and t0,t2
beqz t0,2f
andi t1,t0,0x01ff // check for GIU int
xori t1,0x0100 // (and no higher priority SYSINT1 int)
bnez t1,1f
li a0,3
// if it is, break out further
#ifdef CONFIG_CPU_VR4181
lui t3,%hi(VR4181_GPINTMSK)
lhu t0,%lo(VR4181_GPINTMSK)(t3)
lhu t2,%lo(VR4181_GPINTSTAT)(t3)
xori t0, 0xffff
and t0,t2
bnez t0,1f
li a0,35
#else
lhu t0,%lo(VR4181_GIUINTLREG)(t3)
lhu t2,%lo(VR4181_MGIUINTLREG)(t3)
li a0,35
and t0,t2
bnez t0,1f
lhu t2,%lo(VR4181_MGIUINTHREG)(t3)
lhu t0,%lo(VR4181_GIUINTHREG)(t3)
// load delay stall
and t0,t2
bnez t0,1f
li a0,51
#endif
go_spurious: j spurious_interrupt
nop
2: lhu t0,%lo(VR4181_SYSINT2REG)(t3)
lhu t2,%lo(VR4181_MSYSINT2REG)(t3)
#ifdef CONFIG_CPU_VR4181
and t0,0xfffe // see above comment
#else
and t0,0xfffa // see above comment
#endif
and t0,t2
beqz t0,go_spurious
li a0,19
1: andi t1,t0,0x000f
addi a0,4
beqzl t1,1b // the beqzl will cancel the last
srl t0,4 // shift so we don't lose the bits
1: andi t1,t0,0x0001
addi a0,1
beqz t1,1b
srl t0,1
handle_it: jal do_IRQ
move a1,sp
j ret_from_irq
nop
END(vr41xx_handle_irq)
--- NEW FILE: prom.c ---
/***********************************************************************
*
* Copyright 2001 MontaVista Software Inc.
* Author: js...@mv... or js...@ju...
*
* arch/mips/vr4181/osprey/prom.c
* prom code for osprey.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
***********************************************************************
*/
#include <linux/init.h>
#include <linux/config.h>
#include <linux/kernel.h>
#include <linux/string.h>
#include <linux/mm.h>
#include <linux/bootmem.h>
#include <asm/bootinfo.h>
#include <asm/addrspace.h>
char arcs_cmdline[COMMAND_LINE_SIZE];
/*
* [jsun] right now we assume it is the nec debug monitor, which does
* not pass any arguments.
*/
void __init prom_init()
{
strcpy(arcs_cmdline, "ether=0,0x03fe0300,eth0 "
// strcpy(arcs_cmdline, "ether=0,0x0300,eth0 "
"video=vr4181fb:xres:240,yres:320,bpp:8");
mips_machgroup = MACH_GROUP_NEC_VR41XX;
mips_machtype = MACH_NEC_OSPREY;
/* 16MB fixed */
add_memory_region(0, 16 << 20, BOOT_MEM_RAM);
}
void __init prom_free_prom_memory(void)
{
}
void __init prom_fixup_mem_map(unsigned long start, unsigned long end)
{
}
--- NEW FILE: reset.c ---
/*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* Copyright (C) 1997, 2001 Ralf Baechle
* Copyright 2001 MontaVista Software Inc.
* Author: js...@mv... or js...@ju...
*/
#include <linux/sched.h>
#include <linux/mm.h>
#include <asm/io.h>
#include <asm/pgtable.h>
#include <asm/processor.h>
#include <asm/reboot.h>
#include <asm/system.h>
void nec_osprey_restart(char *command)
{
set_cp0_status((ST0_BEV | ST0_ERL), (ST0_BEV | ST0_ERL));
set_cp0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
flush_cache_all();
write_32bit_cp0_register(CP0_WIRED, 0);
__asm__ __volatile__("jr\t%0"::"r"(0xbfc00000));
}
void nec_osprey_halt(void)
{
printk(KERN_NOTICE "\n** You can safely turn off the power\n");
while (1)
__asm__(".set\tmips3\n\t"
"wait\n\t"
".set\tmips0");
}
void nec_osprey_power_off(void)
{
nec_osprey_halt();
}
--- NEW FILE: setup.c ---
/*
* linux/arch/mips/vr4181/setup.c
*
* VR41xx setup routines
*
* Copyright (C) 1999 Bradley D. LaRonde
* Copyright (C) 1999, 2000 Michael Klar
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
*/
#include <linux/config.h>
#include <linux/console.h>
#include <linux/ide.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <asm/reboot.h>
#include <asm/vr4181/vr4181.h>
#include <asm/io.h>
#include <linux/pc_keyb.h>
extern struct kbd_ope no_kbd_ops;
struct semaphore vr4181_dma_sem;
// This enables the CF hacks below, to be replaced with real CF driver eventually
#if defined(CONFIG_EVEREX_FREESTYLE)
#define CF_HACK
#else
// If CF doesn't work on your device, try changing this to #define:
#undef CF_HACK
#endif
#ifdef CONFIG_TCIC
#define TCIC_BASE 0x240
#define TCIC_MODE 0x08
#define TCIC_AUX 0x0E
#define TCIC_MODE_PGMMASK 0x1f
#define TCIC_AUX_ILOCK (6<<5)
#define TCIC_ILOCK_CRESET 0x04
#endif
extern void nec_osprey_restart(char* c);
extern void nec_osprey_halt(void);
extern void nec_osprey_power_off(void);
#if defined(CF_HACK) || defined(CONFIG_I82365)
void __init put_cf_reg(unsigned char reg, unsigned char val)
{
#ifdef CONFIG_CPU_VR4181
*VR4181_PCCARDINDEX = reg;
barrier();
*VR4181_PCCARDDATA = val;
#else
outb(reg, 0x3e0);
outb(val, 0x3e1);
#endif
}
#endif
#if defined(CONFIG_NEC_OSPREY) || defined(CONFIG_IBM_WORKPAD) || \
defined(CONFIG_NEC_MOBILEGEAR2_R300) || \
defined(CONFIG_NEC_MOBILEGEAR2_R310) || \
defined(CONFIG_NEC_MOBILEGEAR2_R430) || \
defined(CONFIG_NEC_MOBILEGEAR2_R530) || \
defined(CONFIG_NEC_MOBILEGEAR2_R700) || \
defined(CONFIG_NEC_MOBILEGEAR2_R730) || \
defined(CONFIG_DOCOMO_SIGMARION) || \
defined(CONFIG_AGENDA_VR3)
// extern void platdep_setup(void);
void platdep_setup(void) {}
#else
void platdep_setup(void) {}
#endif
void __init nec_osprey_setup(void)
{
mips_io_port_base = VR4181_PORT_BASE;
isa_slot_offset = VR4181_ISAMEM_BASE;
#ifdef CONFIG_BLK_DEV_IDE
ide_ops = &vr4181_ide_ops;
#endif
#ifdef CONFIG_FB
conswitchp = &dummy_con;
#endif
// reset the PC card, and power off
#ifdef CONFIG_I82365
put_cf_reg(0x03, 0x20); // socket 0
put_cf_reg(0x43, 0x20); // socket 1
put_cf_reg(0x02, 0x00); // socket 0
put_cf_reg(0x42, 0x00); // socket 1
#endif
#ifdef CONFIG_TCIC
{
u_char mode;
mode = (inb(TCIC_BASE+TCIC_MODE) & TCIC_MODE_PGMMASK) | TCIC_AUX_ILOCK;
outb(mode, TCIC_BASE+TCIC_MODE);
outb(TCIC_ILOCK_CRESET, TCIC_BASE+TCIC_AUX);
}
#endif
#ifdef CF_HACK
// this is a nasty hack to initialize the CF registers, eventually this
// is to be replaced with a real CF controller driver
{
unsigned char i;
unsigned char cfinitdata[] = { 0x90, 0x63, 0x00, 0x35, 0x00, 0x55,
0x76, 0x03, 0x77, 0x03, 0x70, 0x01, 0x78, 0x01, 0x10, 0x00,
0x1f, 0x00, 0xf0, 0x7f, 0x00, 0x00, 0x20, 0x00, 0xe4, 0x00,
0xe0, 0x3f, 0x00, 0x02, 0xe5, 0x00, 0xed, 0x00, 0x1b, 0x3f,
0x00, 0x00, 0xee, 0x00, 0xf6, 0x00, 0x00, 0x00, 0x00, 0x01,
0xf7, 0x00, 0xff, 0x00, 0x00, 0x00 };
#ifdef CONFIG_CPU_VR4181
// Enable CF, not key scan.
*VR4181_KEYEN = 0;
// Unmask all CF IRQs for now except for IRQ 3 (which makes it fail)
// I think the bit sense in reversed from what User Manual states
*VR4181_INTMSKREG = 0xdeb0;
// Set CF wait states.
*VR4181_CFG_REG_1 = 1;
#else
#warning "Generic CF hack in use, assuming non-i82365 registers set up prior to boot"
#endif
put_cf_reg(0x02, 0x10);
udelay(1);
for (i = 0x02; i < 0x36; i++)
put_cf_reg(i, cfinitdata[i-2]);
// enable the IO and mem windows, now that start and stop values set up
put_cf_reg(0x06, 0xdf);
// reset the card
put_cf_reg(0x03, 0x23);
udelay(1);
put_cf_reg(0x03, 0x63);
mdelay(30);
// now set up CF config register (this assumes it is a CF card...)
writeb(0x43, ioremap(0x10200, 1));
}
#endif
_machine_restart = nec_osprey_restart;
_machine_halt = nec_osprey_halt;
_machine_power_off = nec_osprey_power_off;
/* setup resource limit */
ioport_resource.end = 0xffffffff;
iomem_resource.end = 0xffffffff;
// Insure that vr4181_dma_sem is initialized as unlocked, even
// in the case of a failed hibernate/wakeup:
init_MUTEX(&vr4181_dma_sem);
// Do platform-dependent setup.
// This is mostly stuff that doesn't fit well anywhere else.
platdep_setup();
/* [jsun] hack */
/*
printk("[jsun] hack to change external ISA control register, %x -> %x\n",
(*VR4181_XISACTL),
(*VR4181_XISACTL) | 0x2);
*VR4181_XISACTL |= 0x2;
*/
// *VR4181_GPHIBSTH = 0x2000;
// *VR4181_GPMD0REG = 0x00c0;
// *VR4181_GPINTEN = 1<<6;
/* [jsun] I believe this will get the interrupt type right
* for the ether port.
*/
*VR4181_GPINTTYPL = 0x3000;
}
|
|
From: Jun S. <ju...@us...> - 2001-09-22 04:27:18
|
Update of /cvsroot/linux-mips/linux/arch/mips/vr41xx In directory usw-pr-cvs1:/tmp/cvs-serv27047/arch/mips/vr41xx Removed Files: Makefile dbg_io.c irq.c kbd_no.c reset.c serial.c time.c Log Message: Initial re-structuring of vr41xx directory. More are coming to actually get Osprey/Eagle building and running. --- Makefile DELETED --- --- dbg_io.c DELETED --- --- irq.c DELETED --- --- kbd_no.c DELETED --- --- reset.c DELETED --- --- serial.c DELETED --- --- time.c DELETED --- |
|
From: Jun S. <ju...@us...> - 2001-09-22 04:27:18
|
Update of /cvsroot/linux-mips/linux/arch/mips/vr4122/common
In directory usw-pr-cvs1:/tmp/cvs-serv27047/arch/mips/vr4122/common
Added Files:
Makefile cmu.c dbg_io.c icu.c kbd.c pci.c reset.c time.c
Log Message:
Initial re-structuring of vr41xx directory. More are coming to
actually get Osprey/Eagle building and running.
--- NEW FILE: Makefile ---
#
# Copyright 2001 MontaVista Software Inc.
# Author: Yoichi Yuasa
# yy...@mv... or so...@mv...
#
# Makefile for the NEC Vr4122 CPU, generic files.
#
# Note! Dependencies are done automagically by 'make dep', which also
# removes any old dependencies. DON'T put your own dependencies here
# unless it's something special (ie not a .c file).
#
.S.s:
$(CPP) $(CFLAGS) $< -o $*.s
.S.o:
$(CC) $(CFLAGS) -c $< -o $*.o
all: vr4122.o
O_TARGET := vr4122.o
export-objs := serial.o
obj-y := cmu.o icu.o int-handler.o kbd.o reset.o time.o
obj-$(CONFIG_PCI) += pci.o
obj-$(CONFIG_REMOTE_DEBUG) += dbg_io.o
int-handler.o: int-handler.S
include $(TOPDIR)/Rules.make
--- NEW FILE: cmu.c ---
/*
* BRIEF MODULE DESCRIPTION
* NEC Vr4122 Clock Mask Unit routines.
*
* Copyright 2001 MontaVista Software Inc.
* Author: Yoichi Yuasa
* yy...@mv... or so...@mv...
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/spinlock.h>
#include <linux/interrupt.h>
#include <asm/io.h>
#include <asm/vr4122/vr4122.h>
spinlock_t vr4122_cmu_lock = SPIN_LOCK_UNLOCKED;
void vr4122_clock_supply(unsigned short mask)
{
unsigned long flags;
unsigned short val;
write_lock_irqsave(&vr4122_cmu_lock, flags);
val = readw(VR4122_CMUCLKMSK);
val |= mask;
writew(val, VR4122_CMUCLKMSK);
write_unlock_irqrestore(&vr4122_cmu_lock, flags);
}
void vr4122_clock_mask(unsigned short mask)
{
unsigned long flags;
unsigned short val;
write_lock_irqsave(&vr4122_cmu_lock, flags);
val = readw(VR4122_CMUCLKMSK);
val &= ~mask;
writew(val, VR4122_CMUCLKMSK);
write_unlock_irqrestore(&vr4122_cmu_lock, flags);
}
--- NEW FILE: dbg_io.c ---
#include <linux/config.h>
#ifdef CONFIG_REMOTE_DEBUG
/* --- CONFIG --- */
/* we need uint32 uint8 */
typedef unsigned char uint8;
typedef unsigned short uint16;
typedef unsigned int uint32;
/* --- END OF CONFIG --- */
#define UART16550_BAUD_2400 2400
#define UART16550_BAUD_4800 4800
#define UART16550_BAUD_9600 9600
#define UART16550_BAUD_19200 19200
#define UART16550_BAUD_38400 38400
#define UART16550_BAUD_57600 57600
#define UART16550_BAUD_115200 115200
#define UART16550_PARITY_NONE 0
#define UART16550_PARITY_ODD 0x08
#define UART16550_PARITY_EVEN 0x18
#define UART16550_PARITY_MARK 0x28
#define UART16550_PARITY_SPACE 0x38
#define UART16550_DATA_5BIT 0x0
#define UART16550_DATA_6BIT 0x1
#define UART16550_DATA_7BIT 0x2
#define UART16550_DATA_8BIT 0x3
#define UART16550_STOP_1BIT 0x0
#define UART16550_STOP_2BIT 0x4
/* ----------------------------------------------------- */
/* === CONFIG === */
/* [stevel] we use the IT8712 serial port for kgdb */
#define DEBUG_BASE 0xAF000820 /* Vr4122 DSIU base address */
#define MAX_BAUD 115200
/* === END OF CONFIG === */
/* register offset */
#define OFS_RCV_BUFFER 0
#define OFS_TRANS_HOLD 0
#define OFS_SEND_BUFFER 0
#define OFS_INTR_ENABLE 1
#define OFS_INTR_ID 2
#define OFS_DATA_FORMAT 3
#define OFS_LINE_CONTROL 3
#define OFS_MODEM_CONTROL 4
#define OFS_RS232_OUTPUT 4
#define OFS_LINE_STATUS 5
#define OFS_MODEM_STATUS 6
#define OFS_RS232_INPUT 6
#define OFS_SCRATCH_PAD 7
#define OFS_DIVISOR_LSB 0
#define OFS_DIVISOR_MSB 1
/* memory-mapped read/write of the port */
#define UART16550_READ(y) (*((volatile uint8*)(DEBUG_BASE + y)))
#define UART16550_WRITE(y,z) ((*((volatile uint8*)(DEBUG_BASE + y))) = z)
void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop)
{
uint16 mask;
/* disable interrupts */
UART16550_WRITE(OFS_INTR_ENABLE, 0);
/* turn on the clocks to the serial port */
mask = *((volatile uint16 *)(0xAF000808));
mask &= ~0x0001;
*((volatile uint16 *)(0xAF000808)) = mask;
mask = *((volatile uint16 *)(0xAF000060));
mask |= 0x0802;
*((volatile uint16 *)(0xAF000060)) = mask;
/* set up buad rate */
{
uint32 divisor;
/* set DIAB bit */
UART16550_WRITE(OFS_LINE_CONTROL, 0x80);
/* set divisor */
divisor = MAX_BAUD / baud;
UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff);
UART16550_WRITE(OFS_DIVISOR_MSB, (divisor & 0xff00)>>8);
/* clear DIAB bit */
UART16550_WRITE(OFS_LINE_CONTROL, 0x0);
}
/* set data format */
UART16550_WRITE(OFS_DATA_FORMAT, data | parity | stop);
}
static int remoteDebugInitialized = 0;
uint8 getDebugChar(void)
{
if (!remoteDebugInitialized) {
remoteDebugInitialized = 1;
debugInit(UART16550_BAUD_115200,
UART16550_DATA_8BIT,
UART16550_PARITY_NONE,
UART16550_STOP_1BIT);
}
while((UART16550_READ(OFS_LINE_STATUS) & 0x1) == 0);
return UART16550_READ(OFS_RCV_BUFFER);
}
int putDebugChar(uint8 byte)
{
if (!remoteDebugInitialized) {
remoteDebugInitialized = 1;
debugInit(UART16550_BAUD_115200,
UART16550_DATA_8BIT,
UART16550_PARITY_NONE,
UART16550_STOP_1BIT);
}
while ((UART16550_READ(OFS_LINE_STATUS) &0x20) == 0);
UART16550_WRITE(OFS_SEND_BUFFER, byte);
return 1;
}
#endif
--- NEW FILE: icu.c ---
/*
* BRIEF MODULE DESCRIPTION
* Interrupt dispatcher for NEC Vr4122 Interrupt Control Unit.
*
* Copyright 2001 MontaVista Software Inc.
* Author: Yoichi Yuasa
* yy...@mv... or so...@mv...
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <asm/io.h>
#include <asm/types.h>
#include <asm/vr4122/vr4122.h>
static void giuint_irqdispatch(struct pt_regs *regs)
{
u16 pendl, pendh, maskl, maskh;
int i = 0;
pendl = readw(VR4122_GIUINTLREG);
pendh = readw(VR4122_GIUINTHREG);
maskl = readw(VR4122_MGIUINTLREG);
maskh = readw(VR4122_MGIUINTHREG);
pendl &= maskl;
pendh &= maskh;
if (pendl) {
for (i = 0; i < 16; i++) {
if (pendl & 0x0001) {
do_IRQ(VR4122_GIUINTL_IRQ_BASE + i, regs);
return;
}
pendl >>= 1;
}
}
else if (pendh) {
for (i = 0; i < 16; i++) {
if (pendh & 0x0001) {
do_IRQ(VR4122_GIUINTH_IRQ_BASE + i, regs);
return;
}
pendh >>= 1;
}
}
}
asmlinkage void int0_icu_irqdispatch(struct pt_regs *regs)
{
u16 pend1, pend2, mask1, mask2;
int i;
pend1 = readw(VR4122_SYSINT1REG);
pend2 = readw(VR4122_SYSINT2REG);
mask1 = readw(VR4122_MSYSINT1REG);
mask2 = readw(VR4122_MSYSINT2REG);
pend1 &= mask1;
pend2 &= mask2;
if (pend1) {
if ((pend1 & 0x01ff) == 0x0100) {
giuint_irqdispatch(regs);
return;
}
else {
for (i = 0; i < 16; i++) {
if (pend1 & 0x0001) {
do_IRQ(VR4122_SYSINT1_IRQ_BASE + i, regs);
return;
}
pend1 >>= 1;
}
}
}
else if (pend2) {
for (i = 0; i < 16; i++) {
if (pend2 & 0x0001) {
do_IRQ(VR4122_SYSINT2_IRQ_BASE + i, regs);
return;
}
pend2 >>= 1;
}
}
}
--- NEW FILE: kbd.c ---
/*
* linux/arch/mips/vr4122/common/kbd.c
*
* Allows CONFIG_VT without keyboard (KIU) driver
*
* Copyright (C) 1999 Bradley D. LaRonde
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
*/
#include <linux/sched.h>
#include <linux/errno.h>
#include <linux/init.h>
void kbd_leds(unsigned char leds)
{
return;
}
int kbd_setkeycode(unsigned int scancode, unsigned int keycode)
{
return (scancode == keycode) ? 0 : -EINVAL;
}
int kbd_getkeycode(unsigned int scancode)
{
return scancode;
}
int kbd_translate(unsigned char scancode, unsigned char *keycode,
char raw_mode)
{
*keycode = scancode;
return 1;
}
char kbd_unexpected_up(unsigned char keycode)
{
return 0x80;
}
void __init kbd_init_hw(void)
{
}
--- NEW FILE: pci.c ---
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* PCI support for NEC Vr4122.
*
* Copyright (C) 2000 Mike McDonald
*/
#include <linux/config.h>
#include <linux/delay.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/types.h>
#include <asm/byteorder.h>
#include <asm/io.h>
#include <asm/vr4122/vr4122.h>
#ifdef CONFIG_PCI
#define mkaddr(dev, reg) \
do { \
if (dev->bus->number == 0) { \
if (PCI_SLOT(dev->devfn) < 11 || \
PCI_SLOT(dev->devfn) >= 32 || \
PCI_FUNC(dev->devfn) >= 8 || \
reg >= 256) \
return 0xFFFFFFFF; \
*(volatile u32 *)VR4122_PCICONFAREG = \
(reg & 0xFC) | \
( PCI_FUNC(dev->devfn) << 8) | \
(1 << PCI_SLOT(dev->devfn)); \
} else { \
if (dev->bus->number >= 256 || \
PCI_SLOT(dev->devfn) >= 32 || \
PCI_FUNC(dev->devfn) >=8 || \
reg >= 256) \
return 0xFFFFFFFF; \
*(volatile u32 *)VR4122_PCICONFAREG = 1 | \
(reg & 0xFC) | \
(dev->devfn << 8) | \
(dev->bus->number << 16); \
} \
} while (0);
/*
* We can't address 8 and 16 bit words directly. Instead we have to
* read/write a 32bit word and mask/modify the data we actually want.
*/
int vr4122_pcibios_read_config_byte(struct pci_dev *dev,
int where, unsigned char *val)
{
u32 res;
mkaddr(dev, where);
res = readl(VR4122_PCICONFDREG);
*val = (le32_to_cpu(res) >> ((where & 3) << 3)) & 0xff;
return PCIBIOS_SUCCESSFUL;
}
int vr4122_pcibios_read_config_word(struct pci_dev *dev,
int where, unsigned short *val)
{
u32 res;
if (where & 1)
return PCIBIOS_BAD_REGISTER_NUMBER;
mkaddr(dev, where);
res = readl(VR4122_PCICONFDREG);
*val = (le32_to_cpu(res) >> ((where & 3) << 3)) & 0xffff;
return PCIBIOS_SUCCESSFUL;
}
int vr4122_pcibios_read_config_dword(struct pci_dev *dev,
int where, unsigned int *val)
{
u32 res;
if (where & 3)
return PCIBIOS_BAD_REGISTER_NUMBER;
mkaddr(dev, where);
res = readl(VR4122_PCICONFDREG);
*val = le32_to_cpu(res);
return PCIBIOS_SUCCESSFUL;
}
int vr4122_pcibios_write_config_byte(struct pci_dev *dev,
int where, unsigned char val)
{
mkaddr(dev, where);
writeb(val, VR4122_PCICONFDREG + (where & 3));
return PCIBIOS_SUCCESSFUL;
}
int vr4122_pcibios_write_config_word(struct pci_dev *dev,
int where, unsigned short val)
{
if (where & 1)
return PCIBIOS_BAD_REGISTER_NUMBER;
mkaddr(dev, where);
writew(le16_to_cpu(val), VR4122_PCICONFDREG + (where & 3));
return PCIBIOS_SUCCESSFUL;
}
int vr4122_pcibios_write_config_dword(struct pci_dev *dev,
int where, unsigned int val)
{
if (where & 3)
return PCIBIOS_BAD_REGISTER_NUMBER;
mkaddr(dev, where);
writel(le32_to_cpu(val), VR4122_PCICONFDREG);
return PCIBIOS_SUCCESSFUL;
}
struct pci_ops vr4122_pci_ops = {
vr4122_pcibios_read_config_byte,
vr4122_pcibios_read_config_word,
vr4122_pcibios_read_config_dword,
vr4122_pcibios_write_config_byte,
vr4122_pcibios_write_config_word,
vr4122_pcibios_write_config_dword
};
void __init vr4122_pcibios_init(void)
{
u32 dummy;
/* Enable PCI clock */
vr4122_clock_supply(VR4122_CMUCLKMSK_MSKPCIU);
udelay(100);
/* Set master memory & I/O windows */
*(volatile u32 *)VR4122_PCIMMAW1REG = 0x100f9010;
*(volatile u32 *)VR4122_PCIMMAW2REG = 0x140fd014;
*(volatile u32 *)VR4122_PCIMIOAWREG = 0x160fd000;
/* Set target memory windows */
*(volatile u32 *)VR4122_PCITAW1REG = 0x00081000;
*(volatile u32 *)VR4122_PCIMBA1REG = 0x00000000;
*(volatile u32 *)VR4122_PCITAW2REG = 0x00000000;
*(volatile u32 *)VR4122_PCIMAILBAREG = 0x00000000;
/* Clear bus error */
dummy = *(volatile u32 *)VR4122_BUSERRADREG;
*(volatile u32 *)VR4122_PCICLKSELREG = 0x00000000; /* PCIckl = VRCKL/2 */
*(volatile u32 *)VR4122_PCITRDYVREG = 100;
*(volatile u32 *)VR4122_PCICACHELSREG = 0x00008004;
udelay(100);
*(volatile u32 *)VR4122_PCIENREG = 0x00000004;
*(volatile u32 *)VR4122_PCICOMMANDREG = 0x00000147;
mdelay(3);
}
#endif /* CONFIG_PCI */
--- NEW FILE: reset.c ---
/*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* Copyright (C) 1997, 2001 Ralf Baechle
* Copyright 2001 MontaVista Software Inc.
* Author: js...@mv... or js...@ju...
*/
#include <linux/sched.h>
#include <linux/mm.h>
#include <asm/io.h>
#include <asm/pgtable.h>
#include <asm/processor.h>
#include <asm/reboot.h>
#include <asm/system.h>
void vr4122_restart(char *command)
{
set_cp0_status((ST0_BEV | ST0_ERL), (ST0_BEV | ST0_ERL));
set_cp0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
flush_cache_all();
write_32bit_cp0_register(CP0_WIRED, 0);
__asm__ __volatile__("jr\t%0"::"r"(0xbfc00000));
}
void vr4122_halt(void)
{
printk(KERN_NOTICE "\n** You can safely turn off the power\n");
while (1);
}
void vr4122_power_off(void)
{
vr4122_halt();
}
--- NEW FILE: time.c ---
/*
* BRIEF MODULE DESCRIPTION
* NEC Vr4122 RTC Unit routines.
*
* Copyright 2001 MontaVista Software Inc.
* Author: Yoichi Yuasa
* yy...@mv... or so...@mv...
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/spinlock.h>
#include <asm/io.h>
#include <asm/time.h>
#include <asm/vr4122/vr4122.h>
spinlock_t vr4122_rtc_lock = SPIN_LOCK_UNLOCKED;
static inline unsigned short read_etime_register(unsigned long addr)
{
unsigned short val;
do {
val = readw(addr);
} while (val != readw(addr));
return val;
}
static unsigned long vr4122_rtc_get_time(void)
{
unsigned short etimel, etimem, etimeh;
do {
etimem = read_etime_register(VR4122_ETIMEMREG);
etimeh = read_etime_register(VR4122_ETIMEHREG);
etimel = read_etime_register(VR4122_ETIMELREG);
} while (etimem != read_etime_register(VR4122_ETIMEMREG));
return ((etimeh << 17) | (etimem << 1) | (etimel >> 15));
}
static int vr4122_rtc_set_time(unsigned long sec)
{
unsigned long flags;
spin_lock_irqsave(&vr4122_rtc_lock, flags);
writew(sec << 15, VR4122_ETIMELREG);
writew(sec >> 1, VR4122_ETIMEMREG);
writew(sec >> 17, VR4122_ETIMEHREG);
spin_unlock_irqrestore(&vr4122_rtc_lock, flags);
return 0;
}
void vr4122_time_init(void)
{
rtc_get_time = vr4122_rtc_get_time;
rtc_set_time = vr4122_rtc_set_time;
}
void vr4122_timer_setup(struct irqaction *irq)
{
unsigned int count;
count = read_32bit_cp0_register(CP0_COUNT);
write_32bit_cp0_register (CP0_COMPARE, count + (mips_counter_frequency / HZ));
setup_irq(VR4122_IRQ_TIMER, irq);
}
|
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From: Jun S. <ju...@us...> - 2001-09-22 04:27:18
|
Update of /cvsroot/linux-mips/linux/arch/mips/vr41xx/vr4121 In directory usw-pr-cvs1:/tmp/cvs-serv27047/arch/mips/vr41xx/vr4121 Removed Files: Makefile cmu.c icu.c int_handler.S Log Message: Initial re-structuring of vr41xx directory. More are coming to actually get Osprey/Eagle building and running. --- Makefile DELETED --- --- cmu.c DELETED --- --- icu.c DELETED --- --- int_handler.S DELETED --- |
|
From: Jun S. <ju...@us...> - 2001-09-22 04:10:14
|
Update of /cvsroot/linux-mips/linux/arch/mips/vr4122/common In directory usw-pr-cvs1:/tmp/cvs-serv25447/vr4122/common Log Message: Directory /cvsroot/linux-mips/linux/arch/mips/vr4122/common added to the repository |
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From: Jun S. <ju...@us...> - 2001-09-22 04:10:14
|
Update of /cvsroot/linux-mips/linux/arch/mips/vr4181/osprey In directory usw-pr-cvs1:/tmp/cvs-serv25447/vr4181/osprey Log Message: Directory /cvsroot/linux-mips/linux/arch/mips/vr4181/osprey added to the repository |
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From: Jun S. <ju...@us...> - 2001-09-22 04:10:14
|
Update of /cvsroot/linux-mips/linux/arch/mips/vr4181/common In directory usw-pr-cvs1:/tmp/cvs-serv25447/vr4181/common Log Message: Directory /cvsroot/linux-mips/linux/arch/mips/vr4181/common added to the repository |
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From: Jun S. <ju...@us...> - 2001-09-22 04:10:14
|
Update of /cvsroot/linux-mips/linux/arch/mips/vr4122/eagle In directory usw-pr-cvs1:/tmp/cvs-serv25447/vr4122/eagle Log Message: Directory /cvsroot/linux-mips/linux/arch/mips/vr4122/eagle added to the repository |
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From: Jun S. <ju...@us...> - 2001-09-22 04:09:27
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Update of /cvsroot/linux-mips/linux/arch/mips/vr4122 In directory usw-pr-cvs1:/tmp/cvs-serv25301/vr4122 Log Message: Directory /cvsroot/linux-mips/linux/arch/mips/vr4122 added to the repository |
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From: Jun S. <ju...@us...> - 2001-09-22 04:09:27
|
Update of /cvsroot/linux-mips/linux/arch/mips/vr4181 In directory usw-pr-cvs1:/tmp/cvs-serv25301/vr4181 Log Message: Directory /cvsroot/linux-mips/linux/arch/mips/vr4181 added to the repository |
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From: Jun S. <ju...@us...> - 2001-09-22 04:07:45
|
Update of /cvsroot/linux-mips/linux/include/asm-mips/vr4181 In directory usw-pr-cvs1:/tmp/cvs-serv25116/vr4181 Log Message: Directory /cvsroot/linux-mips/linux/include/asm-mips/vr4181 added to the repository |
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From: Jun S. <ju...@us...> - 2001-09-22 04:07:44
|
Update of /cvsroot/linux-mips/linux/include/asm-mips/vr4122 In directory usw-pr-cvs1:/tmp/cvs-serv25116/vr4122 Log Message: Directory /cvsroot/linux-mips/linux/include/asm-mips/vr4122 added to the repository |
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