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From: James S. <jsi...@us...> - 2001-11-29 17:16:57
|
Update of /cvsroot/linux-mips/linux/arch/mips/mm
In directory usw-pr-cvs1:/tmp/cvs-serv19944
Modified Files:
tlb-sb1.c
Log Message:
Use mips_cpu.tlbsize like everywhere else.
Index: tlb-sb1.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/mm/tlb-sb1.c,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- tlb-sb1.c 2001/11/26 19:16:06 1.3
+++ tlb-sb1.c 2001/11/29 17:16:54 1.4
@@ -28,8 +28,6 @@
/* These are probed at ld_mmu time */
-static unsigned int tlb_entries;
-
/* Dump the current entry* and pagemask registers */
static inline void dump_cur_tlb_regs(void)
{
@@ -78,7 +76,7 @@
printk("\n\nFull TLB Dump:"
"Idx EntryHi EntryLo0 EntryLo1 PageMask\n"
"--------------------------------------------------------------\n");
- for (entry = 0; entry < tlb_entries; entry++) {
+ for (entry = 0; entry < mips_cpu.tlbsize; entry++) {
set_index(entry);
printk("\n%02i ", entry);
__asm__ __volatile__ (
@@ -102,7 +100,7 @@
old_ctx = (get_entryhi() & 0xff);
set_entrylo0(0);
set_entrylo1(0);
- for (entry = 0; entry < tlb_entries; entry++) {
+ for (entry = 0; entry < mips_cpu.tlbsize; entry++) {
set_entryhi(KSEG0 + (PAGE_SIZE << 1) * entry);
set_index(entry);
tlb_write_indexed();
@@ -123,11 +121,12 @@
{
int entry;
long addr = 0;
+
long inc = 1<<24; /* 16MB */
/* Save old context and create impossible VPN2 value */
set_entrylo0(0);
set_entrylo1(0);
- for (entry = 0; entry < tlb_entries; entry++) {
+ for (entry = 0; entry < mips_cpu.tlbsize; entry++) {
do {
addr += inc;
set_entryhi(addr);
@@ -138,7 +137,7 @@
}
/* Now that we know we're safe from collisions, we can safely flush
the TLB with the "normal" routine. */
- flush_tlb_all();
+ local_flush_tlb_all();
}
@@ -296,7 +295,7 @@
u32 config1;
config1 = read_mips32_cp0_config1();
- tlb_entries = ((config1 >> 25) & 0x3f) + 1;
+ mips_cpu.tlbsize = ((config1 >> 25) & 0x3f) + 1;
/*
* We don't know what state the firmware left the TLB's in, so this is
|
|
From: Steve L. <slo...@us...> - 2001-11-29 01:32:36
|
Update of /cvsroot/linux-mips/linux/arch/mips/au1000/pb1000
In directory usw-pr-cvs1:/tmp/cvs-serv31912
Modified Files:
setup.c
Log Message:
Au1000 OHCI workaround for DoneHead register corruption problem.
Index: setup.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/au1000/pb1000/setup.c,v
retrieving revision 1.14
retrieving revision 1.15
diff -u -d -r1.14 -r1.15
--- setup.c 2001/11/26 19:57:38 1.14
+++ setup.c 2001/11/29 01:32:31 1.15
@@ -46,6 +46,12 @@
#include <asm/au1000.h>
#include <asm/pb1000.h>
+#ifdef CONFIG_USB_OHCI
+// Enable the workaround for the OHCI DoneHead
+// register corruption problem.
+#define CONFIG_AU1000_OHCI_FIX
+#endif
+
#if defined(CONFIG_AU1000_SERIAL_CONSOLE)
extern void console_setup(char *, int *);
char serial_console[20];
@@ -79,7 +85,8 @@
void __init au1000_setup(void)
{
char *argptr;
- u32 pin_func, static_cfg0, usb_clocks=0;
+ u32 pin_func, static_cfg0;
+ u32 sys_freqctrl, sys_clksrc;
argptr = prom_getcmdline();
@@ -112,7 +119,7 @@
// set AUX clock to 12MHz * 8 = 96 MHz
outl(8, AUX_PLL_CNTRL);
outl(0, PIN_STATE);
- udelay(1000);
+ udelay(100);
#if defined (CONFIG_USB_OHCI) || defined (CONFIG_AU1000_USB_DEVICE)
#ifdef CONFIG_USB_OHCI
@@ -125,16 +132,57 @@
strcat(argptr, usb_args);
}
#endif
- // enable CLK2 and/or CLK1 for USB Host and/or Device clocks
- outl(0x00300000, FQ_CNTRL_1); // FREQ2 = aux/2 = 48 MHz
-#ifdef CONFIG_AU1000_USB_DEVICE
- usb_clocks |= 0x00000200; // CLK1 = FREQ2
-#endif
+
+ /* zero and disable FREQ2 */
+ sys_freqctrl = inl(FQ_CNTRL_1);
+ sys_freqctrl &= ~0xFFF00000;
+ outl(sys_freqctrl, FQ_CNTRL_1);
+
+ /* zero and disable USBH/USBD clocks */
+ sys_clksrc = inl(CLOCK_SOURCE_CNTRL);
+ sys_clksrc &= ~0x00007FE0;
+ outl(sys_clksrc, CLOCK_SOURCE_CNTRL);
+
+ sys_freqctrl = inl(FQ_CNTRL_1);
+ sys_freqctrl &= ~0xFFF00000;
+
+ sys_clksrc = inl(CLOCK_SOURCE_CNTRL);
+ sys_clksrc &= ~0x00007FE0;
+
+#ifdef CONFIG_AU1000_OHCI_FIX
+ /* CPU core freq to 48MHz to slow it way down... */
+ outl(4, CPU_PLL_CNTRL);
+
+ /*
+ * Setup 48MHz FREQ2 from CPUPLL for USB Host
+ */
+ /* FRDIV2=3 -> div by 8 of 384MHz -> 48MHz */
+ sys_freqctrl |= ((3<<22) | (1<<21) | (0<<20));
+ outl(sys_freqctrl, FQ_CNTRL_1);
+
+ /* CPU core freq to 384MHz */
+ outl(0x20, CPU_PLL_CNTRL);
+
+ printk("Au1000: 48MHz OHCI workaround enabled\n");
+
+#else // CONFIG_AU1000_OHCI_FIX
+
+ // FREQ2 = aux/2 = 48 MHz
+ sys_freqctrl |= ((0<<22) | (1<<21) | (1<<20));
+ outl(sys_freqctrl, FQ_CNTRL_1);
+
+#endif // CONFIG_AU1000_OHCI_FIX
+
+ /*
+ * Route 48MHz FREQ2 into USB Host and/or Device
+ */
#ifdef CONFIG_USB_OHCI
- usb_clocks |= 0x00004000; // CLK2 = FREQ2
+ sys_clksrc |= ((4<<12) | (0<<11) | (0<<10));
#endif
- outl(usb_clocks, CLOCK_SOURCE_CNTRL);
- udelay(1000);
+#ifdef CONFIG_AU1000_USB_DEVICE
+ sys_clksrc |= ((4<<7) | (0<<6) | (0<<5));
+#endif
+ outl(sys_clksrc, CLOCK_SOURCE_CNTRL);
#ifdef CONFIG_USB_OHCI
// enable host controller and wait for reset done
@@ -158,7 +206,7 @@
outl(0x0030, OUTPUT_STATE_CLEAR);
#endif // defined (CONFIG_USB_OHCI) || defined (CONFIG_AU1000_USB_DEVICE)
- // select gpio 15 (for interrupt line)
+ // make gpio 15 an input (for interrupt line)
pin_func = inl(PIN_FUNCTION) & (u32)(~0x100);
// we don't need I2S, so make it available for GPIO[31:29]
pin_func |= (1<<5);
@@ -177,7 +225,8 @@
outl(0x00000004, STATIC_CONFIG_2);
// STATIC_TIMING_2
- outl(0x08061908, STATIC_TIMING_2);
+ //outl(0x08061908, STATIC_TIMING_2);
+ outl(0x09000000, STATIC_TIMING_2);
// Set 32-bit base address decoding for RCE2*
outl(0x10003ff0, STATIC_ADDRESS_2);
|
|
From: Jun S. <ju...@us...> - 2001-11-28 23:15:06
|
Update of /cvsroot/linux-mips/linux/arch/mips/korva In directory usw-pr-cvs1:/tmp/cvs-serv24367/arch/mips/korva Modified Files: Makefile Log Message: Need to export the .o file as well. Index: Makefile =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips/korva/Makefile,v retrieving revision 1.3 retrieving revision 1.4 diff -u -d -r1.3 -r1.4 --- Makefile 2001/10/05 21:26:19 1.3 +++ Makefile 2001/11/28 23:11:21 1.4 @@ -18,5 +18,7 @@ obj-$(CONFIG_REMOTE_DEBUG) += dbg_io.o +export-objs := candy_setup.o + include $(TOPDIR)/Rules.make |
|
From: Pete P. <pp...@us...> - 2001-11-28 22:50:45
|
Update of /cvsroot/linux-mips/linux/drivers/mtd/maps
In directory usw-pr-cvs1:/tmp/cvs-serv18547/drivers/mtd/maps
Added Files:
Config.in Makefile pb1xxx-flash.c
Log Message:
* Added mtd partitioning support for the Alchemy Pb1000 board.
* Updated the defconfig file to include mtd and jffs2 support.
--- NEW FILE: Config.in ---
# drivers/mtd/maps/Config.in
# $Id: Config.in,v 1.1 2001/11/28 22:50:42 ppopov Exp $
mainmenu_option next_comment
comment 'Mapping drivers for chip access'
dep_tristate ' CFI Flash device in physical memory map' CONFIG_MTD_PHYSMAP $CONFIG_MTD_CFI
if [ "$CONFIG_MTD_PHYSMAP" = "y" -o "$CONFIG_MTD_PHYSMAP" = "m" ]; then
hex ' Physical start address of flash mapping' CONFIG_MTD_PHYSMAP_START 0x8000000
hex ' Physical length of flash mapping' CONFIG_MTD_PHYSMAP_LEN 0x4000000
int ' Bus width in octets' CONFIG_MTD_PHYSMAP_BUSWIDTH 2
fi
if [ "$CONFIG_SPARC" = "y" -o "$CONFIG_SPARC64" = "y" ]; then
dep_tristate ' Sun Microsystems userflash support' CONFIG_MTD_SUN_UFLASH $CONFIG_MTD_CFI
fi
if [ "$CONFIG_X86" = "y" ]; then
dep_tristate ' CFI Flash device mapped on Photron PNC-2000' CONFIG_MTD_PNC2000 $CONFIG_MTD_CFI $CONFIG_MTD_PARTITIONS
dep_tristate ' CFI Flash device mapped on AMD SC520 CDP' CONFIG_MTD_SC520CDP $CONFIG_MTD_CFI
dep_tristate ' CFI Flash device mapped on AMD NetSc520' CONFIG_MTD_NETSC520 $CONFIG_MTD_CFI $CONFIG_MTD_PARTITIONS
dep_tristate ' CFI Flash device mapped on Arcom SBC-GXx boards' CONFIG_MTD_SBC_GXX $CONFIG_MTD_CFI_INTELEXT $CONFIG_MTD_PARTITIONS
dep_tristate ' CFI Flash device mapped on Arcom ELAN-104NC' CONFIG_MTD_ELAN_104NC $CONFIG_MTD_CFI_INTELEXT $CONFIG_MTD_PARTITIONS
dep_tristate ' JEDEC Flash device mapped on Mixcom piggyback card' CONFIG_MTD_MIXMEM $CONFIG_MTD_JEDEC
dep_tristate ' JEDEC Flash device mapped on Octagon 5066 SBC' CONFIG_MTD_OCTAGON $CONFIG_MTD_JEDEC
dep_tristate ' JEDEC Flash device mapped on Tempustech VMAX SBC301' CONFIG_MTD_VMAX $CONFIG_MTD_JEDEC
dep_tristate ' BIOS flash chip on Intel L440GX boards' CONFIG_MTD_L440GX $CONFIG_I386 $CONFIG_MTD_JEDEC
fi
if [ "$CONFIG_PPC" = "y" ]; then
dep_tristate ' CFI Flash device mapped on TQM8XXL' CONFIG_MTD_TQM8XXL $CONFIG_MTD_CFI $CONFIG_TQM8xxL $CONFIG_PPC
dep_tristate ' CFI Flash device mapped on RPX Lite or CLLF' CONFIG_MTD_RPXLITE $CONFIG_MTD_CFI $CONFIG_PPC
dep_tristate ' CFI Flash device mapped on D-Box2' CONFIG_MTD_DBOX2 $CONFIG_MTD_CFI_INTELSTD $CONFIG_MTD_CFI_INTELEXT $CONFIG_MTD_CFI_AMDSTD
dep_tristate ' CFI Flash device mapping on FlagaDM' CONFIG_MTD_CFI_FLAGADM $CONFIG_MTD_CFI
fi
if [ "$CONFIG_MIPS" = "y" ]; then
dep_tristate ' Alchemy Pb1000 boot flash device' CONFIG_MTD_PB1000 $CONFIG_MIPS_PB1000
dep_tristate ' Flash chip mapping on ITE QED-4N-S01B, Globespan IVR or custom board' CONFIG_MTD_CSTM_MIPS_IXX $CONFIG_MTD_CFI $CONFIG_MTD_JEDEC $CONFIG_MTD_PARTITIONS
if [ "$CONFIG_MTD_CSTM_MIPS_IXX" = "y" -o "$CONFIG_MTD_CSTM_MIPS_IXX" = "m" ]; then
hex ' Physical start address of flash mapping' CONFIG_MTD_CSTM_MIPS_IXX_START 0x8000000
hex ' Physical length of flash mapping' CONFIG_MTD_CSTM_MIPS_IXX_LEN 0x4000000
int ' Bus width in octets' CONFIG_MTD_CSTM_MIPS_IXX_BUSWIDTH 2
fi
dep_tristate ' Momenco Ocelot boot flash device' CONFIG_MTD_OCELOT $CONFIG_MOMENCO_OCELOT
fi
if [ "$CONFIG_SH" = "y" ]; then
dep_tristate ' CFI Flash device mapped on Hitachi SolutionEngine' CONFIG_MTD_SOLUTIONENGINE $CONFIG_MTD_CFI $CONFIG_SH $CONFIG_MTD_REDBOOT_PARTS
fi
if [ "$CONFIG_ARM" = "y" ]; then
dep_tristate ' CFI Flash device mapped on Nora' CONFIG_MTD_NORA $CONFIG_MTD_CFI
dep_tristate ' CFI Flash device mapped on ARM Integrator/P720T' CONFIG_MTD_ARM_INTEGRATOR $CONFIG_MTD_CFI
dep_tristate ' Cirrus CDB89712 evaluation board mappings' CONFIG_MTD_CDB89712 $CONFIG_MTD_CFI $CONFIG_ARCH_CDB89712
dep_tristate ' CFI Flash device mapped on StrongARM SA11x0' CONFIG_MTD_SA1100 $CONFIG_MTD_CFI $CONFIG_ARCH_SA1100 $CONFIG_MTD_PARTITIONS
dep_tristate ' CFI Flash device mapped on DC21285 Footbridge' CONFIG_MTD_DC21285 $CONFIG_MTD_CFI $CONFIG_ARCH_FOOTBRIDGE $CONFIG_MTD_PARTITIONS
dep_tristate ' CFI Flash device mapped on the XScale IQ80310 board' CONFIG_MTD_IQ80310 $CONFIG_MTD_CFI $CONFIG_ARCH_IQ80310
fi
endmenu
--- NEW FILE: Makefile ---
#
# linux/drivers/maps/Makefile
#
# $Id: Makefile,v 1.1 2001/11/28 22:50:42 ppopov Exp $
O_TARGET := mapslink.o
# Chip mappings
obj-$(CONFIG_MTD_CDB89712) += cdb89712.o
obj-$(CONFIG_MTD_ARM_INTEGRATOR)+= integrator-flash.o
obj-$(CONFIG_MTD_CFI_FLAGADM) += cfi_flagadm.o
obj-$(CONFIG_MTD_CSTM_MIPS_IXX) += cstm_mips_ixx.o
obj-$(CONFIG_MTD_DC21285) += dc21285.o
obj-$(CONFIG_MTD_ELAN_104NC) += elan-104nc.o
obj-$(CONFIG_MTD_IQ80310) += iq80310.o
obj-$(CONFIG_MTD_L440GX) += l440gx.o
obj-$(CONFIG_MTD_NORA) += nora.o
obj-$(CONFIG_MTD_OCTAGON) += octagon-5066.o
obj-$(CONFIG_MTD_PHYSMAP) += physmap.o
obj-$(CONFIG_MTD_PNC2000) += pnc2000.o
obj-$(CONFIG_MTD_RPXLITE) += rpxlite.o
obj-$(CONFIG_MTD_TQM8XXL) += tqm8xxl.o
obj-$(CONFIG_MTD_SA1100) += sa1100-flash.o
obj-$(CONFIG_MTD_SBC_GXX) += sbc_gxx.o
obj-$(CONFIG_MTD_SC520CDP) += sc520cdp.o
obj-$(CONFIG_MTD_NETSC520) += netsc520.o
obj-$(CONFIG_MTD_SUN_UFLASH) += sun_uflash.o
obj-$(CONFIG_MTD_VMAX) += vmax301.o
obj-$(CONFIG_MTD_DBOX2) += dbox2-flash.o
obj-$(CONFIG_MTD_OCELOT) += ocelot.o
obj-$(CONFIG_MTD_SOLUTIONENGINE)+= solutionengine.o
obj-$(CONFIG_MTD_PB1000) += pb1xxx-flash.o
include $(TOPDIR)/Rules.make
--- NEW FILE: pb1xxx-flash.c ---
/*
* Flash memory access on Alchemy Pb1xxx boards
*
* (C) 2001 Pete Popov <pp...@mv...>
*
*/
#include <linux/config.h>
#include <linux/module.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/map.h>
#include <linux/mtd/partitions.h>
#include <asm/io.h>
#define WINDOW_ADDR 0x1F800000
#define WINDOW_SIZE 0x800000
__u8 physmap_read8(struct map_info *map, unsigned long ofs)
{
return __raw_readb(map->map_priv_1 + ofs);
}
__u16 physmap_read16(struct map_info *map, unsigned long ofs)
{
return __raw_readw(map->map_priv_1 + ofs);
}
__u32 physmap_read32(struct map_info *map, unsigned long ofs)
{
return __raw_readl(map->map_priv_1 + ofs);
}
void physmap_copy_from(struct map_info *map, void *to, unsigned long from, ssize_t len)
{
memcpy_fromio(to, map->map_priv_1 + from, len);
}
void physmap_write8(struct map_info *map, __u8 d, unsigned long adr)
{
__raw_writeb(d, map->map_priv_1 + adr);
mb();
}
void physmap_write16(struct map_info *map, __u16 d, unsigned long adr)
{
__raw_writew(d, map->map_priv_1 + adr);
mb();
}
void physmap_write32(struct map_info *map, __u32 d, unsigned long adr)
{
__raw_writel(d, map->map_priv_1 + adr);
mb();
}
void physmap_copy_to(struct map_info *map, unsigned long to, const void *from, ssize_t len)
{
memcpy_toio(map->map_priv_1 + to, from, len);
}
static struct map_info pb1xxx_map = {
name: "Pb1xxx flash",
size: 0x800000,
buswidth: 4,
read8: physmap_read8,
read16: physmap_read16,
read32: physmap_read32,
copy_from: physmap_copy_from,
write8: physmap_write8,
write16: physmap_write16,
write32: physmap_write32,
copy_to: physmap_copy_to,
};
#ifdef CONFIG_MIPS_PB1000
static unsigned long pb1000_max_flash_size = 0x00800000;
static struct mtd_partition pb1000_partitions[] = {
{
name: "yamon env",
size: 0x00020000,
offset: 0,
mask_flags: MTD_WRITEABLE
},{
name: "jffs/2",
size: 0x003e0000,
offset: 0x20000,
},{
name: "boot code",
size: 0x100000,
offset: 0x400000,
mask_flags: MTD_WRITEABLE
},{
name: "raw/kernel",
size: 0x300000,
offset: 0x500000
}
};
#else
#error Unsupported board
#endif
#define NB_OF(x) (sizeof(x)/sizeof(x[0]))
static struct mtd_partition *parsed_parts;
static struct mtd_info *mymtd;
int __init pb1xxx_mtd_init(void)
{
struct mtd_partition *parts;
int nb_parts = 0;
int parsed_nr_parts = 0;
char *part_type;
/* Default flash buswidth */
pb1xxx_map.buswidth = 4;
/*
* Static partition definition selection
*/
part_type = "static";
#ifdef CONFIG_MIPS_PB1000
parts = pb1000_partitions;
nb_parts = NB_OF(pb1000_partitions);
#endif
pb1xxx_map.size = 4;
/*
* Now let's probe for the actual flash. Do it here since
* specific machine settings might have been set above.
*/
printk(KERN_NOTICE "Pb1xxx flash: probing %d-bit flash bus\n",
pb1xxx_map.buswidth*8);
pb1xxx_map.map_priv_1 =
(unsigned long)ioremap(WINDOW_ADDR, WINDOW_SIZE);
mymtd = do_map_probe("cfi_probe", &pb1xxx_map);
if (!mymtd)
return -ENXIO;
mymtd->module = THIS_MODULE;
add_mtd_partitions(mymtd, parts, nb_parts);
return 0;
}
static void __exit pb1xxx_mtd_cleanup(void)
{
if (mymtd) {
del_mtd_partitions(mymtd);
map_destroy(mymtd);
if (parsed_parts)
kfree(parsed_parts);
}
}
module_init(pb1xxx_mtd_init);
module_exit(pb1xxx_mtd_cleanup);
MODULE_AUTHOR("Pete Popov");
MODULE_DESCRIPTION("Pb1xxx CFI map driver");
MODULE_LICENSE("GPL");
|
|
From: Pete P. <pp...@us...> - 2001-11-28 22:50:45
|
Update of /cvsroot/linux-mips/linux/arch/mips/configs In directory usw-pr-cvs1:/tmp/cvs-serv18547/arch/mips/configs Modified Files: defconfig-pb1000 Log Message: * Added mtd partitioning support for the Alchemy Pb1000 board. * Updated the defconfig file to include mtd and jffs2 support. Index: defconfig-pb1000 =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips/configs/defconfig-pb1000,v retrieving revision 1.15 retrieving revision 1.16 diff -u -d -r1.15 -r1.16 --- defconfig-pb1000 2001/11/27 23:31:02 1.15 +++ defconfig-pb1000 2001/11/28 22:50:42 1.16 @@ -109,9 +109,66 @@ # # Memory Technology Devices (MTD) # -# CONFIG_MTD is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_GEN_PROBE=y +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +# CONFIG_MTD_CFI_INTELEXT is not set +CONFIG_MTD_CFI_AMDSTD=y +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set +# CONFIG_MTD_OBSOLETE_CHIPS is not set +# CONFIG_MTD_AMDSTD is not set +# CONFIG_MTD_SHARP is not set +# CONFIG_MTD_JEDEC is not set # +# Mapping drivers for chip access +# +# CONFIG_MTD_PHYSMAP is not set +CONFIG_MTD_PB1000=y +# CONFIG_MTD_CSTM_MIPS_IXX is not set +# CONFIG_MTD_OCELOT is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_PMC551 is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLKMTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC1000 is not set +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOCPROBE is not set + +# +# NAND Flash Device Drivers +# +# CONFIG_MTD_NAND is not set + +# # Parallel port support # # CONFIG_PARPORT is not set @@ -380,7 +437,7 @@ # CONFIG_AGP is not set # CONFIG_DRM is not set CONFIG_AU1000_GPIO=y -CONFIG_TS_AU1000_ADS7846=y +# CONFIG_TS_AU1000_ADS7846 is not set # # Multimedia devices @@ -406,11 +463,12 @@ # CONFIG_VFAT_FS is not set # CONFIG_EFS_FS is not set # CONFIG_JFFS_FS is not set -# CONFIG_JFFS2_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 # CONFIG_CRAMFS is not set # CONFIG_TMPFS is not set # CONFIG_RAMFS is not set -CONFIG_ISO9660_FS=y +# CONFIG_ISO9660_FS is not set # CONFIG_JOLIET is not set # CONFIG_ZISOFS is not set # CONFIG_MINIX_FS is not set @@ -422,7 +480,7 @@ # CONFIG_DEVFS_FS is not set # CONFIG_DEVFS_MOUNT is not set # CONFIG_DEVFS_DEBUG is not set -# CONFIG_DEVPTS_FS is not set +CONFIG_DEVPTS_FS=y # CONFIG_QNX4FS_FS is not set # CONFIG_QNX4FS_RW is not set # CONFIG_ROMFS_FS is not set @@ -460,21 +518,8 @@ # # Partition Types # -CONFIG_PARTITION_ADVANCED=y -# CONFIG_ACORN_PARTITION is not set -# CONFIG_OSF_PARTITION is not set -# CONFIG_AMIGA_PARTITION is not set -# CONFIG_ATARI_PARTITION is not set -# CONFIG_MAC_PARTITION is not set +# CONFIG_PARTITION_ADVANCED is not set CONFIG_MSDOS_PARTITION=y -# CONFIG_BSD_DISKLABEL is not set -# CONFIG_MINIX_SUBPARTITION is not set -# CONFIG_SOLARIS_X86_PARTITION is not set -# CONFIG_UNIXWARE_DISKLABEL is not set -# CONFIG_LDM_PARTITION is not set -CONFIG_SGI_PARTITION=y -# CONFIG_ULTRIX_PARTITION is not set -# CONFIG_SUN_PARTITION is not set # CONFIG_SMB_NLS is not set # CONFIG_NLS is not set |
|
From: Pete P. <pp...@us...> - 2001-11-28 22:48:38
|
Update of /cvsroot/linux-mips/linux/drivers/mtd/maps In directory usw-pr-cvs1:/tmp/cvs-serv18062/drivers/mtd/maps Log Message: Directory /cvsroot/linux-mips/linux/drivers/mtd/maps added to the repository |
|
From: Jun S. <ju...@us...> - 2001-11-28 22:48:08
|
Update of /cvsroot/linux-mips/linux/drivers/net
In directory usw-pr-cvs1:/tmp/cvs-serv17622/drivers/net
Modified Files:
nec_candy.c
Log Message:
Fix typo and warnings. Thanks to Geoffrey Espin.
Index: nec_candy.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/drivers/net/nec_candy.c,v
retrieving revision 1.4
retrieving revision 1.5
diff -u -d -r1.4 -r1.5
--- nec_candy.c 2001/11/08 01:46:43 1.4
+++ nec_candy.c 2001/11/28 22:48:05 1.5
@@ -2108,8 +2108,8 @@
dma_cache_inv((ulong)pp->rx_ring,
sizeof(struct candy_desc)*(RX_RING_SIZE+1));
- pp->tx_ring = KSEG1ADDR(pp->tx_ring);
- pp->rx_ring = KSEG1ADDR(pp->rx_ring);
+ pp->tx_ring = (void*) KSEG1ADDR(pp->tx_ring);
+ pp->rx_ring = (void*) KSEG1ADDR(pp->rx_ring);
/* allocate rx skbs */
for (i=0; i< RX_RING_SIZE; i++) {
@@ -2242,8 +2242,8 @@
pp = candy_priv_head;
candy_priv_head = pp->next;
- kfree(KSEG0ADDR(pp->rx_ring));
- kfree(KSEG0ADDR(pp->tx_ring));
+ kfree((void*)KSEG0ADDR(pp->rx_ring));
+ kfree((void*)KSEG0ADDR(pp->tx_ring));
for (i=0; i< RX_RING_SIZE; i++) dev_kfree_skb(pp->rx_skb[i]);
|
|
From: Jun S. <ju...@us...> - 2001-11-28 22:48:08
|
Update of /cvsroot/linux-mips/linux/arch/mips/korva In directory usw-pr-cvs1:/tmp/cvs-serv17622/arch/mips/korva Modified Files: candy_setup.c Log Message: Fix typo and warnings. Thanks to Geoffrey Espin. Index: candy_setup.c =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips/korva/candy_setup.c,v retrieving revision 1.1 retrieving revision 1.2 diff -u -d -r1.1 -r1.2 --- candy_setup.c 2001/09/17 17:02:29 1.1 +++ candy_setup.c 2001/11/28 22:48:05 1.2 @@ -48,7 +48,7 @@ return 0; } -EXPORT_SYMBLE(nec_candy_get_boot_params); +EXPORT_SYMBOL(nec_candy_get_boot_params); /* |
|
From: Pete P. <pp...@us...> - 2001-11-28 19:01:20
|
Update of /cvsroot/linux-mips/linux/include/asm-mips
In directory usw-pr-cvs1:/tmp/cvs-serv7405/include/asm-mips
Modified Files:
bootinfo.h
Log Message:
Changed PB1000 to Pb1000.
Index: bootinfo.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/bootinfo.h,v
retrieving revision 1.15
retrieving revision 1.16
diff -u -d -r1.15 -r1.16
--- bootinfo.h 2001/11/27 22:51:19 1.15
+++ bootinfo.h 2001/11/28 19:01:18 1.16
@@ -197,7 +197,7 @@
*/
#define MACH_PB1000 0 /* Au1000-based eval board */
-#define GROUP_ALCHEMY_NAMES { "PB1000" } /* the actual board name */
+#define GROUP_ALCHEMY_NAMES { "Pb1000" } /* the actual board name */
/*
* Valid machtype for group NEC_VR41XX
|
|
From: Jun S. <ju...@us...> - 2001-11-28 19:00:14
|
Update of /cvsroot/linux-mips/linux/arch/mips/configs In directory usw-pr-cvs1:/tmp/cvs-serv7023/arch/mips/configs Modified Files: defconfig-ddb5476 defconfig-ddb5477 defconfig-osprey Log Message: Update defconfigs to use MIPS RTC. Index: defconfig-ddb5476 =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips/configs/defconfig-ddb5476,v retrieving revision 1.15 retrieving revision 1.16 diff -u -d -r1.15 -r1.16 --- defconfig-ddb5476 2001/11/27 23:31:02 1.15 +++ defconfig-ddb5476 2001/11/28 19:00:10 1.16 @@ -28,6 +28,7 @@ # CONFIG_PS2 is not set # CONFIG_CASIO_BE300 is not set # CONFIG_VADEM_CLIO_1000 is not set +# CONFIG_NEC_MOBILEPRO_780 is not set # CONFIG_MIPS_MAGNUM_4000 is not set # CONFIG_MOMENCO_OCELOT is not set CONFIG_DDB5476=y @@ -459,6 +460,7 @@ # CONFIG_INTEL_RNG is not set # CONFIG_NVRAM is not set # CONFIG_RTC is not set +CONFIG_MIPS_RTC=y # CONFIG_DTLK is not set # CONFIG_R3964 is not set # CONFIG_APPLICOM is not set Index: defconfig-ddb5477 =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips/configs/defconfig-ddb5477,v retrieving revision 1.14 retrieving revision 1.15 diff -u -d -r1.14 -r1.15 --- defconfig-ddb5477 2001/11/27 23:31:02 1.14 +++ defconfig-ddb5477 2001/11/28 19:00:10 1.15 @@ -28,6 +28,7 @@ # CONFIG_PS2 is not set # CONFIG_CASIO_BE300 is not set # CONFIG_VADEM_CLIO_1000 is not set +# CONFIG_NEC_MOBILEPRO_780 is not set # CONFIG_MIPS_MAGNUM_4000 is not set # CONFIG_MOMENCO_OCELOT is not set # CONFIG_DDB5476 is not set @@ -373,6 +374,7 @@ # CONFIG_INTEL_RNG is not set # CONFIG_NVRAM is not set # CONFIG_RTC is not set +CONFIG_MIPS_RTC=y # CONFIG_DTLK is not set # CONFIG_R3964 is not set # CONFIG_APPLICOM is not set Index: defconfig-osprey =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips/configs/defconfig-osprey,v retrieving revision 1.11 retrieving revision 1.12 diff -u -d -r1.11 -r1.12 --- defconfig-osprey 2001/11/27 23:31:02 1.11 +++ defconfig-osprey 2001/11/28 19:00:10 1.12 @@ -28,6 +28,7 @@ # CONFIG_PS2 is not set # CONFIG_CASIO_BE300 is not set # CONFIG_VADEM_CLIO_1000 is not set +# CONFIG_NEC_MOBILEPRO_780 is not set # CONFIG_MIPS_MAGNUM_4000 is not set # CONFIG_MOMENCO_OCELOT is not set # CONFIG_DDB5476 is not set @@ -347,6 +348,7 @@ # CONFIG_INTEL_RNG is not set # CONFIG_NVRAM is not set # CONFIG_RTC is not set +CONFIG_MIPS_RTC=y # CONFIG_DTLK is not set # CONFIG_R3964 is not set # CONFIG_APPLICOM is not set |
|
From: Jun S. <ju...@us...> - 2001-11-28 18:55:43
|
Update of /cvsroot/linux-mips/linux/arch/mips/ite-boards/generic In directory usw-pr-cvs1:/tmp/cvs-serv4820/arch/mips/ite-boards/generic Modified Files: time.c Log Message: Switch DDB5476 to use GP timer instead of CPU counter. Misc updates. Index: time.c =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips/ite-boards/generic/time.c,v retrieving revision 1.5 retrieving revision 1.6 diff -u -d -r1.5 -r1.6 --- time.c 2001/11/22 01:19:24 1.5 +++ time.c 2001/11/28 18:55:40 1.6 @@ -141,9 +141,6 @@ r4k_cur = (read_32bit_cp0_register(CP0_COUNT) + r4k_offset); write_32bit_cp0_register(CP0_COMPARE, r4k_cur); set_cp0_status(ALLINTS); - - /* this is the last board dependent code */ - db_run(board_init_done_flag = 1); } void local_timer_interrupt(struct pt_regs *regs) |
|
From: Jun S. <ju...@us...> - 2001-11-28 18:55:43
|
Update of /cvsroot/linux-mips/linux/arch/mips/ddb5xxx/ddb5477
In directory usw-pr-cvs1:/tmp/cvs-serv4820/arch/mips/ddb5xxx/ddb5477
Modified Files:
setup.c
Log Message:
Switch DDB5476 to use GP timer instead of CPU counter. Misc updates.
Index: setup.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/ddb5xxx/ddb5477/setup.c,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- setup.c 2001/11/26 19:57:39 1.3
+++ setup.c 2001/11/28 18:55:40 1.4
@@ -36,7 +36,7 @@
-#define USE_CPU_COUNTER_TIMER /* whether we use cpu counter */
+// #define USE_CPU_COUNTER_TIMER /* whether we use cpu counter */
#ifdef USE_CPU_COUNTER_TIMER
#define CPU_COUNTER_FREQUENCY 83000000
@@ -88,10 +88,6 @@
rtc_ds1386_init(KSEG1ADDR(DDB_LCS1_BASE));
}
-#if defined(CONFIG_DEBUG)
-int board_init_done_flag = 0;
-#endif
-
extern int setup_irq(unsigned int irq, struct irqaction *irqaction);
static void __init ddb_timer_setup(struct irqaction *irq)
{
@@ -113,9 +109,6 @@
setup_irq(SP_TIMER_IRQ, irq);
#endif
-
- /* this is the last board dependent code */
- db_run(board_init_done_flag = 1);
}
static void ddb5477_board_init(void);
|
|
From: Jun S. <ju...@us...> - 2001-11-28 18:55:43
|
Update of /cvsroot/linux-mips/linux/arch/mips/ddb5xxx/ddb5476
In directory usw-pr-cvs1:/tmp/cvs-serv4820/arch/mips/ddb5xxx/ddb5476
Modified Files:
setup.c
Log Message:
Switch DDB5476 to use GP timer instead of CPU counter. Misc updates.
Index: setup.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/ddb5xxx/ddb5476/setup.c,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- setup.c 2001/11/26 19:57:38 1.3
+++ setup.c 2001/11/28 18:55:40 1.4
@@ -28,13 +28,20 @@
#include <asm/ddb5xxx/ddb5xxx.h>
-#ifdef CONFIG_REMOTE_DEBUG
-extern void rs_kgdb_hook(int);
-extern void breakpoint(void);
+// #define USE_CPU_COUNTER_TIMER /* whether we use cpu counter */
+
+#ifdef USE_CPU_COUNTER_TIMER
+
+#define CPU_COUNTER_FREQUENCY 83000000
+#else
+/* otherwise we use general purpose timer */
+#define TIMER_FREQUENCY 83000000
+#define TIMER_BASE DDB_T2CTRL
+#define TIMER_IRQ (VRC5476_IRQ_BASE + VRC5476_IRQ_GPT)
#endif
-#if defined(CONFIG_SERIAL_CONSOLE)
-extern void console_setup(char *);
+#ifdef CONFIG_REMOTE_DEBUG
+extern void breakpoint(void);
#endif
extern struct ide_ops std_ide_ops;
@@ -75,22 +82,20 @@
static void __init ddb_time_init(void)
{
- mips_counter_frequency = 83000000;
+#if defined(USE_CPU_COUNTER_TIMER)
+ mips_counter_frequency = CPU_COUNTER_FREQUENCY;
+#endif
/* we have ds1396 RTC chip */
rtc_ds1386_init(KSEG1ADDR(DDB_PCI_MEM_BASE));
-
- /* optional: we don't have a good way to set RTC time,
- * so we will hack here to set a time. In normal running.
- * it should *not* be called becaues RTC will keep the correct time.
- */
- /* rtc_set_time(mktime(2001, 10, 05, 17, 20, 0)); */
}
extern int setup_irq(unsigned int irq, struct irqaction *irqaction);
static void __init ddb_timer_setup(struct irqaction *irq)
{
+#if defined(USE_CPU_COUNTER_TIMER)
+
unsigned int count;
/* we are using the cpu counter for timer interrupts */
@@ -99,6 +104,13 @@
/* to generate the first timer interrupt */
count = read_32bit_cp0_register(CP0_COUNT);
write_32bit_cp0_register(CP0_COMPARE, count + 1000);
+
+#else
+
+ ddb_out32(TIMER_BASE, TIMER_FREQUENCY/HZ);
+ ddb_out32(TIMER_BASE+4, 0x1); /* enable timer */
+ setup_irq(TIMER_IRQ, irq);
+#endif
}
static struct {
|
|
From: James S. <jsi...@us...> - 2001-11-28 17:28:33
|
Update of /cvsroot/linux-mips/linux/arch/mips/mm
In directory usw-pr-cvs1:/tmp/cvs-serv11003
Modified Files:
c-r3k.c c-r4k.c c-tx39.c
Log Message:
more non-coherent IO fixes.
Index: c-r3k.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/mm/c-r3k.c,v
retrieving revision 1.4
retrieving revision 1.5
diff -u -d -r1.4 -r1.5
--- c-r3k.c 2001/11/27 17:53:47 1.4
+++ c-r3k.c 2001/11/28 17:28:31 1.5
@@ -331,7 +331,9 @@
_flush_icache_page = r3k_flush_icache_page;
_flush_icache_range = r3k_flush_icache_range;
+#ifdef CONFIG_NONCOHERENT_IO
_dma_cache_wback_inv = r3k_dma_cache_wback_inv;
+#endif /* CONFIG_NONCOHERENT_IO */
printk("Primary instruction cache %dkb, linesize %d bytes\n",
(int) (icache_size >> 10), (int) icache_lsize);
Index: c-r4k.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/mm/c-r4k.c,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -d -r1.2 -r1.3
--- c-r4k.c 2001/11/27 17:53:47 1.2
+++ c-r4k.c 2001/11/28 17:28:31 1.3
@@ -1141,6 +1141,7 @@
flush_cache_all();
}
+#ifdef CONFIG_NONCOHERENT_IO
/*
* Writeback and invalidate the primary cache dcache before DMA.
*
@@ -1247,6 +1248,8 @@
panic("r4k_dma_cache called - should not happen.\n");
}
+#endif /* CONFIG_NONCOHERENT_IO */
+
/*
* While we're protected against bad userland addresses we don't care
* very much about what happens in that case. Usually a segmentation
@@ -1435,10 +1438,11 @@
___flush_cache_all = _flush_cache_all;
_flush_icache_page = r4k_flush_icache_page_p;
-
+#ifdef CONFIG_NONCOHERENT_IO
_dma_cache_wback_inv = r4k_dma_cache_wback_inv_pc;
_dma_cache_wback = r4k_dma_cache_wback;
_dma_cache_inv = r4k_dma_cache_inv_pc;
+#endif
}
static void __init setup_scache_funcs(void)
@@ -1519,9 +1523,11 @@
}
___flush_cache_all = _flush_cache_all;
_flush_icache_page = r4k_flush_icache_page_s;
+#ifdef CONFIG_NONCOHERENT_IO
_dma_cache_wback_inv = r4k_dma_cache_wback_inv_sc;
_dma_cache_wback = r4k_dma_cache_wback;
_dma_cache_inv = r4k_dma_cache_inv_sc;
+#endif /* CONFIG_NONCOHERENT_IO */
}
typedef int (*probe_func_t)(unsigned long);
Index: c-tx39.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/mm/c-tx39.c,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- c-tx39.c 2001/11/27 17:53:47 1.3
+++ c-tx39.c 2001/11/28 17:28:31 1.4
@@ -294,8 +294,9 @@
_flush_page_to_ram = tx39h_flush_page_to_ram;
_flush_icache_page = (void *) tx39h_flush_icache_all;
_flush_icache_range = (void *) tx39h_flush_icache_all;
-
+#ifdef CONFIG_NONCOHERENT_IO
_dma_cache_wback_inv = tx39h_dma_cache_wback_inv;
+#endif /* CONFIG_NONCOHERENT_IO */
break;
case CPU_TX3922:
@@ -315,11 +316,11 @@
_flush_page_to_ram = tx39_flush_page_to_ram;
_flush_icache_page = tx39_flush_icache_page;
_flush_icache_range = tx39_flush_icache_range;
-
+#ifdef CONFIG_NONCOHERENT_IO
_dma_cache_wback_inv = tx39_dma_cache_wback_inv;
_dma_cache_wback = tx39_dma_cache_wback;
_dma_cache_inv = tx39_dma_cache_inv;
-
+#endif /* CONFIG_NONCOHERENT_IO */
break;
}
|
|
From: James S. <jsi...@us...> - 2001-11-28 17:19:22
|
Update of /cvsroot/linux-mips/linux/arch/mips/kernel In directory usw-pr-cvs1:/tmp/cvs-serv8480 Modified Files: smp.c Log Message: Yes, we always have at least one CPU :-) Index: smp.c =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips/kernel/smp.c,v retrieving revision 1.7 retrieving revision 1.8 diff -u -d -r1.7 -r1.8 --- smp.c 2001/11/20 18:18:27 1.7 +++ smp.c 2001/11/28 17:19:18 1.8 @@ -41,7 +41,7 @@ /* Ze Big Kernel Lock! */ spinlock_t kernel_flag = SPIN_LOCK_UNLOCKED; int smp_threads_ready; -int smp_num_cpus; /* Number that came online. */ +int smp_num_cpus = 1; /* Number that came online. */ cpumask_t cpu_online_map; /* Bitmask of currently online CPUs */ int global_irq_holder = NO_PROC_ID; spinlock_t global_irq_lock = SPIN_LOCK_UNLOCKED; |
|
From: James S. <jsi...@us...> - 2001-11-28 17:18:26
|
Update of /cvsroot/linux-mips/linux/arch/mips64/kernel In directory usw-pr-cvs1:/tmp/cvs-serv8182/mips64/kernel Modified Files: setup.c Log Message: Unswap accidently swapped code lines. Index: setup.c =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips64/kernel/setup.c,v retrieving revision 1.7 retrieving revision 1.8 diff -u -d -r1.7 -r1.8 --- setup.c 2001/11/26 17:17:26 1.7 +++ setup.c 2001/11/28 17:18:23 1.8 @@ -397,8 +397,8 @@ mips_cpu.options |= MIPS_CPU_MIPS16; if (config1 & 1) mips_cpu.options |= MIPS_CPU_FPU; - break; mips_cpu.scache.flags = MIPS_CACHE_NOT_PRESENT; + break; default: mips_cpu.cputype = CPU_UNKNOWN; break; |
|
From: James S. <jsi...@us...> - 2001-11-28 17:18:26
|
Update of /cvsroot/linux-mips/linux/arch/mips/kernel In directory usw-pr-cvs1:/tmp/cvs-serv8182/mips/kernel Modified Files: setup.c Log Message: Unswap accidently swapped code lines. Index: setup.c =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips/kernel/setup.c,v retrieving revision 1.35 retrieving revision 1.36 diff -u -d -r1.35 -r1.36 --- setup.c 2001/11/27 22:51:18 1.35 +++ setup.c 2001/11/28 17:18:23 1.36 @@ -479,8 +479,8 @@ mips_cpu.options |= MIPS_CPU_MIPS16; if (config1 & 1) mips_cpu.options |= MIPS_CPU_FPU; - break; mips_cpu.scache.flags = MIPS_CACHE_NOT_PRESENT; + break; default: mips_cpu.cputype = CPU_UNKNOWN; break; |
|
From: James S. <jsi...@us...> - 2001-11-28 17:15:48
|
Update of /cvsroot/linux-mips/linux/include/asm-mips64 In directory usw-pr-cvs1:/tmp/cvs-serv7512 Modified Files: io.h Log Message: O2 bits. Index: io.h =================================================================== RCS file: /cvsroot/linux-mips/linux/include/asm-mips64/io.h,v retrieving revision 1.9 retrieving revision 1.10 diff -u -d -r1.9 -r1.10 --- io.h 2001/11/27 23:52:10 1.9 +++ io.h 2001/11/28 17:15:45 1.10 @@ -22,6 +22,10 @@ #include <asm/sn/io.h> #endif +#ifdef CONFIG_SGI_IP32 +#include <asm/ip32/io.h> +#endif + extern unsigned long bus_to_baddr[256]; /* |
|
From: James S. <jsi...@us...> - 2001-11-28 17:15:05
|
Update of /cvsroot/linux-mips/linux/drivers/net
In directory usw-pr-cvs1:/tmp/cvs-serv7307
Added Files:
meth.c meth.h
Log Message:
Rest of METH driver.
--- NEW FILE: meth.c ---
/*
* meth.c -- O2 Builtin 10/100 Ethernet driver, that doesn't work at the moment
*
* Copyright (C) 2001 Ilya Volynets
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*/
#ifndef __KERNEL__
# define __KERNEL__
#endif
#ifndef MFE_DEBUG
#define MFE_DEBUG 0
#endif
#if MFE_DEBUG>=1
#define DPRINTK(str,args...) printk (KERN_DEBUG "meth: %s: " str, __FUNCTION__ , ## args)
#define MFE_RX_DEBUG 2
#else
#define DPRINTK(str,args...)
#define MFE_RX_DEBUG 0
#endif
#include <linux/config.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/sched.h>
#include <linux/kernel.h> /* printk() */
#include <linux/delay.h>
#include <linux/malloc.h> /* kmalloc() */
#include <linux/errno.h> /* error codes */
#include <linux/types.h> /* size_t */
#include <linux/interrupt.h> /* mark_bh */
#include <linux/pci.h>
#include <linux/in.h>
#include <linux/netdevice.h> /* struct device, and other headers */
#include <linux/etherdevice.h> /* eth_type_trans */
#include <linux/ip.h> /* struct iphdr */
#include <linux/tcp.h> /* struct tcphdr */
#include <linux/skbuff.h>
#include <linux/mii.h> /*MII definitions */
#include <asm/ip32/crime.h>
#include <asm/ip32/mace.h>
#include <asm/ip32/ip32_ints.h>
#include "meth.h"
#include <linux/in6.h>
#include <asm/checksum.h>
static const char *version="meth.c: Ilya Volynets (il...@th...)";
static const char *meth_str="SGI O2 Fast Ethernet";
MODULE_AUTHOR("Ilya Volynets");
MODULE_DESCRIPTION("SGI O2 Builtin Fast Ethernet driver");
/* This is a load-time options */
/*static int eth = 0;
MODULE_PARM(eth, "i");*/
/*
#ifdef HAVE_TX_TIMEOUT
static int timeout = 0;
MODULE_PARM(timeout, "i");
#endif
*/
int meth_eth;
/*
* This structure is private to each device. It is used to pass
* packets in and out, so there is place for a packet
*/
typedef struct meth_private {
struct net_device_stats stats;
volatile struct meth_regs *regs;
u64 mode; /* in-memory copy of MAC control register */
int phy_addr; /* address of phy, used by mdio_* functions, initialized in mdio_probe*/
tx_packet *tx_ring;
dma_addr_t tx_ring_dma;
int free_space;
struct sk_buff *tx_skbs[TX_RING_ENTRIES];
dma_addr_t tx_skb_dmas[TX_RING_ENTRIES];
int tx_read,tx_write;
rx_packet *rx_ring[RX_RING_ENTRIES];
dma_addr_t rx_ring_dmas[RX_RING_ENTRIES];
int rx_write;
spinlock_t meth_lock;
} meth_private;
extern struct net_device meth_devs[];
void meth_tx_timeout (struct net_device *dev);
void meth_interrupt(int irq, void *dev_id, struct pt_regs *pregs);
/* global, initialized in ip32-setup.c */
char o2meth_eaddr[8]={0,0,0,0,0,0,0,0};
static inline void load_eaddr(struct net_device *dev,
volatile struct meth_regs *regs)
{
int i;
DPRINTK("Loading MAC Address: %02x:%02x:%02x:%02x:%02x:%02x\n",
(int)o2meth_eaddr[0]&0xFF,(int)o2meth_eaddr[1]&0xFF,(int)o2meth_eaddr[2]&0xFF,
(int)o2meth_eaddr[3]&0xFF,(int)o2meth_eaddr[4]&0xFF,(int)o2meth_eaddr[5]&0xFF);
//memcpy(dev->dev_addr,o2meth_eaddr+2,6);
for (i=0; i<6; i++)
dev->dev_addr[i]=o2meth_eaddr[i];
regs->mac_addr= //dev->dev_addr[0]|(dev->dev_addr[1]<<8)|
//dev->dev_addr[2]<<16|(dev->dev_addr[3]<<24)|
//dev->dev_addr[4]<<32|(dev->dev_addr[5]<<40);
(*(u64*)o2meth_eaddr)>>16;
DPRINTK("MAC, finally is %0lx\n",regs->mac_addr);
}
/*
*Waits for BUSY status of mdio bus to clear
*/
#define WAIT_FOR_PHY(___regs, ___rval) \
while((___rval=___regs->phy_data)&MDIO_BUSY){ \
udelay(25); \
}
/*read phy register, return value read */
static int mdio_read(meth_private *priv,int phyreg)
{
volatile meth_regs* regs=priv->regs;
volatile u32 rval;
WAIT_FOR_PHY(regs,rval)
regs->phy_registers=(priv->phy_addr<<5)|(phyreg&0x1f);
udelay(25);
regs->phy_trans_go=1;
udelay(25);
WAIT_FOR_PHY(regs,rval)
return rval&MDIO_DATA_MASK;
}
/*write phy register */
static void mdio_write(meth_private* priv,int pfyreg,int val)
{
volatile meth_regs* regs=priv->regs;
int rval;
/// DPRINTK("Trying to write value %i to reguster %i\n",val, pfyreg);
/// spin_lock_irq(&priv->meth_lock);
WAIT_FOR_PHY(regs,rval)
regs->phy_registers=(priv->phy_addr<<5)|(pfyreg&0x1f);
regs->phy_data=val;
udelay(25);
WAIT_FOR_PHY(regs,rval)
/// spin_unlock_irq(&priv->meth_lock);
}
/* Modify phy register using given mask and value */
static void mdio_update(meth_private* priv,int phyreg, int val, int mask)
{
int rval;
DPRINTK("RMW value %i to PHY register %i with mask %i\n",val,phyreg,mask);
rval=mdio_read(priv,phyreg);
rval=(rval&~mask)|(val&mask);
mdio_write(priv,phyreg,rval);
}
/* handle errata data on MDIO bus */
//static void mdio_errata(meth_private *priv)
//{
/* Hmmm... what the hell is phyerrata? does it come from sys init parameters in IRIX */
//}
static int mdio_probe(meth_private *priv)
{
int i, p2, p3;
DPRINTK("Detecting PHY kind\n");
/* check if phy is detected already */
if(priv->phy_addr>=0&&priv->phy_addr<32)
return 0;
spin_lock_irq(priv->meth_lock);
for (i=0;i<32;++i){
priv->phy_addr=(char)i;
p2=mdio_read(priv,2);
#ifdef MFE_DEBUG
p3=mdio_read(priv,3);
switch ((p2<<12)|(p3>>4)){
case PHY_QS6612X:
DPRINTK("PHY is QS6612X\n");
break;
case PHY_ICS1889:
DPRINTK("PHY is ICS1889\n");
break;
case PHY_ICS1890:
DPRINTK("PHY is ICS1890\n");
break;
case PHY_DP83840:
DPRINTK("PHY is DP83840\n");
break;
}
#endif
if(p2!=0xffff&&p2!=0x0000){
DPRINTK("PHY code: %x\n",(p2<<12)|(p3>>4));
break;
}
}
spin_unlock_irq(priv->meth_lock);
if(priv->phy_addr<32) {
return 0;
}
DPRINTK("Oopsie! PHY is not known!\n");
priv->phy_addr=-1;
return -ENODEV;
}
static int meth_init_tx_ring(meth_private *priv)
{
/* Init TX ring */
DPRINTK("Initializing TX ring\n");
priv->tx_ring=(tx_packet*)pci_alloc_consistent(NULL,TX_RING_BUFFER_SIZE,&(priv->tx_ring_dma));
if(!priv->tx_ring)
return -ENOMEM;
memset(priv->tx_ring,0,TX_RING_BUFFER_SIZE);
priv->regs->tx_ring_base=priv->tx_ring_dma;
priv->free_space=TX_RING_ENTRIES;
/* Now init ksb save area */
memset(priv->tx_skbs,0,sizeof(priv->tx_skbs));
memset(priv->tx_skb_dmas,0,sizeof(priv->tx_skb_dmas));
DPRINTK("Done with TX ring init\n");
return 0;
}
static int meth_init_rx_ring(meth_private *priv)
{
int i;
DPRINTK("Initializing RX ring\n");
for(i=0;i<RX_RING_ENTRIES;i++){
DPRINTK("\t1:\t%i\n",i);
/*if(!(priv->rx_ring[i]=get_free_page(GFP_KERNEL)))
return -ENOMEM;
DPRINTK("\t2:\t%i\n",i);*/
priv->rx_ring[i]=(rx_packet*)pci_alloc_consistent(NULL,METH_RX_BUFF_SIZE,&(priv->rx_ring_dmas[i]));
/* I'll need to re-sync it after each RX */
DPRINTK("\t2:\t%i\n",i);
priv->regs->rx_fifo=priv->rx_ring_dmas[i];
}
DPRINTK("Done with RX ring\n");
return 0;
}
static void meth_free_tx_ring(meth_private *priv)
{
pci_free_consistent(NULL,TX_RING_BUFFER_SIZE,priv->tx_ring,priv->tx_ring_dma);
}
static void meth_free_rx_ring(meth_private *priv)
{
int i;
for(i=0;i<RX_RING_ENTRIES;i++)
pci_free_consistent(NULL,TX_RING_BUFFER_SIZE,priv->rx_ring[i],priv->rx_ring_dmas[i]);
}
/*============End Helper Routines=====================*/
/*
* Open and close
*/
int meth_open(struct net_device *dev)
{
meth_private *priv=dev->priv;
volatile meth_regs *regs=priv->regs;
MOD_INC_USE_COUNT;
/* Start DMA */
regs->dma_ctrl|=
METH_DMA_TX_EN|/*METH_DMA_TX_INT_EN|*/
METH_DMA_RX_EN|METH_DMA_RX_INT_EN;
if(request_irq(dev->irq,meth_interrupt,SA_SHIRQ,meth_str,dev)){
printk(KERN_ERR "%s: Can't get irq %d\n", dev->name, dev->irq);
return -EAGAIN;
}
netif_start_queue(dev);
DPRINTK("Opened... DMA control=0x%08lx\n", regs->dma_ctrl);
return 0;
}
int meth_release(struct net_device *dev)
{
netif_stop_queue(dev); /* can't transmit any more */
/* shut down dma */
((meth_private*)(dev->priv))->regs->dma_ctrl&=
~(METH_DMA_TX_EN|METH_DMA_TX_INT_EN|
METH_DMA_RX_EN|METH_DMA_RX_INT_EN);
free_irq(dev->irq, dev);
MOD_DEC_USE_COUNT;
return 0;
}
/*
* Configuration changes (passed on by ifconfig)
*/
int meth_config(struct net_device *dev, struct ifmap *map)
{
if (dev->flags & IFF_UP) /* can't act on a running interface */
return -EBUSY;
/* Don't allow changing the I/O address */
if (map->base_addr != dev->base_addr) {
printk(KERN_WARNING "meth: Can't change I/O address\n");
return -EOPNOTSUPP;
}
/* Allow changing the IRQ */
if (map->irq != dev->irq) {
printk(KERN_WARNING "meth: Can't change IRQ\n");
return -EOPNOTSUPP;
}
DPRINTK("Configured\n");
/* ignore other fields */
return 0;
}
/*
* Receive a packet: retrieve, encapsulate and pass over to upper levels
*/
void meth_rx(struct net_device* dev)
{
struct sk_buff *skb;
struct meth_private *priv = (struct meth_private *) dev->priv;
rx_packet *rxb;
DPRINTK("RX...\n");
while((rxb=priv->rx_ring[priv->rx_write])->status.raw&0x8000000000000000){
int len=rxb->status.parsed.rx_len;
DPRINTK("\tpriv->tx_write=%i\n",priv->rx_write);
if(!(rxb->status.raw&METH_RX_STATUS_ERRORS)){
DPRINTK("Packet had no errors...\n");
skb=alloc_skb(len+2,GFP_ATOMIC);/* Should be atomic -- we are in interrupt */
if(!skb){
/* Ouch! No memory! Drop packet on the floor */
DPRINTK("!!!>>>Ouch! Not enough Memory for RX buffer!\n");
priv->stats.tx_dropped++;
} else {
DPRINTK("And there was no problem getting new skb...\n");
skb_reserve(skb, 2); /* align IP on 16B boundary */
memcpy(skb_put(skb, len), rxb->buf, len);
/* Write metadata, and then pass to the receive level */
skb->dev = dev;
skb->protocol = eth_type_trans(skb, dev);
//skb->ip_summed = CHECKSUM_UNNECESSARY; /* don't check it */
priv->stats.rx_packets++;
DPRINTK("We are about to pass packet up\n");
netif_rx(skb);
DPRINTK("There we go... Whew...\n");
}
}
rxb->status.raw=0;
priv->regs->rx_fifo=priv->rx_ring_dmas[priv->rx_write];
priv->rx_write=(priv->rx_write+1)&(RX_RING_ENTRIES-1);
}
}
void meth_tx_cleanup(struct net_device* dev, int rptr)
{
meth_private *priv=dev->priv;
//volatile meth_regs* regs=priv->regs;
tx_packet* status;
struct sk_buff* skb;
DPRINTK("TX...\n");
spin_lock(&priv->meth_lock);
priv->regs->dma_ctrl&=~(METH_DMA_TX_INT_EN);
while(priv->tx_read!=rptr){
skb=priv->tx_skbs[priv->tx_read];
status=&priv->tx_ring[priv->tx_read];
if(!status->header.res.sent)
break;
if(status->header.raw&METH_TX_STATUS_DONE){
priv->stats.tx_packets++;
priv->stats.tx_bytes+=skb->len;
}
dev_kfree_skb(skb);
status->header.raw=0;
priv->tx_read=(priv->tx_read+1)&(TX_RING_ENTRIES-1);
}
spin_unlock(priv->meth_lock);
netif_wake_queue(dev);
}
/*
* The typical interrupt entry point
*/
void meth_interrupt(int irq, void *dev_id, struct pt_regs *pregs)
{
struct meth_private *priv;
//volatile meth_regs* regs;
union {
u32 reg; /*Whole status register */
struct {
u32 : 2,
rx_seq : 5,
tx_read : 9,
rx_read : 8,
int_mask: 8;
} parsed;
} status;
/*
* As usual, check the "device" pointer for shared handlers.
* Then assign "struct device *dev"
*/
struct net_device *dev = (struct net_device *)dev_id;
/* ... and check with hw if it's really ours */
if (!dev /*paranoid*/ ) return;
/* Lock the device */
priv = (struct meth_private *) dev->priv;
spin_lock(&priv->meth_lock);
status.reg = priv->regs->int_flags;
priv->regs->int_flags=status.reg&0xff; /* clear interrupts */
DPRINTK("Interrupt, status %08x...\n",status.reg);
if (status.parsed.int_mask & METH_INT_RX_THRESHOLD) {
/* send it to meth_rx for handling */
meth_rx(dev);
}
if (status.parsed.int_mask & (METH_INT_TX_EMPTY|METH_INT_TX_PKT)) {
/* a transmission is over: free the skb */
meth_tx_cleanup(dev,status.parsed.tx_read);
}
/* check for errors too... */
DPRINTK("Interrupt handling done...\n");
/* Unlock the device and we are done */
spin_unlock(&priv->meth_lock);
}
/*
* Transmits packets that fit into TX describtor (are <=120B)
*/
static void meth_tx_short_prepare(meth_private* priv, struct sk_buff* skb)
{
tx_packet *desc=&priv->tx_ring[priv->tx_write];
int len=(skb->len<ETH_ZLEN)?ETH_ZLEN:skb->len;
DPRINTK("Short packet... \n");
/* amybe I should set whole thing to 0 first... */
memcpy(desc->data.dt+(120-len),skb->data,skb->len);
if(skb->len<len)
memset(desc->data.dt+120-len+skb->len,0,len-skb->len);
desc->header.raw=METH_TX_CMD_INT_EN|(len-1)|((128-len)<<16);
DPRINTK("desc=%016lx\n",desc->header.raw);
}
#define TX_CATBUF1 BIT(25)
static void meth_tx_1page_prepare(meth_private* priv, struct sk_buff* skb)
{
tx_packet *desc=&priv->tx_ring[priv->tx_write];
void *data=skb->data;
int len=(u64)data&0x7;
dma_addr_t catbuf;
desc->header.raw=METH_TX_CMD_INT_EN|TX_CATBUF1|(skb->len-1);
if(len){
memcpy(desc->data.dt+(120-len),data,len);
desc->header.raw|=(128-len)<<16;
}
data+=len;
/* I'll just pretend I know for sure that pci_unmap_single is NOP */
catbuf=pci_map_single(NULL,data,skb->len-len,PCI_DMA_TODEVICE);
desc->data.cat_buf[0].raw=catbuf|((skb->len-len-1)<<31);
}
#define TX_CATBUF2 BIT(26)
static void meth_tx_2page_prepare(meth_private* priv, struct sk_buff* skb)
{
tx_packet *desc=&priv->tx_ring[priv->tx_write];
void *data=skb->data;
int len=(u64)data&0x7;
dma_addr_t catbuf1,catbuf2;
desc->header.raw=METH_TX_CMD_INT_EN|TX_CATBUF1|TX_CATBUF2|(skb->len-1);
if(len){
memcpy(desc->data.dt+(120-len),data,len);
desc->header.raw|=(128-len)<<16;
}
data+=len;
/* I'll just pretend I know for sure that pci_unmap_single is NOP */
catbuf1=pci_map_single(NULL,data,skb->len-len,PCI_DMA_TODEVICE);
desc->data.cat_buf[0].raw=catbuf1|((skb->len-len-1)<<31);
len=(u64)data&0xFFF;
data+=len;
catbuf2=pci_map_single(NULL,data,skb->len-((u64)data-(u64)skb->data),PCI_DMA_TODEVICE);
desc->data.cat_buf[1].raw=catbuf2|((skb->len-((u64)data-(u64)skb->data))<<31);
}
/*
* Transmit a packet (called by the kernel)
*/
int meth_tx(struct sk_buff *skb, struct net_device *dev)
{
struct meth_private *priv = (struct meth_private *) dev->priv;
spin_lock(&priv->meth_lock);
DPRINTK("Transmitting data...\n");
if(skb->len<=120) /* Whole thing fits into descriptor */
meth_tx_short_prepare(priv,skb);
else if(((u64)(skb->data)&0xFFF)<skb->len) /* Packet crosses page boundary */
meth_tx_2page_prepare(priv,skb);
else /* Packet is in one page */
meth_tx_1page_prepare(priv,skb);
dev->trans_start = jiffies; /* save the timestamp */
/* Remember the skb, so we can free it at interrupt time */
priv->tx_skbs[priv->tx_write] = skb;
priv->regs->tx_info.wptr=priv->tx_write;
priv->tx_write=(priv->tx_write+1)&(TX_RING_ENTRIES-1);
priv->regs->dma_ctrl|=METH_DMA_TX_INT_EN;
spin_unlock(&priv->meth_lock);
return 0;
}
/*
* Deal with a transmit timeout.
*/
/*
void meth_tx_timeout (struct net_device *dev)
{
struct meth_private *priv = (struct meth_private *) dev->priv;
DPRINTK("Transmit timeout at %ld, latency %ld\n", jiffies,
jiffies - dev->trans_start);
priv->status = meth_TX_INTR;
meth_interrupt(0, dev, NULL);
priv->stats.tx_errors++;
netif_wake_queue(dev);
return;
}
*/
/*
* Ioctl commands
*/
int meth_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
{
DPRINTK("ioctl\n");
return 0;
}
/*
* Return statistics to the caller
*/
struct net_device_stats *meth_stats(struct net_device *dev)
{
struct meth_private *priv = (struct meth_private *) dev->priv;
return &priv->stats;
}
/*
* The init function (sometimes called probe).
* It is invoked by register_netdev()
*/
int meth_init(struct net_device *dev)
{
meth_private *priv;
volatile meth_regs* regs;
int ret;
/*
* Then, assign other fields in dev, using ether_setup() and some
* hand assignments
*/
ether_setup(dev); /* assign some of the fields */
dev->open = meth_open;
dev->stop = meth_release;
dev->set_config = meth_config;
dev->hard_start_xmit = meth_tx;
dev->do_ioctl = meth_ioctl;
dev->get_stats = meth_stats;
/*#ifdef HAVE_TX_TIMEOUT
dev->tx_timeout = meth_tx_timeout;
dev->watchdog_timeo = timeout;
#endif*/
dev->irq = MACE_ETHERNET_IRQ;
SET_MODULE_OWNER(dev);
/*
* Then, allocate the priv field. This encloses the statistics
* and a few private fields.
*/
priv = kmalloc(sizeof(struct meth_private), GFP_KERNEL);
if (priv == NULL)
return -ENOMEM;
dev->priv=priv;
memset(priv, 0, sizeof(struct meth_private));
spin_lock_init(& (struct meth_private *) (dev->priv)->meth_lock);
/*
* Make the usual checks: check_region(), probe irq, ... -ENODEV
* should be returned if no device found. No resource should be
* grabbed: this is done on open().
*/
priv->regs=(meth_regs*)SGI_MFE;
dev->base_addr=SGI_MFE;
regs=(meth_regs*)SGI_MFE;
/* Reset card */
regs->mac_ctrl=SGI_MAC_RESET;
regs->mac_ctrl=0;
udelay(25);
DPRINTK("MAC control after reset: %016lx\n",regs->mac_ctrl);
printk("SGI O2 Fast Ethernet rev. %ld\n",regs->mac_ctrl>>29);
load_eaddr(dev,regs);
priv->phy_addr=-1; /* No phy is known yet... */
if(mdio_probe(priv)<0){
DPRINTK("Unable to find PHY\n");
return -ENODEV;
}
/* Should load some "errata", but later */
/* Initial mode -- 100|Half-duplex|Acept normal packets */
priv->mode=METH_ACCEPT_MCAST|METH_100MBIT|METH_DEFAULT_IPG;
if(dev->flags|IFF_PROMISC)
priv->mode|=METH_PROMISC;
regs->mac_ctrl=priv->mode;
if((ret=meth_init_tx_ring(priv))<0||(ret=meth_init_rx_ring(priv))<0){
meth_free_tx_ring(priv);
meth_free_rx_ring(priv);
return ret;
}
/* Now set dma control, but don't enable DMA, yet */
priv->regs->dma_ctrl=(4<<METH_RX_OFFSET_SHIFT)|(RX_RING_ENTRIES<<METH_RX_DEPTH_SHIFT);
return 0;
}
/*
* The devices
*/
struct net_device meth_devs[1] = {
{ init: meth_init, } /* init, nothing more */
};
/*
* Finally, the module stuff
*/
int meth_init_module(void)
{
int result, device_present = 0;
strcpy(meth_devs[0].name, "eth%d");
if ( (result = register_netdev(meth_devs)) )
printk("meth: error %i registering device \"%s\"\n",
result, meth_devs->name);
else device_present++;
#ifndef METH_DEBUG
EXPORT_NO_SYMBOLS;
#endif
return device_present ? 0 : -ENODEV;
}
void meth_cleanup(void)
{
kfree(meth_devs->priv);
unregister_netdev(meth_devs);
return;
}
module_init(meth_init_module);
module_exit(meth_cleanup);
--- NEW FILE: meth.h ---
/*
* snull.h -- definitions for the network module
*
* Copyright (C) 2001 Alessandro Rubini and Jonathan Corbet
* Copyright (C) 2001 O'Reilly & Associates
*
* The source code in this file can be freely used, adapted,
* and redistributed in source or binary form, so long as an
* acknowledgment appears in derived source files. The citation
* should list that the code comes from the book "Linux Device
* Drivers" by Alessandro Rubini and Jonathan Corbet, published
* by O'Reilly & Associates. No warranty is attached;
* we cannot take responsibility for errors or fitness for use.
*/
/* version dependencies have been confined to a separate file */
#define SGI_MFE (MACE_BASE+MACE_ENET)
/* (0xBF280000)*/
/* Tunable parameters */
#define TX_RING_ENTRIES 64 /* 64-512?*/
#define RX_RING_ENTRIES 16 /* Do not change */
/* Internal constants */
#define TX_RING_BUFFER_SIZE (TX_RING_ENTRIES*sizeof(tx_packet))
#define RX_BUFFER_SIZE 1546 /* ethenet packet size */
#define METH_RX_BUFF_SIZE 4096
#define RX_BUFFER_OFFSET (sizeof(rx_status_vector)+2) /* staus vector + 2 bytes of padding */
#define RX_BUCKET_SIZE 256
/* For more detailed explanations of what each field menas,
see Nick's great comments to #defines below (or docs, if
you are lucky enough toget hold of them :)*/
/* tx status vector is written over tx command header upon
dma completion. */
typedef struct tx_status_vector {
u64 sent:1; /* always set to 1...*/
u64 pad0:34;/* always set to 0 */
u64 flags:9; /*I'm too lazy to specify each one separately at the moment*/
u64 col_retry_cnt:4; /*collision retry count*/
u64 len:16; /*Transmit length in bytes*/
} tx_status_vector;
/*
* Each packet is 128 bytes long.
* It consists of header, 0-3 concatination
* buffer pointers and up to 120 data bytes.
*/
typedef struct tx_packet_hdr {
u64 pad1:36; /*should be filled with 0 */
u64 cat_ptr3_valid:1, /*Concatination pointer valid flags*/
cat_ptr2_valid:1,
cat_ptr1_valid:1;
u64 tx_int_flag:1; /*Generate TX intrrupt when packet has been sent*/
u64 term_dma_flag:1; /*Terminate transmit DMA on transmit abort conditions*/
u64 data_offset:7; /*Starting byte offset in ring data block*/
u64 data_len:16; /*Length of valid data in bytes-1*/
} tx_packet_hdr;
typedef union tx_cat_ptr {
struct {
u64 pad2:16; /* should be 0 */
u64 len:16; /*length of buffer data - 1*/
u64 start_addr:29; /*Physical starting address*/
u64 pad1:3; /* should be zero */
} form;
u64 raw;
} tx_cat_ptr;
typedef struct tx_packet {
union {
tx_packet_hdr header;
tx_status_vector res;
u64 raw;
}header;
union {
tx_cat_ptr cat_buf[3];
char dt[120];
} data;
} tx_packet;
typedef union rx_status_vector {
struct {
u64 pad1:1;/*fill it with ones*/
u64 pad2:15;/*fill with 0*/
u64 ip_chk_sum:16;
u64 seq_num:5;
u64 mac_addr_match:1;
u64 mcast_addr_match:1;
u64 carrier_event_seen:1;
u64 bad_packet:1;
u64 long_event_seen:1;
u64 invalid_preamble:1;
u64 broadcast:1;
u64 multicast:1;
u64 crc_error:1;
u64 huh:1;/*???*/
u64 rx_code_violation:1;
u64 rx_len:16;
} parsed;
u64 raw;
} rx_status_vector;
typedef struct rx_packet {
rx_status_vector status;
u64 pad[4]; /* For whatever reason, there needs to be 4 double-word offset */
char buf[METH_RX_BUFF_SIZE-sizeof(rx_status_vector)-sizeof(u64)];/* data */
} rx_packet;
typedef struct meth_regs {
u64 mac_ctrl; /*0x00,rw,31:0*/
u64 int_flags; /*0x08,rw,30:0*/
u64 dma_ctrl; /*0x10,rw,15:0*/
u64 timer; /*0x18,rw,5:0*/
u64 int_tx; /*0x20,wo,0:0*/
u64 int_rx; /*0x28,wo,9:4*/
struct {
u32 tx_info_pad;
u32 rptr:16,wptr:16;
} tx_info; /*0x30,rw,31:0*/
u64 tx_info_al; /*0x38,rw,31:0*/
struct {
u32 rx_buff_pad1;
u32 rx_buff_pad2:8,
wptr:8,
rptr:8,
depth:8;
} rx_buff; /*0x40,ro,23:0*/
u64 rx_buff_al1; /*0x48,ro,23:0*/
u64 rx_buff_al2; /*0x50,ro,23:0*/
u64 int_update; /*0x58,wo,31:0*/
u32 phy_data_pad;
u32 phy_data; /*0x60,rw,16:0*/
u32 phy_reg_pad;
u32 phy_registers; /*0x68,rw,9:0*/
u64 phy_trans_go; /*0x70,wo,0:0*/
u64 backoff_seed; /*0x78,wo,10:0*/
u64 imq_reserved[4];/*0x80,ro,64:0(x4)*/
/*===================================*/
u64 mac_addr; /*0xA0,rw,47:0, I think it's MAC address, but I'm not sure*/
u64 mcast_addr; /*0xA8,rw,47:0, This seems like secondary MAC address*/
u64 mcast_filter; /*0xB0,rw,63:0*/
u64 tx_ring_base; /*0xB8,rw,31:13*/
/* Following are read-only debugging info register */
u64 tx_pkt1_hdr; /*0xC0,ro,63:0*/
u64 tx_pkt1_ptr[3]; /*0xC8,ro,63:0(x3)*/
u64 tx_pkt2_hdr; /*0xE0,ro,63:0*/
u64 tx_pkt2_ptr[3]; /*0xE8,ro,63:0(x3)*/
/*===================================*/
u32 rx_pad;
u32 rx_fifo;
u64 reserved[31];
}meth_regs;
/* Bits in METH_MAC */
#define SGI_MAC_RESET BIT(0) /* 0: MAC110 active in run mode, 1: Global reset signal to MAC110 core is active */
#define METH_PHY_FDX BIT(1) /* 0: Disable full duplex, 1: Enable full duplex */
#define METH_PHY_LOOP BIT(2) /* 0: Normal operation, follows 10/100mbit and M10T/MII select, 1: loops internal MII bus */
/* selects ignored */
#define METH_100MBIT BIT(3) /* 0: 10meg mode, 1: 100meg mode */
#define METH_PHY_MII BIT(4) /* 0: MII selected, 1: SIA selected */
/* Note: when loopback is set this bit becomes collision control. Setting this bit will */
/* cause a collision to be reported. */
/* Bits 5 and 6 are used to determine the the Destination address filter mode */
#define METH_ACCEPT_MY 0 /* 00: Accept PHY address only */
#define METH_ACCEPT_MCAST 0x20 /* 01: Accept physical, broadcast, and multicast filter matches only */
#define METH_ACCEPT_AMCAST 0x40 /* 10: Accept physical, broadcast, and all multicast packets */
#define METH_PROMISC 0x60 /* 11: Promiscious mode */
#define METH_PHY_LINK_FAIL BIT(7) /* 0: Link failure detection disabled, 1: Hardware scans for link failure in PHY */
#define METH_MAC_IPG 0x1ffff00
#define METH_DEFAULT_IPG ((17<<15) | (11<<22) | (21<<8))
/* 0x172e5c00 */ /* 23, 23, 23 */ /*0x54A9500 *//*21,21,21*/
/* Bits 8 through 14 are used to determine Inter-Packet Gap between "Back to Back" packets */
/* The gap depends on the clock speed of the link, 80ns per increment for 100baseT, 800ns */
/* per increment for 10BaseT */
/* Bits 15 through 21 are used to determine IPGR1 */
/* Bits 22 through 28 are used to determine IPGR2 */
#define METH_REV_SHIFT 29 /* Bits 29 through 31 are used to determine the revision */
/* 000: Inital revision */
/* 001: First revision, Improved TX concatenation */
/* DMA control bits */
#define METH_RX_OFFSET_SHIFT 12 /* Bits 12:14 of DMA control register indicate starting offset of packet data for RX operation */
#define METH_RX_DEPTH_SHIFT 4 /* Bits 8:4 define RX fifo depth -- when # of RX fifo entries != depth, interrupt is generted */
#define METH_DMA_TX_EN BIT(1) /* enable TX DMA */
#define METH_DMA_TX_INT_EN BIT(0) /* enable TX Buffer Empty interrupt */
#define METH_DMA_RX_EN BIT(15) /* Enable RX */
#define METH_DMA_RX_INT_EN BIT(9) /* Enable interrupt on RX packet */
/* RX status bits */
#define METH_RX_ST_RCV_CODE_VIOLATION BIT(16)
#define METH_RX_ST_DRBL_NBL BIT(17)
#define METH_RX_ST_CRC_ERR BIT(18)
#define METH_RX_ST_MCAST_PKT BIT(19)
#define METH_RX_ST_BCAST_PKT BIT(20)
#define METH_RX_ST_INV_PREAMBLE_CTX BIT(21)
#define METH_RX_ST_LONG_EVT_SEEN BIT(22)
#define METH_RX_ST_BAD_PACKET BIT(23)
#define METH_RX_ST_CARRIER_EVT_SEEN BIT(24)
#define METH_RX_ST_MCAST_FILTER_MATCH BIT(25)
#define METH_RX_ST_PHYS_ADDR_MATCH BIT(26)
#define METH_RX_STATUS_ERRORS \
( \
METH_RX_ST_RCV_CODE_VIOLATION| \
METH_RX_ST_CRC_ERR| \
METH_RX_ST_INV_PREAMBLE_CTX| \
METH_RX_ST_LONG_EVT_SEEN| \
METH_RX_ST_BAD_PACKET| \
METH_RX_ST_CARRIER_EVT_SEEN \
)
/* Bits in METH_INT */
/* Write _1_ to corresponding bit to clear */
#define METH_INT_TX_EMPTY BIT(0) /* 0: No interrupt pending, 1: The TX ring buffer is empty */
#define METH_INT_TX_PKT BIT(1) /* 0: No interrupt pending */
/* 1: A TX message had the INT request bit set, the packet has been sent. */
#define METH_INT_TX_LINK_FAIL BIT(2) /* 0: No interrupt pending, 1: PHY has reported a link failure */
#define METH_INT_MEM_ERROR BIT(3) /* 0: No interrupt pending */
/* 1: A memory error occurred durring DMA, DMA stopped, Fatal */
#define METH_INT_TX_ABORT BIT(4) /* 0: No interrupt pending, 1: The TX aborted operation, DMA stopped, FATAL */
#define METH_INT_RX_THRESHOLD BIT(5) /* 0: No interrupt pending, 1: Selected receive threshold condition Valid */
#define METH_INT_RX_UNDERFLOW BIT(6) /* 0: No interrupt pending, 1: FIFO was empty, packet could not be queued */
#define METH_INT_RX_OVERFLOW BIT(7) /* 0: No interrupt pending, 1: DMA FIFO Overflow, DMA stopped, FATAL */
/* Bits 8 through 12 alias of RX read-pointer */
/* Bits 13 through 15 are always 0. */
#define METH_INT_RPTR_MASK 0x1FF0000 /* Bits 16 through 24 alias of TX read-pointer */
/* Bits 25 through 29 are the starting seq number for the message at the */
/* top of the queue */
#define METH_ERRORS ( \
METH_INT_RX_OVERFLOW| \
METH_INT_RX_UNDERFLOW| \
METH_INT_MEM_ERROR| \
METH_INT_TX_ABORT)
#define METH_INT_MCAST_HASH BIT(30) /* If RX DMA is enabled the hash select logic output is latched here */
/* TX status bits */
#define METH_TX_STATUS_DONE BIT(23) /* Packet was transmitted successfully */
/* Tx command header bits */
#define METH_TX_CMD_INT_EN BIT(24) /* Generate TX interrupt when packet is sent */
/* Phy MDIO interface busy flag */
#define MDIO_BUSY BIT(16)
#define MDIO_DATA_MASK 0xFFFF
/* PHY defines */
#define PHY_QS6612X 0x0181441 /* Quality TX */
#define PHY_ICS1889 0x0015F41 /* ICS FX */
#define PHY_ICS1890 0x0015F42 /* ICS TX */
#define PHY_DP83840 0x20005C0 /* National TX */
|
|
From: James S. <jsi...@us...> - 2001-11-28 17:13:10
|
Update of /cvsroot/linux-mips/linux/include/asm-mips64/ip32
In directory usw-pr-cvs1:/tmp/cvs-serv6803/include/asm-mips64/ip32
Modified Files:
io.h mace.h
Log Message:
O2 ipdates.
Index: io.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips64/ip32/io.h,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- io.h 2001/09/04 22:41:02 1.1
+++ io.h 2001/11/28 17:13:07 1.2
@@ -3,7 +3,12 @@
#include <asm/ip32/mace.h>
-#define UNCACHEDADDR(x) (0x9000000000000000UL | (x))
+/*#ifdef CONFIG_MIPS_UNCACHED*/
+#define UNCACHEDADDR(x) (0x9000000000000000UL | (u64)(x))
+/*#else
+#define UNCACHEDADDR(x) (x)
+#endif*/
+/*#define UNCACHEDADDR(x) (KSEG1ADDR (x)) */
#define IO_SPACE_BASE UNCACHEDADDR (MACEPCI_HI_MEMORY)
#define IO_SPACE_LIMIT 0xffffffffUL
Index: mace.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips64/ip32/mace.h,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -d -r1.2 -r1.3
--- mace.h 2001/10/31 18:26:53 1.2
+++ mace.h 2001/11/28 17:13:07 1.3
@@ -31,54 +31,7 @@
#define MACE_I2C_BASE (MACE_PERIF + 0x00030000)
#define MACE_UST_BASE (MACE_PERIF + 0x00040000)
-#ifndef _LANGUAGE_ASSEMBLY
-#include <asm/types.h>
-
-/*
- * XXX Some of these are probably not needed (or even legal?)
- */
-static inline u8 mace_read_8 (unsigned long __offset)
-{
- return *((volatile u8 *) (MACE_BASE + __offset));
-}
-static inline u16 mace_read_16 (unsigned long __offset)
-{
- return *((volatile u16 *) (MACE_BASE + __offset));
-}
-
-static inline u32 mace_read_32 (unsigned long __offset)
-{
- return *((volatile u32 *) (MACE_BASE + __offset));
-}
-
-static inline u64 mace_read_64 (unsigned long __offset)
-{
- return *((volatile u64 *) (MACE_BASE + __offset));
-}
-
-static inline void mace_write_8 (unsigned long __offset, u8 __val)
-{
- *((volatile u8 *) (MACE_BASE + __offset)) = __val;
-}
-
-static inline void mace_write_16 (unsigned long __offset, u16 __val)
-{
- *((volatile u16 *) (MACE_BASE + __offset)) = __val;
-}
-
-static inline void mace_write_32 (unsigned long __offset, u32 __val)
-{
- *((volatile u32 *) (MACE_BASE + __offset)) = __val;
-}
-
-static inline void mace_write_64 (unsigned long __offset, u64 __val)
-{
- *((volatile u64 *) (MACE_BASE + __offset)) = __val;
-}
-
-#endif
-
#undef BIT
#define BIT(__bit_offset) (1UL << (__bit_offset))
@@ -89,7 +42,7 @@
#define MACEPCI_ERROR_FLAGS (MACE_PCI + 0x00000004)
#define MACEPCI_CONTROL (MACE_PCI + 0x00000008)
#define MACEPCI_REV (MACE_PCI + 0x0000000c)
-#define MACEPCI_WFLUSH (MACE_PCI + 0x0000000c) /* ??? */
+#define MACEPCI_WFLUSH (MACE_PCI + 0x0000000c) /* ??? --IV !!! It's for flushing read buffers on PCI MEMORY accesses!!! */
#define MACEPCI_CONFIG_ADDR (MACE_PCI + 0x00000cf8)
#define MACEPCI_CONFIG_DATA (MACE_PCI + 0x00000cfc)
#define MACEPCI_LOW_MEMORY 0x1a000000
@@ -97,7 +50,8 @@
#define MACEPCI_SWAPPED_VIEW 0
#define MACEPCI_NATIVE_VIEW 0x40000000
#define MACEPCI_IO 0x80000000
-#define MACEPCI_HI_MEMORY 0x0000000280000000UL
+/*#define MACEPCI_HI_MEMORY 0x0000000280000000UL * This mipght be just 0x0000000200000000UL 2G more :) (or maybe it is different between 1.1 & 1.5 */
+#define MACEPCI_HI_MEMORY 0x0000000200000000UL /* This mipght be just 0x0000000200000000UL 2G more :) (or maybe it is different between 1.1 & 1.5 */
#define MACEPCI_HI_IO 0x0000000100000000UL
/*
@@ -242,5 +196,59 @@
#define MACEISA_SERIAL2_TDMAME_INT BIT (29)
#define MACEISA_SERIAL2_RDMAT_INT BIT (30)
#define MACEISA_SERIAL2_RDMAOR_INT BIT (31)
+
+#ifndef _LANGUAGE_ASSEMBLY
+#include <asm/types.h>
+
+/*
+ * XXX Some of these are probably not needed (or even legal?)
+ */
+static inline u8 mace_read_8 (unsigned long __offset)
+{
+ return *((volatile u8 *) (MACE_BASE + __offset));
+}
+
+static inline u16 mace_read_16 (unsigned long __offset)
+{
+ return *((volatile u16 *) (MACE_BASE + __offset));
+}
+
+static inline u32 mace_read_32 (unsigned long __offset)
+{
+ return *((volatile u32 *) (MACE_BASE + __offset));
+}
+
+static inline u64 mace_read_64 (unsigned long __offset)
+{
+ return *((volatile u64 *) (MACE_BASE + __offset));
+}
+
+static inline void mace_write_8 (unsigned long __offset, u8 __val)
+{
+ *((volatile u8 *) (MACE_BASE + __offset)) = __val;
+}
+
+static inline void mace_write_16 (unsigned long __offset, u16 __val)
+{
+ *((volatile u16 *) (MACE_BASE + __offset)) = __val;
+}
+
+static inline void mace_write_32 (unsigned long __offset, u32 __val)
+{
+ *((volatile u32 *) (MACE_BASE + __offset)) = __val;
+}
+
+static inline void mace_write_64 (unsigned long __offset, u64 __val)
+{
+ *((volatile u64 *) (MACE_BASE + __offset)) = __val;
+}
+
+/* Call it whenever device needs to read data from main memory coherently */
+static inline void mace_inv_read_buffers(void)
+{
+/* mace_write_32(MACEPCI_WFLUSH,0xffffffff);*/
+}
+#endif
+
#endif /* __ASM_MACE_H__ */
|
|
From: James S. <jsi...@us...> - 2001-11-28 17:13:10
|
Update of /cvsroot/linux-mips/linux/arch/mips64/sgi-ip32
In directory usw-pr-cvs1:/tmp/cvs-serv6803/arch/mips64/sgi-ip32
Modified Files:
ip32-pci-dma.c ip32-pci.c ip32-reset.c ip32-setup.c
Log Message:
O2 ipdates.
Index: ip32-pci-dma.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips64/sgi-ip32/ip32-pci-dma.c,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- ip32-pci-dma.c 2001/10/26 16:13:55 1.3
+++ ip32-pci-dma.c 2001/11/28 17:13:07 1.4
@@ -16,67 +16,186 @@
#include <asm/addrspace.h>
#include <asm/ip32/mace.h>
+#ifndef PCI_DMA_DEBUG
+#define PCI_DMA_DEBUG 0
+#endif
+
+#if PCI_DMA_DEBUG>=1
+#define DPRINTK(str,args...) printk (KERN_DEBUG "MACEPCI: %s: " str, __FUNCTION__ , ## args)
+#else
+#define DPRINTK(str,args...)
+#endif
+
+#define mips_wbflush() __asm__ __volatile__ ("sync" : : : "memory")
+/*#define mace_inv_read_buffers mips_wbflush*/
+
+/* Pure 2^n version of get_order */
+extern __inline__ int get_order(unsigned long size)
+{
+ int order;
+
+ size = (size-1) >> (PAGE_SHIFT-1);
+ order = -1;
+ do {
+ size >>= 1;
+ order++;
+ } while (size);
+ return order;
+}
+
void *pci_alloc_consistent(struct pci_dev *hwdev, size_t size,
dma_addr_t * dma_handle)
{
void *ret;
int gfp = GFP_ATOMIC;
- if (hwdev == NULL || hwdev->dma_mask != 0xffffffff)
+ if (hwdev != NULL && hwdev->dma_mask != 0xffffffff)
gfp |= GFP_DMA;
ret = (void *) __get_free_pages(gfp, get_order(size));
if (ret != NULL) {
memset(ret, 0, size);
dma_cache_wback_inv((unsigned long) ret, size);
- *dma_handle = KDM_TO_PHYS(ret);
+ *dma_handle = ( __pa (ret));
+ DPRINTK("pci_alloc_consistent: addr=%016lx; dma_handle=%08x\n",(u64)KSEG1ADDR(ret),*dma_handle);
+ return KSEG1ADDR(ret);
}
- return ret;
+ DPRINTK("pci_alloc_consistent2: addr=%016lx; dma_handle=%08x\n",(u64)KSEG1ADDR(ret),*dma_handle);
+ return NULL;
}
void pci_free_consistent(struct pci_dev *hwdev, size_t size,
void *vaddr, dma_addr_t dma_handle)
{
- free_pages((unsigned long) PHYS_TO_K0(vaddr), get_order(size));
+ DPRINTK("pci_free_consistent: addr=%016lx; dma_handle=%08x\n",(u64)KSEG0ADDR(vaddr),dma_handle);
+ free_pages((unsigned long) KSEG0ADDR(vaddr), get_order(size));
}
-
-/*
-dma_addr_t pci_map_single(struct pci_dev *hwdev, void *ptr, size_t size,
- int direction)
+dma_addr_t pci_map_single(struct pci_dev *hwdev, void *ptr,
+ size_t size, int direction)
{
if (direction == PCI_DMA_NONE)
BUG();
-
+
+ DPRINTK("pci_map_single: addr=%016lx; dma_handle=%08x\n",(u64)ptr,__pa(ptr));
+ mips_wbflush();
+ dma_cache_wback_inv((unsigned long)ptr, size);
+/* if(direction==PCI_DMA_TODEVICE)
+ mace_inv_read_buffers();*/
+ return (__pa(ptr));
}
+
+/*
+ * Unmap a single streaming mode DMA translation. The dma_addr and size
+ * must match what was provided for in a previous pci_map_single call. All
+ * other usages are undefined.
+ *
+ * After this call, reads by the cpu to the buffer are guarenteed to see
+ * whatever the device wrote there.
+ */
void pci_unmap_single(struct pci_dev *hwdev, dma_addr_t dma_addr,
- size_t size, int direction)
+ size_t size, int direction)
{
if (direction == PCI_DMA_NONE)
BUG();
+ DPRINTK("pci_unmap_single\n");
+ /* Nothing to do */
}
-int pci_map_sg(struct pci_dev *hwdev, struct scatterlist *sg, int nents,
- int direction)
+
+/*
+ * Map a set of buffers described by scatterlist in streaming
+ * mode for DMA. This is the scather-gather version of the
+ * above pci_map_single interface. Here the scatter gather list
+ * elements are each tagged with the appropriate dma address
+ * and length. They are obtained via sg_dma_{address,length}(SG).
+ *
+ * NOTE: An implementation may be able to use a smaller number of
+ * DMA address/length pairs than there are SG table elements.
+ * (for example via virtual mapping capabilities)
+ * The routine returns the number of addr/length pairs actually
+ * used, at most nents.
+ *
+ * Device ownership issues as mentioned above for pci_map_single are
+ * the same here.
+ */
+int pci_map_sg(struct pci_dev *hwdev, struct scatterlist *sg,
+ int nents, int direction)
{
+ int i;
+
if (direction == PCI_DMA_NONE)
BUG();
+
+/* if(direction==PCI_DMA_TODEVICE)
+ mace_inv_read_buffers();*/
+ DPRINTK("pci_map_sg\n");
+ /* Make sure that gcc doesn't leave the empty loop body. */
+ for (i = 0; i < nents; i++, sg++) {
+ mips_wbflush();
+ dma_cache_wback_inv((unsigned long)sg->address, sg->length);
+ sg->address = (char *)(__pa(sg->address));
+ }
+
+ return nents;
}
+
+/*
+ * Unmap a set of streaming mode DMA translations.
+ * Again, cpu read rules concerning calls here are the same as for
+ * pci_unmap_single() above.
+ */
void pci_unmap_sg(struct pci_dev *hwdev, struct scatterlist *sg,
- int nents, int direction)
+ int nents, int direction)
{
if (direction == PCI_DMA_NONE)
BUG();
+ DPRINTK("pci_unmap_sg\n");
+ /* Nothing to do */
}
-void pci_dma_sync_single(struct pci_dev *hwdev, dma_addr_t dma_handle,
- size_t size, int direction)
+
+/*
+ * Make physical memory consistent for a single
+ * streaming mode DMA translation after a transfer.
+ *
+ * If you perform a pci_map_single() but wish to interrogate the
+ * buffer using the cpu, yet do not wish to teardown the PCI dma
+ * mapping, you must call this function before doing so. At the
+ * next point you give the PCI dma address back to the card, the
+ * device again owns the buffer.
+ */
+void pci_dma_sync_single(struct pci_dev *hwdev,
+ dma_addr_t dma_handle,
+ size_t size, int direction)
{
if (direction == PCI_DMA_NONE)
BUG();
+ DPRINTK("pci_dma_sync_single: addr=%016lx dma_handle=%08x\n",__va(dma_handle),dma_handle);
+ mips_wbflush();
+ dma_cache_wback_inv((unsigned long)__va(dma_handle), size);
+/* if(direction==PCI_DMA_TODEVICE)
+ mace_inv_read_buffers();*/
}
-void pci_dma_sync_sg(struct pci_dev *hwdev, struct scatterlist *sg,
- int nelems, int direction)
+
+/*
+ * Make physical memory consistent for a set of streaming
+ * mode DMA translations after a transfer.
+ *
+ * The same as pci_dma_sync_single but for a scatter-gather list,
+ * same rules and usage.
+ */
+void pci_dma_sync_sg(struct pci_dev *hwdev,
+ struct scatterlist *sg,
+ int nelems, int direction)
{
+ int i;
if (direction == PCI_DMA_NONE)
BUG();
+ DPRINTK("pci_dma_sync_sg\n");
+ /* Make sure that gcc doesn't leave the empty loop body. */
+ for (i = 0; i < nelems; i++, sg++){
+ mips_wbflush();
+ dma_cache_wback_inv((unsigned long)__va(sg->address), sg->length);
+ }
+/* if(direction==PCI_DMA_TODEVICE)
+ mace_inv_read_buffers();*/
}
-*/
Index: ip32-pci.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips64/sgi-ip32/ip32-pci.c,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -d -r1.2 -r1.3
--- ip32-pci.c 2001/10/26 16:13:55 1.2
+++ ip32-pci.c 2001/11/28 17:13:07 1.3
@@ -221,11 +221,30 @@
pci_write_config_byte (dev, PCI_CACHE_LINE_SIZE, 0x20);
pci_write_config_byte (dev, PCI_LATENCY_TIMER, 0x30);
pci_read_config_word (dev, PCI_COMMAND, &cmd);
- cmd |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_PARITY);
+ cmd |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_SPECIAL | PCI_COMMAND_INVALIDATE | PCI_COMMAND_PARITY);
pci_write_config_word (dev, PCI_COMMAND, cmd);
pci_set_master (dev);
}
+ /*
+ * Fixup O2 PCI slot. Bad hack.
+ */
+/* devtag = pci_make_tag(0, 0, 3, 0);
+ slot = macepci_conf_read(0, devtag, PCI_COMMAND_STATUS_REG);
+ slot |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE;
+ macepci_conf_write(0, devtag, PCI_COMMAND_STATUS_REG, slot);
+
+ slot = macepci_conf_read(0, devtag, PCI_MAPREG_START);
+ if (slot == 0xffffffe1)
+ macepci_conf_write(0, devtag, PCI_MAPREG_START, 0x00001000);
+
+ slot = macepci_conf_read(0, devtag, PCI_MAPREG_START + (2 << 2));
+ if ((slot & 0xffff0000) == 0) {
+ slot += 0x00010000;
+ macepci_conf_write(0, devtag, PCI_MAPREG_START + (2 << 2),
+ 0x00000000);
+ }
+ */
#ifdef DEBUG_MACE_PCI
printk ("Triggering PCI bridge interrupt...\n");
mace_write_32 (MACEPCI_ERROR_FLAGS, MACEPCI_ERROR_INTERRUPT_TEST);
Index: ip32-reset.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips64/sgi-ip32/ip32-reset.c,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- ip32-reset.c 2001/10/26 16:13:55 1.1
+++ ip32-reset.c 2001/11/28 17:13:07 1.2
@@ -4,19 +4,21 @@
* for more details.
*
* Copyright (C) 2001 Keith M Wesolowski
+ * Copyright (C) 2001 Paul Mundt
*/
-
-#include <asm/promlib.h>
+#include <asm/sgialib.h>
-/* linux/reboot.h */
-void machine_restart (char *cmd) {
- ArcReboot (cmd);
+void machine_restart(char *cmd)
+{
+ ArcReboot();
}
-void machine_halt (void) {
+void machine_halt(void)
+{
ArcEnterInteractiveMode();
}
-void machine_power_off (void) {
- ArcPowerDown();
+void machine_power_off(void)
+{
+ machine_halt();
}
Index: ip32-setup.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips64/sgi-ip32/ip32-setup.c,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -d -r1.2 -r1.3
--- ip32-setup.c 2001/10/26 16:13:55 1.2
+++ ip32-setup.c 2001/11/28 17:13:07 1.3
@@ -27,11 +27,32 @@
unsigned long mips_io_port_base = UNCACHEDADDR (MACEPCI_HI_IO);;
-
-void __init ip32_init (int argc, char **argv, char **envp) {
- prom_meminit ();
+#ifdef CONFIG_SGI_O2MACE_ETH
+/* this is taken care of in here 'cause they say using Arc later on is problematic */
+extern char o2meth_eaddr[8];
+static inline unsigned char str2hexnum(unsigned char c)
+{
+ if (c >= '0' && c <= '9')
+ return c - '0';
+ if (c >= 'a' && c <= 'f')
+ return c - 'a' + 10;
+ return 0; /* foo */
}
+static inline void str2eaddr(unsigned char *ea, unsigned char *str)
+{
+ int i;
+ for (i = 0; i < 6; i++) {
+ unsigned char num;
+
+ if(*str == ':')
+ str++;
+ num = str2hexnum(*str++) << 4;
+ num |= (str2hexnum(*str++));
+ ea[i] = num;
+ }
+}
+#endif
void __init ip32_setup(void)
{
#ifdef CONFIG_SERIAL_CONSOLE
@@ -46,6 +67,12 @@
console_setup ("ttyS1");
else
console_setup ("ttyS0");
+ }
+#endif
+#ifdef CONFIG_SGI_O2MACE_ETH
+ {
+ char *mac=ArcGetEnvironmentVariable("eaddr");
+ str2eaddr(o2meth_eaddr, mac);
}
#endif
|
|
From: James S. <jsi...@us...> - 2001-11-28 17:10:47
|
Update of /cvsroot/linux-mips/linux/arch/mips
In directory usw-pr-cvs1:/tmp/cvs-serv6001/arch/mips
Modified Files:
config.in
Log Message:
Add a few O2 METH drivers bits.
Index: config.in
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/config.in,v
retrieving revision 1.57
retrieving revision 1.58
diff -u -d -r1.57 -r1.58
--- config.in 2001/11/27 22:51:18 1.57
+++ config.in 2001/11/28 17:10:43 1.58
@@ -108,6 +108,10 @@
define_bool CONFIG_MCA n
define_bool CONFIG_SBUS n
+if [ "$CONFIG_DECSTATION" = "y" ]; then
+ define_bool CONFIG_NONCOHERENT_IO y
+fi
+
if [ "$CONFIG_SIBYTE_SB1250" = "y" ]; then
define_bool CONFIG_NEW_IRQ y
define_bool CONFIG_PCI n
|
|
From: James S. <jsi...@us...> - 2001-11-28 17:10:47
|
Update of /cvsroot/linux-mips/linux/arch/mips64/configs In directory usw-pr-cvs1:/tmp/cvs-serv6001/arch/mips64/configs Modified Files: defconfig-ip32 Log Message: Add a few O2 METH drivers bits. Index: defconfig-ip32 =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips64/configs/defconfig-ip32,v retrieving revision 1.4 retrieving revision 1.5 diff -u -d -r1.4 -r1.5 --- defconfig-ip32 2001/11/26 17:17:26 1.4 +++ defconfig-ip32 2001/11/28 17:10:43 1.5 @@ -252,6 +252,7 @@ # Ethernet (10 or 100Mbit) # CONFIG_NET_ETHERNET=y +CONFIG_SGI_O2MACE_ETH=y # CONFIG_SUNLANCE is not set # CONFIG_HAPPYMEAL is not set # CONFIG_SUNBMAC is not set |
|
From: James S. <jsi...@us...> - 2001-11-28 17:10:47
|
Update of /cvsroot/linux-mips/linux/drivers/net
In directory usw-pr-cvs1:/tmp/cvs-serv6001/drivers/net
Modified Files:
Config.in Makefile
Log Message:
Add a few O2 METH drivers bits.
Index: Config.in
===================================================================
RCS file: /cvsroot/linux-mips/linux/drivers/net/Config.in,v
retrieving revision 1.16
retrieving revision 1.17
diff -u -d -r1.16 -r1.17
--- Config.in 2001/11/13 22:11:59 1.16
+++ Config.in 2001/11/28 17:10:43 1.17
@@ -66,6 +66,9 @@
if [ "$CONFIG_SGI_IP27" = "y" ]; then
bool ' SGI IOC3 Ethernet' CONFIG_SGI_IOC3_ETH
fi
+ if [ "$CONFIG_SGI_IP32" = "y" ]; then
+ tristate ' SGI O2 MACE Fast Ethernet support' CONFIG_SGI_O2MACE_ETH
+ fi
if [ "$CONFIG_IA64_SGI_SN1" = "y" ]; then
bool ' SGI IOC3 Ethernet' CONFIG_SGI_IOC3_ETH
fi
Index: Makefile
===================================================================
RCS file: /cvsroot/linux-mips/linux/drivers/net/Makefile,v
retrieving revision 1.9
retrieving revision 1.10
diff -u -d -r1.9 -r1.10
--- Makefile 2001/11/10 03:52:49 1.9
+++ Makefile 2001/11/28 17:10:43 1.10
@@ -155,6 +155,7 @@
obj-$(CONFIG_SUN3LANCE) += sun3lance.o
obj-$(CONFIG_DEFXX) += defxx.o
obj-$(CONFIG_SGISEEQ) += sgiseeq.o
+obj-$(CONFIG_SGI_O2MACE_ETH) += meth.o
obj-$(CONFIG_AT1700) += at1700.o
obj-$(CONFIG_FMV18X) += fmv18x.o
obj-$(CONFIG_EL1) += 3c501.o
|
|
From: James S. <jsi...@us...> - 2001-11-28 17:05:37
|
Update of /cvsroot/linux-mips/linux/include/asm-mips64
In directory usw-pr-cvs1:/tmp/cvs-serv4309/asm-mips64
Modified Files:
bcache.h
Log Message:
Match both <asm/bcache.h> variants.
Index: bcache.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips64/bcache.h,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- bcache.h 2001/10/31 18:26:52 1.1
+++ bcache.h 2001/11/28 17:05:35 1.2
@@ -11,8 +11,6 @@
#include <linux/config.h>
-#ifdef CONFIG_BOARD_SCACHE
-
/* Some R4000 / R4400 / R4600 / R5000 machines may have a non-dma-coherent,
chipset implemented caches. On machines with other CPUs the CPU does the
cache thing itself. */
@@ -25,6 +23,8 @@
extern void indy_sc_init(void);
extern void sni_pcimt_sc_init(void);
+
+#ifdef CONFIG_BOARD_SCACHE
extern struct bcache_ops *bcops;
|
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