From: Michael S. <mi...@sc...> - 2024-07-29 06:30:16
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On 29.07.24 00:24, marcello.carla wrote: > It is a possibility and has been considered. The reason that led to > prefer edge interupts to level ones is the unavoidable overhead that > comes from the doubling of NRFD and NDAC interrupts. Not huge, but not > negligible. In any case, hardware problems like a chattering interrupt > or repeated interrupts due to line reflections cannot be handled in > software. They can be handled in software, and IMHO they should be - that is part of designing robust software. When dealing with an asynchronous bus mechanism like GPIB, such stuff can happen and software needs to cope with it. The only overhead I see is that using level-triggered interrupts, I need to enable/disable the interrupts and re-program the level for each transfer. I don't know how costly those operations are, but since we are talking about a 800MHz clock CPU pushing data at something like 1MB/s, this should not be a huge problem. cu Michael |