#87 ibwait does not time out after waiting >1.5s for ibrda to complete (NI-USB-HS)

[Michael Katzmann]

NI-USB-HS driver ibwait problem.

I am using ibrda to read with the timeout disabled (TNONE). After issuing the ibrda (async read) command I loop an ibwait with the timeout set (say 300ms (T300ms)).
ibwait(GPIBdescriptor, TIMO | CMPL | END)
The ibwait times out each 300ms UNTIL a total of 1.5s elapses waiting for ibrda to complete.
ibwait then does not timeout and only returns when the read completes.
This also happens when using the same procedure with ibwrta.

I am using the HP 59401 A bus analyzer in 'slow' mode to debug the bus. This causes each HPIB command to execute at a 500ms rate.

This problem does not occur using the Agilent controller (although there is a different problem).

The attached program produces the following output (when the analyzer is in 'slow' mode, limiting the GPIB rate to 2Hz. Note that the ibwait stops timing out after 1.5 seconds. The write completes after 4.32 seconds and the read 17.31 seconds.

One approximately one in 3 or 4 times the driver does gives a InternalReceiveSetup: command failed error on read.

[maxwell ~] 😼 time ./GPIB.HP59401A-2 -c 1 -d 16
   GPIB controller ID: 1
       GPIB device ID: 16
         EOI asserted: Yes
        EOS character: No
🖊 HP8753: IDN?;
✍🏻 Write waiting for HP8753: 0.3s
✍🏻 Write waiting for HP8753: 0.6s
✍🏻 Write waiting for HP8753: 0.9s
✍🏻 Write waiting for HP8753: 1.2s
✍🏻 Write waiting for HP8753: 1.5s
🖊 HP8753: 5 / 5 bytes in 4.32s
👀 Read waiting for HP8753: 0.3s
👀 Read waiting for HP8753: 0.6s
👀 Read waiting for HP8753: 0.9s
👀 Read waiting for HP8753: 1.2s
👀 Read waiting for HP8753: 1.5s
👓 HP8753: 29 bytes (50 max) in 17.31s
IDN returns "HEWLETT PACKARD,8753C,0,4.13
"

real    0m21.643s
user    0m0.043s
sys 0m0.140s
[maxwell ~] 😼 time ./GPIB.HP59401A-2 -c 1 -d 16
   GPIB controller ID: 1
       GPIB device ID: 16
         EOI asserted: Yes
        EOS character: No
🖊 HP8753: IDN?;
✍🏻 Write waiting for HP8753: 0.3s
✍🏻 Write waiting for HP8753: 0.6s
✍🏻 Write waiting for HP8753: 0.9s
✍🏻 Write waiting for HP8753: 1.2s
✍🏻 Write waiting for HP8753: 1.5s
🖊 HP8753: 5 / 5 bytes in 4.29s
InternalReceiveSetup: command failed
👓 HP8753: 5 bytes (50 max) in 0.27s
GPIB read status/error (0x8100/0x0000)

real    0m4.575s
user    0m0.002s
sys 0m0.110s
[maxwell ~] 😼 

the HP 59401 A bus analyzer uses the following method in 'slow' mode ...

3-26. The sequence of Bus control (handshake) signals is as follows:
1. The "talker" puts data on the data lines and drives the DAV line low to indicate the data is valid.
2. The fastest "listener" accepts the data and sets NRFD low.
3. All other instruments on the Bus accept the data at their individual rates.
4. The 59401 A accepts the data and allows NDAC to go high.
5. The "talker" senses NDAC high, sets DAV high, and puts new data on the Bus.
6. Instruments on the Bus become "ready for data" (set NDAC low and NRFD high).
7. The 59401 A sets its NDAC output low and allows NRFD to go high after a 500ms delay.
8. The "talker" senses NRFD high and sets DAV low, starting the cycle over.

[DaveP]

Fixed finally here