From: Ivan K. <in...@ju...> - 2001-04-06 10:19:37
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On Thu, Apr 05, 2001 at 12:20:22PM -0600, Eric W. Biederman wrote: > The point is on the Alpha all ram is always cached, and i/o space is > completely uncached. You cannot do write-combing for video card > memory. Incorrect. Alphas have write buffers - 6x32 bytes on ev5 and 4x64 on ev6, IIRC. So alphas do write up to 32 or 64 bytes in a single pci transaction. > Memory barriers are a separate issue. On the alpha the > natural way to implement it would be in the page table fill code. > Memory barriers are o.k. but the really don't help the case when what > you want to do is read the latest value out of a pci register. You don't need memory barrier for that. "Write memory barriers" are used to ensure correct write order, and "memory barriers" are used to ensure that all pending reads/writes will complete before next read or write. Ivan. |