From: Gil B. <co...@ba...> - 2005-10-31 07:05:52
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Hello, =20 I suspect I have found the reason for the breakage I reported earlier in = the driver - but I'd be very happy if someone was confirming that my attempt wouldn't mess up my hardware before I set off to test it. =20 This addition: =20 + /* according to ATI, we should use clock 3 for acelerated mode */ + par->clk_wr_offset =3D 3; =20 comes up right after a nice piece of code that actually tries to mask clk_wr_offset: =20 + if (!(aty_ld_le32(CRTC_GEN_CNTL, par) & CRTC_EXT_DISP_EN)) + par->clk_wr_offset =3D (inb(R_GENMO) & 0x0CU) >> 2; + else + par->clk_wr_offset =3D aty_ld_8(CLOCK_CNTL, par) & 0x03U; =20 and so makes this code redundant with a static value that "seems" to = come out of nowhere. Furthermore, looking at atyfb.h, this particular register has overloaded meaning (by its comment) so it may cause the unexpected results I'm = seeing. But. these 4 lines of code replace an even bigger PLL calculation = routine, and I do not know if they are correct or are just an attempt to read the value that got "commented out" because it was not complete. =20 So I ripped out the first two lines and count on the next 4 lines to initialize clk_wr_offset. I already compiled the appropriate kernel, but since my understanding of = all the hidden subtleties of the mach64 registers is far from complete, and = my only mac is an all-in-one machine where damage to the crt by wrong = clocking will render the entire box useless, I would appreciate it if you tell me = at least what you think and if I am putting my hardware at any risk. =20 Thanks, =20 Gil Bahat, System Administrator. |