linux-fbdev-devel — linux-fbdev mailing list for project developers

[Linux-fbdev-devel] [PATCH] au1200fb: fix oops due to uninitialized fb_info.lock mutex

[Manuel L. <man...@go...>]

commit 4148df9b0f38bdd362dd91d52076926c11cbe5a9 breaks au1200fb due to
fb_info.lock now being uninitialized at the time of the
register_frambuffer call:

CPU 0 Unable to handle kernel paging request at virtual address 00000000, epc == 8038ccd4, ra == 802412d4
Call Trace:
[<8038ccd4>] __mutex_lock_slowpath+0x3c/0xe4
[<802412d4>] lock_fb_info+0x20/0x50
[<80242158>] register_framebuffer+0x264/0x2a4
[<8024f8c4>] au1200fb_drv_probe+0x308/0x444
[<80273ef8>] driver_probe_device+0xbc/0x184
[<8027402c>] __driver_attach+0x6c/0xa4
[<802736bc>] bus_for_each_dev+0x60/0xb0
[<80272e20>] bus_add_driver+0xc8/0x24c
[<802743f4>] driver_register+0xdc/0x190
[<8047d130>] au1200fb_init+0x39c/0x3cc
[<80100460>] _stext+0x60/0x1c8
[<8046f334>] kernel_init+0xc8/0x134
[<80106f64>] kernel_thread_helper+0x10/0x18

This band-aid fixes this oops.

Signed-off-by: Manuel Lauss <man...@gm...>
---
 drivers/video/au1200fb.c |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/drivers/video/au1200fb.c b/drivers/video/au1200fb.c
index 0d96f1d..293aff9 100644
--- a/drivers/video/au1200fb.c
+++ b/drivers/video/au1200fb.c
@@ -1671,6 +1671,8 @@ static int au1200fb_drv_probe(struct platform_device *dev)
 		if ((ret = au1200fb_init_fbinfo(fbdev)) < 0)
 			goto failed;

+		mutex_init(&fbdev->fb_info.lock);
+
 		/* Register new framebuffer */
 		if ((ret = register_framebuffer(&fbdev->fb_info)) < 0) {
 			print_err("cannot register new framebuffer");
--
1.6.3.3

Re: [Linux-fbdev-devel] [linux-fbdev-devel][PATCH]fb_pan_display:add x/yoffset check

[Florian T. S. <Flo...@gm...>]

Kai Jiang schrieb:
> While, I suppose when the patch is applied, it should avoid what you 
> mentioned. Following is the code applied patch.
> (And the x/yres and x/yres_virtual have fix value which are defined and 
> checked in the driver.)

That's true as my explanation described the problem with the current 
code you encountered.
I also think that your patch will fix it:

> fb_pan_display(struct fb_info *info, struct fb_var_screeninfo *var)
> {      ......
>         int xoffset = var->xoffset;                 // here transfer 
> x/yoffset to "int" type for comparison
>         int yoffset = var->yoffset;
>        ......
>         if (err || !info->fbops->fb_pan_display ||
>             var->yoffset + yres > info->var.yres_virtual ||        
>             var->xoffset + info->var.xres > info->var.xres_virtual ||    
>             xoffset < 0 || yoffset < 0)             // insure the 
> x/yoffset is large than 0. I think this line can avoid what you concerned.
>                 return -EINVAL;
>        ......
> }

I only wanted to highlight, that as far as I can see the same behavior 
you want to archive can be archived by changing the current code to:

fb_pan_display(struct fb_info *info, struct fb_var_screeninfo *var)
{
        ......
         if (err || !info->fbops->fb_pan_display ||
             var->yoffset > info->var.yres_virtual - yres ||
             var->xoffset > info->var.xres_virtual - info->var.xres)
                 return -EINVAL;
        ......
}

> Do you think so? I am happy to know your comments.

I think your patch is fine as it fixes the accepted invalid value.
There are only a few small disadvantages:
- its a bit odd to convert unsigned to signed value to check its validity
- it adds 2 extra compares
- although not practically relevant, as virtual resolutions>2^31 would 
require an enormous amount of video memory, it would be too strict on 
this side (by checking for signedness in u32 you half the range of 
allowed numbers)

I first got Ville Syrjälä second email a bit wrong (sorry for that). He 
suggests to change your check to an overflow check:

fb_pan_display(struct fb_info *info, struct fb_var_screeninfo *var)
{
        ......
         if (err || !info->fbops->fb_pan_display ||
             var->yoffset + yres > info->var.yres_virtual ||
             var->xoffset + info->var.xres > info->var.xres_virtual ||
             var->yoffset + yres < yres ||
             var->xoffset + info->var.xres < info->var.xres)
                 return -EINVAL;
      ......
}

while my approach is to prevent the overflow.
I hope that after my last e-mail you understand, that all 3 suggested 
approaches (yours, mine, Ville Syrjälä) should fix (at least in my 
opinion) your problem. (as negative values don't exist in unsigned types 
or are actually very large positive integers)


Greetings,

Florian Tobias Schandinat

Re: [Linux-fbdev-devel] [linux-fbdev-devel][PATCH]fb_pan_display:add x/yoffset check

[Kai J. <b1...@fr...>]

Florian Tobias Schandinat wrote:
> Kai Jiang schrieb:
>> Florian Tobias Schandinat wrote:
>>> That's true, but the problem lies in the current implementation 
>>> first adding the resolution, which results in small negative [0 to 
>>> -resolution] values (=large positives) being accepted as they 
>>> overflow during add and become small positive values.
>>> I'd recommend changing
>>>
>>> var->yoffset + yres > info->var.yres_virtual ||
>>> var->xoffset + info->var.xres > info->var.xres_virtual
>>>
>>> to
>>>
>>> var->yoffset > info->var.yres_virtual - yres ||
>>> var->xoffset > info->var.xres_virtual - info->var.xres
>>>
>> I am not sure why do we have these change. Could you give a detail 
>> description or an example?
> It starts with "-1" in an u32 being represented as "0xFFFFFFFF", which 
> would be caught by ">". The problem in the current code is it first 
> adds the resolution before comparison and this causes an overflow.
> Let's say the virtual resolution matches the real resolution:
> yoffset + yres > yres
> There the left side is evaluated at first:
> (yoffset + yres)
> You accept everything that is <=yres. In classical mathematics you 
> would say yoffset has to be 0, but unfortunately this codes accept 
> many more as it can overflow. You get
> yoffset = -1:    (yres-1) > yres
> offset = -yres:    0 > yres
> So as you noticed, the current code will not just accept 0 as yoffset, 
> but the whole range [-yres..0]. This can be fixed by moving the 
> calculation to the right side, where we have trusted values, that do 
> not cause an overflow.
Florian Tobias Schandinat,
Thank you for your quick detail reply.
While, I suppose when the patch is applied, it should avoid what you 
mentioned. Following is the code applied patch.
(And the x/yres and x/yres_virtual have fix value which are defined and 
checked in the driver.)

fb_pan_display(struct fb_info *info, struct fb_var_screeninfo *var)
{      ......
        int xoffset = var->xoffset;                 // here transfer 
x/yoffset to "int" type for comparison
        int yoffset = var->yoffset;
       ......
        if (err || !info->fbops->fb_pan_display ||
            var->yoffset + yres > info->var.yres_virtual ||        
            var->xoffset + info->var.xres > info->var.xres_virtual ||    
            xoffset < 0 || yoffset < 0)             // insure the 
x/yoffset is large than 0. I think this line can avoid what you concerned.
                return -EINVAL;
       ......
}

Do you think so? I am happy to know your comments.

Best Regards,

Kai Jiang

Re: [Linux-fbdev-devel] [linux-fbdev-devel][PATCH]fb_pan_display:add x/yoffset check

[Florian T. S. <Flo...@gm...>]

Kai Jiang schrieb:
> Florian Tobias Schandinat wrote:
>> Ville Syrjälä schrieb:
>>>> So here we have to check the whether the x/yoffset is smaller than 
>>>> zero. If the offset is smaller than zero, in the driver, we should 
>>>> not move the virtual screen any more.
>>>
>>> Checking for overflow will catch you buggy application's negative
>>> values too.
>>
>> That's true, but the problem lies in the current implementation first 
>> adding the resolution, which results in small negative [0 to 
>> -resolution] values (=large positives) being accepted as they overflow 
>> during add and become small positive values.
>> I'd recommend changing
>>
>> var->yoffset + yres > info->var.yres_virtual ||
>> var->xoffset + info->var.xres > info->var.xres_virtual
>>
>> to
>>
>> var->yoffset > info->var.yres_virtual - yres ||
>> var->xoffset > info->var.xres_virtual - info->var.xres
>>
> I am not sure why do we have these change. Could you give a detail 
> description or an example?

A small program to illustrate it:

#include <stdio.h>
int main()
{
         unsigned int    a = -1;
         printf( "%X\n%X\n", a, a+1 );
         return 0;
}

It starts with "-1" in an u32 being represented as "0xFFFFFFFF", which 
would be caught by ">". The problem in the current code is it first adds 
the resolution before comparison and this causes an overflow.
Let's say the virtual resolution matches the real resolution:
yoffset + yres > yres
There the left side is evaluated at first:
(yoffset + yres)
You accept everything that is <=yres. In classical mathematics you would 
say yoffset has to be 0, but unfortunately this codes accept many more 
as it can overflow. You get
yoffset = -1:	(yres-1) > yres
offset = -yres:	0 > yres
So as you noticed, the current code will not just accept 0 as yoffset, 
but the whole range [-yres..0]. This can be fixed by moving the 
calculation to the right side, where we have trusted values, that do not 
cause an overflow.

Hope this helps.


Greetings,

Florian Tobias Schandinat

Re: [Linux-fbdev-devel] [PATCH 5/5] at91/atmel_lcdfb: add at91sam9g10 support to atmel LCD driver

[Nicolas F. <nic...@at...>]

Hi,

Nicolas Ferre :
> From: Hong Xu <ho...@at...>
> 
> Modify atmel LCD driver: atmel_lcdfb for at91sam9g10.  This add a clock
> management equivalent to at91sam9261.

Can we consider an inclusion in linux-fbdev ?

> Signed-off-by: Hong Xu <ho...@at...>
> Signed-off-by: Nicolas Ferre <nic...@at...>

Andrew Victor added his:
Acked-by: Andrew Victor <li...@ma...>

> ---
>  drivers/video/Kconfig           |    4 ++--
>  drivers/video/atmel_lcdfb.c     |    6 ++++--
>  drivers/video/backlight/Kconfig |    2 +-
>  3 files changed, 7 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
> index 5152168..2dbede4 100644
> --- a/drivers/video/Kconfig
> +++ b/drivers/video/Kconfig
> @@ -933,7 +933,7 @@ config FB_S1D13XXX
>  
>  config FB_ATMEL
>  	tristate "AT91/AT32 LCD Controller support"
> -	depends on FB && (ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || ARCH_AT91SAM9G45 || ARCH_AT91CAP9 || AVR32)
> +	depends on FB && (ARCH_AT91SAM9261 || ARCH_AT91SAM9G10 || ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || ARCH_AT91SAM9G45 || ARCH_AT91CAP9 || AVR32)
>  	select FB_CFB_FILLRECT
>  	select FB_CFB_COPYAREA
>  	select FB_CFB_IMAGEBLIT
> @@ -949,7 +949,7 @@ config FB_INTSRAM
>  
>  config FB_ATMEL_STN
>  	bool "Use a STN display with AT91/AT32 LCD Controller"
> -	depends on FB_ATMEL && MACH_AT91SAM9261EK
> +	depends on FB_ATMEL && (MACH_AT91SAM9261EK || MACH_AT91SAM9G10EK)
>  	default n
>  	help
>  	  Say Y if you want to connect a STN LCD display to the AT91/AT32 LCD
> diff --git a/drivers/video/atmel_lcdfb.c b/drivers/video/atmel_lcdfb.c
> index 9a577a8..fc10ac5 100644
> --- a/drivers/video/atmel_lcdfb.c
> +++ b/drivers/video/atmel_lcdfb.c
> @@ -188,7 +188,8 @@ static unsigned long compute_hozval(unsigned long xres, unsigned long lcdcon2)
>  {
>  	unsigned long value;
>  
> -	if (!(cpu_is_at91sam9261() || cpu_is_at32ap7000()))
> +	if (!(cpu_is_at91sam9261() || cpu_is_at91sam9g10()
> +		|| cpu_is_at32ap7000()))
>  		return xres;
>  
>  	value = xres;
> @@ -827,7 +828,8 @@ static int __init atmel_lcdfb_probe(struct platform_device *pdev)
>  	info->fix = atmel_lcdfb_fix;
>  
>  	/* Enable LCDC Clocks */
> -	if (cpu_is_at91sam9261() || cpu_is_at32ap7000()) {
> +	if (cpu_is_at91sam9261() || cpu_is_at91sam9g10()
> +	 || cpu_is_at32ap7000()) {
>  		sinfo->bus_clk = clk_get(dev, "hck1");
>  		if (IS_ERR(sinfo->bus_clk)) {
>  			ret = PTR_ERR(sinfo->bus_clk);
> diff --git a/drivers/video/backlight/Kconfig b/drivers/video/backlight/Kconfig
> index f9d19be..90861cd 100644
> --- a/drivers/video/backlight/Kconfig
> +++ b/drivers/video/backlight/Kconfig
> @@ -110,7 +110,7 @@ config BACKLIGHT_CLASS_DEVICE
>  config BACKLIGHT_ATMEL_LCDC
>  	bool "Atmel LCDC Contrast-as-Backlight control"
>  	depends on BACKLIGHT_CLASS_DEVICE && FB_ATMEL
> -	default y if MACH_SAM9261EK || MACH_SAM9263EK
> +	default y if MACH_SAM9261EK || MACH_SAM9G10EK || MACH_SAM9263EK
>  	help
>  	  This provides a backlight control internal to the Atmel LCDC
>  	  driver.  If the LCD "contrast control" on your board is wired


Best regards,
-- 
Nicolas Ferre

Re: [Linux-fbdev-devel] [PATCH v4] Frame Buffer driver for TI DA8xx/OMAP-L1xx

[Rajashekhara, S. <sud...@ti...>]

On Fri, Jul 03, 2009 at 01:14:21, Krzysztof Helt wrote:
> On Tue, 30 Jun 2009 01:50:13 -0400
> "Rajashekhara, Sudhakar" <sud...@ti...> wrote:
> 
> > Adds LCD controller (LCDC) driver for TI's DA8xx/OMAP-L1xx architecture.
> > LCDC specifications can be found at http://www.ti.com/litv/pdf/sprufm0a.
> > 
> > LCDC on DA8xx consists of two independent controllers, the Raster Controller
> > and the LCD Interface Display Driver (LIDD) controller. LIDD further supports
> > character and graphic displays.
> > 
> > This patch adds support for the graphic display (Sharp LQ035Q3DG01) found on
> > the DA830 based EVM. The EVM details can be found at:
> > http://support.spectrumdigital.com/boards/dskda830/revc/.
> > 
> > Signed-off-by: Sudhakar Rajashekhara <sud...@ti...>
> > Signed-off-by: Pavel Kiryukhin <pki...@ru...>
> > Signed-off-by: Steve Chen <sc...@mv...>
> > ---
> >  Since the previous version, fb_setcolreg function has been modified for
> >  8 and 16 bit modes.
> > 
> >  drivers/video/Kconfig    |   11 +
> >  drivers/video/Makefile   |    1 +
> >  drivers/video/da8xx-fb.c |  897 ++++++++++++++++++++++++++++++++++++++++++++++
> >  include/video/da8xx-fb.h |  106 ++++++
> >  4 files changed, 1015 insertions(+), 0 deletions(-)
> >  create mode 100644 drivers/video/da8xx-fb.c
> >  create mode 100644 include/video/da8xx-fb.h
> > 
> 
> > diff --git a/drivers/video/da8xx-fb.c b/drivers/video/da8xx-fb.c
> > new file mode 100644
> > index 0000000..3135234
> > --- /dev/null
> > +++ b/drivers/video/da8xx-fb.c
> > @@ -0,0 +1,897 @@
> 
> (...)
> 
> > +
> > +static int fb_setcolreg(unsigned regno, unsigned red, unsigned green,
> > +			      unsigned blue, unsigned transp,
> > +			      struct fb_info *info)
> > +{
> > +	struct da8xx_fb_par *par = info->par;
> > +	unsigned short *palette = (unsigned short *)par->v_palette_base;
> > +	u_short pal;
> > +
> > +	if (regno > 255)
> > +		return 1;
> > +
> > +	if (info->fix.visual == FB_VISUAL_DIRECTCOLOR)
> > +		return 1;
> > +
> > +	if (info->var.bits_per_pixel == 8) {
> > +		red >>= 4;
> > +		green >>= 4;
> > +		blue >>= 4;
> > +
> > +		pal = (red & 0x0f00);
> > +		pal |= (green & 0x00f0);
> > +		pal |= (blue & 0x000f);
> > +
> > +		palette[regno] = pal;
> > +
> 
> I am losing my patience. The shift value for the red component is right (probably as I do 
> not know the format of this palette registers). It is however almost surely wrong for other
> componets. Just put this simple example value to get almost white color:
> red = 0xf000;
> green = 0xf000;
> blue = 0xf000;
> 
> The resulting palette value would be 0xf00. Is it close to white on your controller?
> 
> Another example: blue
> red = 0;
> green = 0;
> blue = 0xff00;
> 
> The result : 0x0. It does not differ from the value for black colour (rgb = 0/0/0).
> 

I have corrected this mistake in the v5 version of the patch which I have submitted.

Thanks,
Sudhakar

[Linux-fbdev-devel] [PATCH v5] Frame Buffer driver for TI DA8xx/OMAP-L1xx

[Rajashekhara, S. <sud...@ti...>]

Adds LCD controller (LCDC) driver for TI's DA8xx/OMAP-L1xx architecture.
LCDC specifications can be found at http://www.ti.com/litv/pdf/sprufm0a.

LCDC on DA8xx consists of two independent controllers, the Raster Controller
and the LCD Interface Display Driver (LIDD) controller. LIDD further supports
character and graphic displays.

This patch adds support for the graphic display (Sharp LQ035Q3DG01) found on
the DA830 based EVM. The EVM details can be found at:
http://support.spectrumdigital.com/boards/dskda830/revc/.

Signed-off-by: Sudhakar Rajashekhara <sud...@ti...>
Signed-off-by: Pavel Kiryukhin <pki...@ru...>
Signed-off-by: Steve Chen <sc...@mv...>
---
 This patch applies to Linus's Kernel tree.

 Since the previous version, fb_setcolreg function has been modified for
 8 bit mode.

 drivers/video/Kconfig    |   11 +
 drivers/video/Makefile   |    1 +
 drivers/video/da8xx-fb.c |  900 ++++++++++++++++++++++++++++++++++++++++++++++
 include/video/da8xx-fb.h |  106 ++++++
 4 files changed, 1018 insertions(+), 0 deletions(-)
 create mode 100644 drivers/video/da8xx-fb.c
 create mode 100644 include/video/da8xx-fb.h

diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 8afcf08..d048b7e 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -2038,6 +2038,17 @@ config FB_SH7760
 	  and 8, 15 or 16 bpp color; 90 degrees clockwise display rotation for
 	  panels <= 320 pixel horizontal resolution.
 
+config FB_DA8XX
+        tristate "DA8xx/OMAP-L1xx Framebuffer support"
+        depends on FB && ARCH_DAVINCI_DA830
+	select FB_CFB_FILLRECT
+	select FB_CFB_COPYAREA
+	select FB_CFB_IMAGEBLIT
+	---help---
+          This is the frame buffer device driver for the TI LCD controller
+	  found on DA8xx/OMAP-L1xx SoCs.
+          If unsure, say N.
+
 config FB_VIRTUAL
 	tristate "Virtual Frame Buffer support (ONLY FOR TESTING!)"
 	depends on FB
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 01a819f..288d9b0 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -136,6 +136,7 @@ obj-$(CONFIG_FB_OF)               += offb.o
 obj-$(CONFIG_FB_BF54X_LQ043)	  += bf54x-lq043fb.o
 obj-$(CONFIG_FB_BFIN_T350MCQB)	  += bfin-t350mcqb-fb.o
 obj-$(CONFIG_FB_MX3)		  += mx3fb.o
+obj-$(CONFIG_FB_DA8XX)		  += da8xx-fb.o
 
 # the test framebuffer is last
 obj-$(CONFIG_FB_VIRTUAL)          += vfb.o
diff --git a/drivers/video/da8xx-fb.c b/drivers/video/da8xx-fb.c
new file mode 100644
index 0000000..4b9d80b
--- /dev/null
+++ b/drivers/video/da8xx-fb.c
@@ -0,0 +1,900 @@
+/*
+ * Copyright (C) 2008-2009 MontaVista Software Inc.
+ * Copyright (C) 2008-2009 Texas Instruments Inc
+ *
+ * Based on the LCD driver for TI Avalanche processors written by
+ * Ajay Singh and Shalom Hai.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option)any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/fb.h>
+#include <linux/dma-mapping.h>
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <linux/uaccess.h>
+#include <linux/device.h>
+#include <linux/interrupt.h>
+#include <linux/clk.h>
+#include <video/da8xx-fb.h>
+
+#define DRIVER_NAME "da8xx_lcdc"
+
+/* LCD Status Register */
+#define LCD_END_OF_FRAME0		BIT(8)
+#define LCD_FIFO_UNDERFLOW		BIT(5)
+#define LCD_SYNC_LOST			BIT(2)
+
+/* LCD DMA Control Register */
+#define LCD_DMA_BURST_SIZE(x)		((x) << 4)
+#define LCD_DMA_BURST_1			0x0
+#define LCD_DMA_BURST_2			0x1
+#define LCD_DMA_BURST_4			0x2
+#define LCD_DMA_BURST_8			0x3
+#define LCD_DMA_BURST_16		0x4
+#define LCD_END_OF_FRAME_INT_ENA	BIT(2)
+#define LCD_DUAL_FRAME_BUFFER_ENABLE	BIT(0)
+
+/* LCD Control Register */
+#define LCD_CLK_DIVISOR(x)		((x) << 8)
+#define LCD_RASTER_MODE			0x01
+
+/* LCD Raster Control Register */
+#define LCD_PALETTE_LOAD_MODE(x)	((x) << 20)
+#define PALETTE_AND_DATA		0x00
+#define PALETTE_ONLY			0x01
+
+#define LCD_MONO_8BIT_MODE		BIT(9)
+#define LCD_RASTER_ORDER		BIT(8)
+#define LCD_TFT_MODE			BIT(7)
+#define LCD_UNDERFLOW_INT_ENA		BIT(6)
+#define LCD_MONOCHROME_MODE		BIT(1)
+#define LCD_RASTER_ENABLE		BIT(0)
+#define LCD_TFT_ALT_ENABLE		BIT(23)
+#define LCD_STN_565_ENABLE		BIT(24)
+
+/* LCD Raster Timing 2 Register */
+#define LCD_AC_BIAS_TRANSITIONS_PER_INT(x)	((x) << 16)
+#define LCD_AC_BIAS_FREQUENCY(x)		((x) << 8)
+#define LCD_SYNC_CTRL				BIT(25)
+#define LCD_SYNC_EDGE				BIT(24)
+#define LCD_INVERT_PIXEL_CLOCK			BIT(22)
+#define LCD_INVERT_LINE_CLOCK			BIT(21)
+#define LCD_INVERT_FRAME_CLOCK			BIT(20)
+
+/* LCD Block */
+#define  LCD_CTRL_REG				0x4
+#define  LCD_STAT_REG				0x8
+#define  LCD_RASTER_CTRL_REG			0x28
+#define  LCD_RASTER_TIMING_0_REG		0x2C
+#define  LCD_RASTER_TIMING_1_REG		0x30
+#define  LCD_RASTER_TIMING_2_REG		0x34
+#define  LCD_DMA_CTRL_REG			0x40
+#define  LCD_DMA_FRM_BUF_BASE_ADDR_0_REG	0x44
+#define  LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG	0x48
+
+#define WSI_TIMEOUT	50
+#define PALETTE_SIZE	256
+#define LEFT_MARGIN	64
+#define RIGHT_MARGIN	64
+#define UPPER_MARGIN	32
+#define LOWER_MARGIN	32
+
+static resource_size_t da8xx_fb_reg_base;
+
+static inline unsigned int lcdc_read(unsigned int addr)
+{
+	return (unsigned int)__raw_readl(da8xx_fb_reg_base + (addr));
+}
+
+static inline void lcdc_write(unsigned int val, unsigned int addr)
+{
+	__raw_writel(val, da8xx_fb_reg_base + (addr));
+}
+
+struct da8xx_fb_par {
+	wait_queue_head_t da8xx_wq;
+	resource_size_t p_palette_base;
+	unsigned char *v_palette_base;
+	struct clk *lcdc_clk;
+	unsigned int irq;
+	unsigned short pseudo_palette[16];
+	unsigned int databuf_sz;
+	unsigned int palette_sz;
+};
+
+/* Variable Screen Information */
+static struct fb_var_screeninfo da8xx_fb_var __devinitdata = {
+	.xoffset = 0,
+	.yoffset = 0,
+	.transp = {0, 0, 0},
+	.nonstd = 0,
+	.activate = 0,
+	.height = -1,
+	.width = -1,
+	.pixclock = 46666,	/* 46us - AUO display */
+	.accel_flags = 0,
+	.left_margin = LEFT_MARGIN,
+	.right_margin = RIGHT_MARGIN,
+	.upper_margin = UPPER_MARGIN,
+	.lower_margin = LOWER_MARGIN,
+	.sync = 0,
+	.vmode = FB_VMODE_NONINTERLACED
+};
+
+static struct fb_fix_screeninfo da8xx_fb_fix __devinitdata = {
+	.id = "DA8xx FB Drv",
+	.type = FB_TYPE_PACKED_PIXELS,
+	.type_aux = 0,
+	.visual = FB_VISUAL_PSEUDOCOLOR,
+	.xpanstep = 1,
+	.ypanstep = 1,
+	.ywrapstep = 1,
+	.accel = FB_ACCEL_NONE
+};
+
+struct da8xx_panel {
+	const char	name[25];	/* Full name <vendor>_<model> */
+	unsigned short	width;
+	unsigned short	height;
+	int		hfp;		/* Horizontal front porch */
+	int		hbp;		/* Horizontal back porch */
+	int		hsw;		/* Horizontal Sync Pulse Width */
+	int		vfp;		/* Vertical front porch */
+	int		vbp;		/* Vertical back porch */
+	int		vsw;		/* Vertical Sync Pulse Width */
+	int		pxl_clk;	/* Pixel clock */
+};
+
+static struct da8xx_panel known_lcd_panels[] = {
+	/* Sharp LCD035Q3DG01 */
+	[0] = {
+		.name = "Sharp_LCD035Q3DG01",
+		.width = 320,
+		.height = 240,
+		.hfp = 8,
+		.hbp = 6,
+		.hsw = 0,
+		.vfp = 2,
+		.vbp = 2,
+		.vsw = 0,
+		.pxl_clk = 0x10,
+	},
+	/* Sharp LK043T1DG01 */
+	[1] = {
+		.name = "Sharp_LK043T1DG01",
+		.width = 480,
+		.height = 272,
+		.hfp = 2,
+		.hbp = 2,
+		.hsw = 41,
+		.vfp = 2,
+		.vbp = 2,
+		.vsw = 10,
+		.pxl_clk = 0x12,
+	},
+};
+
+/* Disable the Raster Engine of the LCD Controller */
+static int lcd_disable_raster(struct da8xx_fb_par *par)
+{
+	int ret = 0;
+	u32 reg;
+
+	reg = lcdc_read(LCD_RASTER_CTRL_REG);
+	if (reg & LCD_RASTER_ENABLE) {
+		lcdc_write(reg & ~LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG);
+		ret = wait_event_interruptible_timeout(par->da8xx_wq,
+						!lcdc_read(LCD_STAT_REG) &
+						LCD_END_OF_FRAME0, WSI_TIMEOUT);
+	}
+
+	if (ret < 0)
+		return ret;
+	if (ret == 0)
+		return -ETIMEDOUT;
+
+	return 0;
+}
+
+static void lcd_blit(int load_mode, struct da8xx_fb_par *par)
+{
+	u32 tmp = par->p_palette_base + par->databuf_sz - 4;
+	u32 reg;
+
+	/* Update the databuf in the hw. */
+	lcdc_write(par->p_palette_base, LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
+	lcdc_write(tmp, LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
+
+	/* Start the DMA. */
+	reg = lcdc_read(LCD_RASTER_CTRL_REG);
+	reg &= ~(3 << 20);
+	if (load_mode == LOAD_DATA)
+		reg |= LCD_PALETTE_LOAD_MODE(PALETTE_AND_DATA);
+	else if (load_mode == LOAD_PALETTE)
+		reg |= LCD_PALETTE_LOAD_MODE(PALETTE_ONLY);
+
+	lcdc_write(reg, LCD_RASTER_CTRL_REG);
+}
+
+/* Configure the Burst Size of DMA */
+static int lcd_cfg_dma(int burst_size)
+{
+	u32 reg;
+
+	reg = lcdc_read(LCD_DMA_CTRL_REG) & 0x00000001;
+	switch (burst_size) {
+	case 1:
+		reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_1);
+		break;
+	case 2:
+		reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_2);
+		break;
+	case 4:
+		reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_4);
+		break;
+	case 8:
+		reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_8);
+		break;
+	case 16:
+		reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_16);
+		break;
+	default:
+		return -EINVAL;
+	}
+	lcdc_write(reg | LCD_END_OF_FRAME_INT_ENA, LCD_DMA_CTRL_REG);
+
+	return 0;
+}
+
+static void lcd_cfg_ac_bias(int period, int transitions_per_int)
+{
+	u32 reg;
+
+	/* Set the AC Bias Period and Number of Transisitons per Interrupt */
+	reg = lcdc_read(LCD_RASTER_TIMING_2_REG) & 0xFFF00000;
+	reg |= LCD_AC_BIAS_FREQUENCY(period) |
+		LCD_AC_BIAS_TRANSITIONS_PER_INT(transitions_per_int);
+	lcdc_write(reg, LCD_RASTER_TIMING_2_REG);
+}
+
+static void lcd_cfg_horizontal_sync(int back_porch, int pulse_width,
+		int front_porch)
+{
+	u32 reg;
+
+	reg = lcdc_read(LCD_RASTER_TIMING_0_REG) & 0xf;
+	reg |= ((back_porch & 0xff) << 24)
+	    | ((front_porch & 0xff) << 16)
+	    | ((pulse_width & 0x3f) << 10);
+	lcdc_write(reg, LCD_RASTER_TIMING_0_REG);
+}
+
+static void lcd_cfg_vertical_sync(int back_porch, int pulse_width,
+		int front_porch)
+{
+	u32 reg;
+
+	reg = lcdc_read(LCD_RASTER_TIMING_1_REG) & 0x3ff;
+	reg |= ((back_porch & 0xff) << 24)
+	    | ((front_porch & 0xff) << 16)
+	    | ((pulse_width & 0x3f) << 10);
+	lcdc_write(reg, LCD_RASTER_TIMING_1_REG);
+}
+
+static int lcd_cfg_display(const struct lcd_ctrl_config *cfg)
+{
+	u32 reg;
+
+	reg = lcdc_read(LCD_RASTER_CTRL_REG) & ~(LCD_TFT_MODE |
+						LCD_MONO_8BIT_MODE |
+						LCD_MONOCHROME_MODE);
+
+	switch (cfg->p_disp_panel->panel_shade) {
+	case MONOCHROME:
+		reg |= LCD_MONOCHROME_MODE;
+		if (cfg->mono_8bit_mode)
+			reg |= LCD_MONO_8BIT_MODE;
+		break;
+	case COLOR_ACTIVE:
+		reg |= LCD_TFT_MODE;
+		if (cfg->tft_alt_mode)
+			reg |= LCD_TFT_ALT_ENABLE;
+		break;
+
+	case COLOR_PASSIVE:
+		if (cfg->stn_565_mode)
+			reg |= LCD_STN_565_ENABLE;
+		break;
+
+	default:
+		return -EINVAL;
+	}
+
+	/* enable additional interrupts here */
+	reg |= LCD_UNDERFLOW_INT_ENA;
+
+	lcdc_write(reg, LCD_RASTER_CTRL_REG);
+
+	reg = lcdc_read(LCD_RASTER_TIMING_2_REG);
+
+	if (cfg->sync_ctrl)
+		reg |= LCD_SYNC_CTRL;
+	else
+		reg &= ~LCD_SYNC_CTRL;
+
+	if (cfg->sync_edge)
+		reg |= LCD_SYNC_EDGE;
+	else
+		reg &= ~LCD_SYNC_EDGE;
+
+	if (cfg->invert_pxl_clock)
+		reg |= LCD_INVERT_PIXEL_CLOCK;
+	else
+		reg &= ~LCD_INVERT_PIXEL_CLOCK;
+
+	if (cfg->invert_line_clock)
+		reg |= LCD_INVERT_LINE_CLOCK;
+	else
+		reg &= ~LCD_INVERT_LINE_CLOCK;
+
+	if (cfg->invert_frm_clock)
+		reg |= LCD_INVERT_FRAME_CLOCK;
+	else
+		reg &= ~LCD_INVERT_FRAME_CLOCK;
+
+	lcdc_write(reg, LCD_RASTER_TIMING_2_REG);
+
+	return 0;
+}
+
+static int lcd_cfg_frame_buffer(struct da8xx_fb_par *par, u32 width, u32 height,
+		u32 bpp, u32 raster_order)
+{
+	u32 bpl, reg;
+
+	/* Disable Dual Frame Buffer. */
+	reg = lcdc_read(LCD_DMA_CTRL_REG);
+	lcdc_write(reg & ~LCD_DUAL_FRAME_BUFFER_ENABLE,
+						LCD_DMA_CTRL_REG);
+	/* Set the Panel Width */
+	/* Pixels per line = (PPL + 1)*16 */
+	/*0x3F in bits 4..9 gives max horisontal resolution = 1024 pixels*/
+	width &= 0x3f0;
+	reg = lcdc_read(LCD_RASTER_TIMING_0_REG);
+	reg &= 0xfffffc00;
+	reg |= ((width >> 4) - 1) << 4;
+	lcdc_write(reg, LCD_RASTER_TIMING_0_REG);
+
+	/* Set the Panel Height */
+	reg = lcdc_read(LCD_RASTER_TIMING_1_REG);
+	reg = ((height - 1) & 0x3ff) | (reg & 0xfffffc00);
+	lcdc_write(reg, LCD_RASTER_TIMING_1_REG);
+
+	/* Set the Raster Order of the Frame Buffer */
+	reg = lcdc_read(LCD_RASTER_CTRL_REG) & ~(1 << 8);
+	if (raster_order)
+		reg |= LCD_RASTER_ORDER;
+	lcdc_write(reg, LCD_RASTER_CTRL_REG);
+
+	switch (bpp) {
+	case 1:
+	case 2:
+	case 4:
+	case 16:
+		par->palette_sz = 16 * 2;
+		break;
+
+	case 8:
+		par->palette_sz = 256 * 2;
+		break;
+
+	default:
+		return -EINVAL;
+	}
+
+	bpl = width * bpp / 8;
+	par->databuf_sz = height * bpl + par->palette_sz;
+
+	return 0;
+}
+
+static int fb_setcolreg(unsigned regno, unsigned red, unsigned green,
+			      unsigned blue, unsigned transp,
+			      struct fb_info *info)
+{
+	struct da8xx_fb_par *par = info->par;
+	unsigned short *palette = (unsigned short *)par->v_palette_base;
+	u_short pal;
+
+	if (regno > 255)
+		return 1;
+
+	if (info->fix.visual == FB_VISUAL_DIRECTCOLOR)
+		return 1;
+
+	if (info->var.bits_per_pixel == 8) {
+		red >>= 4;
+		green >>= 8;
+		blue >>= 12;
+
+		pal = (red & 0x0f00);
+		pal |= (green & 0x00f0);
+		pal |= (blue & 0x000f);
+
+		palette[regno] = pal;
+
+	} else if ((info->var.bits_per_pixel == 16) && regno < 16) {
+		red >>= (16 - info->var.red.length);
+		red <<= info->var.red.offset;
+
+		green >>= (16 - info->var.green.length);
+		green <<= info->var.green.offset;
+
+		blue >>= (16 - info->var.blue.length);
+		blue <<= info->var.blue.offset;
+
+		par->pseudo_palette[regno] = red | green | blue;
+
+		palette[0] = 0x4000;
+	}
+
+	return 0;
+}
+
+static int lcd_reset(struct da8xx_fb_par *par)
+{
+	int ret = 0;
+
+	/* Disable the Raster if previously Enabled */
+	if (lcdc_read(LCD_RASTER_CTRL_REG) & LCD_RASTER_ENABLE)
+		ret = lcd_disable_raster(par);
+
+	/* DMA has to be disabled */
+	lcdc_write(0, LCD_DMA_CTRL_REG);
+	lcdc_write(0, LCD_RASTER_CTRL_REG);
+
+	return ret;
+}
+
+static int lcd_init(struct da8xx_fb_par *par, const struct lcd_ctrl_config *cfg,
+		struct da8xx_panel *panel)
+{
+	u32 bpp, ret = 0;
+
+	ret = lcd_reset(par);
+	if (ret != 0)
+		return ret;
+
+	/* Configure the LCD clock divisor. */
+	lcdc_write(LCD_CLK_DIVISOR(panel->pxl_clk) |
+			(LCD_RASTER_MODE & 0x1), LCD_CTRL_REG);
+
+	/* Configure the DMA burst size. */
+	ret = lcd_cfg_dma(cfg->dma_burst_sz);
+	if (ret < 0)
+		return ret;
+
+	/* Configure the AC bias properties. */
+	lcd_cfg_ac_bias(cfg->ac_bias, cfg->ac_bias_intrpt);
+
+	/* Configure the vertical and horizontal sync properties. */
+	lcd_cfg_vertical_sync(panel->vbp, panel->vsw, panel->vfp);
+	lcd_cfg_horizontal_sync(panel->hbp, panel->hsw, panel->hfp);
+
+	/* Configure for disply */
+	ret = lcd_cfg_display(cfg);
+	if (ret < 0)
+		return ret;
+
+	if (QVGA != cfg->p_disp_panel->panel_type)
+		return -EINVAL;
+
+	if (cfg->bpp <= cfg->p_disp_panel->max_bpp &&
+	    cfg->bpp >= cfg->p_disp_panel->min_bpp)
+		bpp = cfg->bpp;
+	else
+		bpp = cfg->p_disp_panel->max_bpp;
+	if (bpp == 12)
+		bpp = 16;
+	ret = lcd_cfg_frame_buffer(par, (unsigned int)panel->width,
+				(unsigned int)panel->height, bpp,
+				cfg->raster_order);
+	if (ret < 0)
+		return ret;
+
+	/* Configure FDD */
+	lcdc_write((lcdc_read(LCD_RASTER_CTRL_REG) & 0xfff00fff) |
+		       (cfg->fdd << 12), LCD_RASTER_CTRL_REG);
+
+	return 0;
+}
+
+static irqreturn_t lcdc_irq_handler(int irq, void *arg)
+{
+	u32 stat = lcdc_read(LCD_STAT_REG);
+	struct da8xx_fb_par *par = arg;
+	u32 reg;
+
+	if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) {
+		reg = lcdc_read(LCD_RASTER_CTRL_REG);
+		lcdc_write(reg & ~LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG);
+		lcdc_write(stat, LCD_STAT_REG);
+		lcdc_write(reg | LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG);
+	} else
+		lcdc_write(stat, LCD_STAT_REG);
+
+	wake_up_interruptible(&par->da8xx_wq);
+	return IRQ_HANDLED;
+}
+
+static int fb_check_var(struct fb_var_screeninfo *var,
+			struct fb_info *info)
+{
+	int err = 0;
+
+	switch (var->bits_per_pixel) {
+	case 1:
+	case 8:
+		var->red.offset = 0;
+		var->red.length = 8;
+		var->green.offset = 0;
+		var->green.length = 8;
+		var->blue.offset = 0;
+		var->blue.length = 8;
+		var->transp.offset = 0;
+		var->transp.length = 0;
+		break;
+	case 4:
+		var->red.offset = 0;
+		var->red.length = 4;
+		var->green.offset = 0;
+		var->green.length = 4;
+		var->blue.offset = 0;
+		var->blue.length = 4;
+		var->transp.offset = 0;
+		var->transp.length = 0;
+		break;
+	case 16:		/* RGB 565 */
+		var->red.offset = 0;
+		var->red.length = 5;
+		var->green.offset = 5;
+		var->green.length = 6;
+		var->blue.offset = 11;
+		var->blue.length = 5;
+		var->transp.offset = 0;
+		var->transp.length = 0;
+		break;
+	default:
+		err = -EINVAL;
+	}
+
+	var->red.msb_right = 0;
+	var->green.msb_right = 0;
+	var->blue.msb_right = 0;
+	var->transp.msb_right = 0;
+	return err;
+}
+
+static int __devexit fb_remove(struct platform_device *dev)
+{
+	struct fb_info *info = dev_get_drvdata(&dev->dev);
+	int ret = 0;
+
+	if (info) {
+		struct da8xx_fb_par *par = info->par;
+
+		if (lcdc_read(LCD_RASTER_CTRL_REG) & LCD_RASTER_ENABLE)
+			ret = lcd_disable_raster(par);
+		lcdc_write(0, LCD_RASTER_CTRL_REG);
+
+		/* disable DMA  */
+		lcdc_write(0, LCD_DMA_CTRL_REG);
+
+		unregister_framebuffer(info);
+		fb_dealloc_cmap(&info->cmap);
+		dma_free_coherent(NULL, par->databuf_sz + PAGE_SIZE,
+					info->screen_base,
+					info->fix.smem_start);
+		free_irq(par->irq, NULL);
+		clk_disable(par->lcdc_clk);
+		clk_put(par->lcdc_clk);
+		framebuffer_release(info);
+
+	}
+	return ret;
+}
+
+static int fb_ioctl(struct fb_info *info, unsigned int cmd,
+			  unsigned long arg)
+{
+	struct lcd_sync_arg sync_arg;
+
+	switch (cmd) {
+	case FBIOGET_CONTRAST:
+	case FBIOPUT_CONTRAST:
+	case FBIGET_BRIGHTNESS:
+	case FBIPUT_BRIGHTNESS:
+	case FBIGET_COLOR:
+	case FBIPUT_COLOR:
+		return -EINVAL;
+	case FBIPUT_HSYNC:
+		if (copy_from_user(&sync_arg, (char *)arg,
+				sizeof(struct lcd_sync_arg)))
+			return -EINVAL;
+		lcd_cfg_horizontal_sync(sync_arg.back_porch,
+					sync_arg.pulse_width,
+					sync_arg.front_porch);
+		break;
+	case FBIPUT_VSYNC:
+		if (copy_from_user(&sync_arg, (char *)arg,
+				sizeof(struct lcd_sync_arg)))
+			return -EINVAL;
+		lcd_cfg_vertical_sync(sync_arg.back_porch,
+					sync_arg.pulse_width,
+					sync_arg.front_porch);
+		break;
+	default:
+		return -EINVAL;
+	}
+	return 0;
+}
+
+static struct fb_ops da8xx_fb_ops = {
+	.owner = THIS_MODULE,
+	.fb_check_var = fb_check_var,
+	.fb_setcolreg = fb_setcolreg,
+	.fb_ioctl = fb_ioctl,
+	.fb_fillrect = cfb_fillrect,
+	.fb_copyarea = cfb_copyarea,
+	.fb_imageblit = cfb_imageblit,
+};
+
+static int __init fb_probe(struct platform_device *device)
+{
+	struct da8xx_lcdc_platform_data *fb_pdata =
+						device->dev.platform_data;
+	struct lcd_ctrl_config *lcd_cfg;
+	struct da8xx_panel *lcdc_info;
+	struct fb_info *da8xx_fb_info;
+	struct resource *lcdc_regs;
+	struct clk *fb_clk = NULL;
+	struct da8xx_fb_par *par;
+	resource_size_t len;
+	int ret, i;
+
+	if (fb_pdata == NULL) {
+		dev_err(&device->dev, "Can not get platform data\n");
+		return -ENOENT;
+	}
+
+	lcdc_regs = platform_get_resource(device, IORESOURCE_MEM, 0);
+	if (!lcdc_regs) {
+		dev_err(&device->dev,
+			"Can not get memory resource for LCD controller\n");
+		return -ENOENT;
+	}
+
+	len = lcdc_regs->end - lcdc_regs->start + 1;
+
+	lcdc_regs = request_mem_region(lcdc_regs->start, len, lcdc_regs->name);
+	if (!lcdc_regs)
+		return -EBUSY;
+
+	da8xx_fb_reg_base = (resource_size_t)ioremap(lcdc_regs->start, len);
+
+	fb_clk = clk_get(&device->dev, NULL);
+	if (IS_ERR(fb_clk)) {
+		dev_err(&device->dev, "Can not get device clock\n");
+		ret = -ENODEV;
+		goto err_request_mem;
+	}
+	ret = clk_enable(fb_clk);
+	if (ret)
+		goto err_clk_put;
+
+	for (i = 0, lcdc_info = known_lcd_panels;
+		i < ARRAY_SIZE(known_lcd_panels);
+		i++, lcdc_info++) {
+		if (strcmp(fb_pdata->type, lcdc_info->name) == 0)
+			break;
+	}
+
+	if (i == ARRAY_SIZE(known_lcd_panels)) {
+		dev_err(&device->dev, "GLCD: No valid panel found\n");
+		ret = ENODEV;
+		goto err_clk_disable;
+	} else
+		dev_info(&device->dev, "GLCD: Found %s panel\n",
+					fb_pdata->type);
+
+	lcd_cfg = (struct lcd_ctrl_config *)fb_pdata->controller_data;
+
+	da8xx_fb_info = framebuffer_alloc(sizeof(struct da8xx_fb_par),
+					&device->dev);
+	if (!da8xx_fb_info) {
+		dev_dbg(&device->dev, "Memory allocation failed for fb_info\n");
+		ret = -ENOMEM;
+		goto err_clk_disable;
+	}
+
+	par = da8xx_fb_info->par;
+
+	if (lcd_init(par, lcd_cfg, lcdc_info) < 0) {
+		dev_err(&device->dev, "lcd_init failed\n");
+		ret = -EFAULT;
+		goto err_release_fb;
+	}
+
+	/* allocate frame buffer */
+	da8xx_fb_info->screen_base = dma_alloc_coherent(NULL,
+					par->databuf_sz + PAGE_SIZE,
+					(resource_size_t *)
+					&da8xx_fb_info->fix.smem_start,
+					GFP_KERNEL | GFP_DMA);
+
+	if (!da8xx_fb_info->screen_base) {
+		dev_err(&device->dev,
+			"GLCD: kmalloc for frame buffer failed\n");
+		ret = -EINVAL;
+		goto err_release_fb;
+	}
+
+	/* move palette base pointer by (PAGE_SIZE - palette_sz) bytes */
+	par->v_palette_base = da8xx_fb_info->screen_base +
+				(PAGE_SIZE - par->palette_sz);
+	par->p_palette_base = da8xx_fb_info->fix.smem_start +
+				(PAGE_SIZE - par->palette_sz);
+
+	/* the rest of the frame buffer is pixel data */
+	da8xx_fb_info->screen_base = par->v_palette_base + par->palette_sz;
+	da8xx_fb_fix.smem_start = par->p_palette_base + par->palette_sz;
+	da8xx_fb_fix.smem_len = par->databuf_sz - par->palette_sz;
+	da8xx_fb_fix.line_length = (lcdc_info->width * lcd_cfg->bpp) / 8;
+
+	par->lcdc_clk = fb_clk;
+
+	init_waitqueue_head(&par->da8xx_wq);
+
+	par->irq = platform_get_irq(device, 0);
+	if (par->irq < 0) {
+		ret = -ENOENT;
+		goto err_release_fb_mem;
+	}
+
+	ret = request_irq(par->irq, lcdc_irq_handler, 0, DRIVER_NAME, par);
+	if (ret)
+		goto err_release_fb_mem;
+
+	/* Initialize par */
+	da8xx_fb_info->var.bits_per_pixel = lcd_cfg->bpp;
+
+	da8xx_fb_var.xres = lcdc_info->width;
+	da8xx_fb_var.xres_virtual = lcdc_info->width;
+
+	da8xx_fb_var.yres = lcdc_info->height;
+	da8xx_fb_var.yres_virtual = lcdc_info->height;
+
+	da8xx_fb_var.grayscale =
+	    lcd_cfg->p_disp_panel->panel_shade == MONOCHROME ? 1 : 0;
+	da8xx_fb_var.bits_per_pixel = lcd_cfg->bpp;
+
+	da8xx_fb_var.hsync_len = lcdc_info->hsw;
+	da8xx_fb_var.vsync_len = lcdc_info->vsw;
+
+	/* Initialize fbinfo */
+	da8xx_fb_info->flags = FBINFO_FLAG_DEFAULT;
+	da8xx_fb_info->fix = da8xx_fb_fix;
+	da8xx_fb_info->var = da8xx_fb_var;
+	da8xx_fb_info->fbops = &da8xx_fb_ops;
+	da8xx_fb_info->pseudo_palette = par->pseudo_palette;
+
+	ret = fb_alloc_cmap(&da8xx_fb_info->cmap, PALETTE_SIZE, 0);
+	if (ret)
+		goto err_free_irq;
+
+	/* First palette_sz byte of the frame buffer is the palette */
+	da8xx_fb_info->cmap.len = par->palette_sz;
+
+	/* Flush the buffer to the screen. */
+	lcd_blit(LOAD_DATA, par);
+
+	/* initialize var_screeninfo */
+	da8xx_fb_var.activate = FB_ACTIVATE_FORCE;
+	fb_set_var(da8xx_fb_info, &da8xx_fb_var);
+
+	dev_set_drvdata(&device->dev, da8xx_fb_info);
+	/* Register the Frame Buffer  */
+	if (register_framebuffer(da8xx_fb_info) < 0) {
+		dev_err(&device->dev,
+			"GLCD: Frame Buffer Registration Failed!\n");
+		ret = -EINVAL;
+		goto err_dealloc_cmap;
+	}
+
+	/* enable raster engine */
+	lcdc_write(lcdc_read(LCD_RASTER_CTRL_REG) |
+			LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG);
+
+	return 0;
+
+err_dealloc_cmap:
+	fb_dealloc_cmap(&da8xx_fb_info->cmap);
+
+err_free_irq:
+	free_irq(par->irq, NULL);
+
+err_release_fb_mem:
+	dma_free_coherent(NULL, par->databuf_sz + PAGE_SIZE,
+				da8xx_fb_info->screen_base,
+				da8xx_fb_info->fix.smem_start);
+
+err_release_fb:
+	framebuffer_release(da8xx_fb_info);
+
+err_clk_disable:
+	clk_disable(fb_clk);
+
+err_clk_put:
+	clk_put(fb_clk);
+
+err_request_mem:
+	release_mem_region(lcdc_regs->start, len);;
+
+	return ret;
+}
+
+#ifdef CONFIG_PM
+static int fb_suspend(struct platform_device *dev, pm_message_t state)
+{
+	 return -EBUSY;
+}
+static int fb_resume(struct platform_device *dev)
+{
+	 return -EBUSY;
+}
+#else
+#define fb_suspend NULL
+#define fb_resume NULL
+#endif
+
+static struct platform_driver da8xx_fb_driver = {
+	.probe = fb_probe,
+	.remove = fb_remove,
+	.suspend = fb_suspend,
+	.resume = fb_resume,
+	.driver = {
+		   .name = DRIVER_NAME,
+		   .owner = THIS_MODULE,
+		   },
+};
+
+static int __init da8xx_fb_init(void)
+{
+	return platform_driver_register(&da8xx_fb_driver);
+}
+
+static void __exit da8xx_fb_cleanup(void)
+{
+	platform_driver_unregister(&da8xx_fb_driver);
+}
+
+module_init(da8xx_fb_init);
+module_exit(da8xx_fb_cleanup);
+
+MODULE_DESCRIPTION("Framebuffer driver for TI da8xx/omap-l1xx");
+MODULE_AUTHOR("Texas Instruments");
+MODULE_LICENSE("GPL");
diff --git a/include/video/da8xx-fb.h b/include/video/da8xx-fb.h
new file mode 100644
index 0000000..5f77675
--- /dev/null
+++ b/include/video/da8xx-fb.h
@@ -0,0 +1,106 @@
+/*
+ * Header file for TI DA8XX LCD controller platform data.
+ *
+ * Copyright (C) 2008-2009 MontaVista Software Inc.
+ * Copyright (C) 2008-2009 Texas Instruments Inc
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#ifndef DA8XX_FB_H
+#define DA8XX_FB_H
+
+enum panel_type {
+	QVGA = 0
+};
+
+enum panel_shade {
+	MONOCHROME = 0,
+	COLOR_ACTIVE,
+	COLOR_PASSIVE,
+};
+
+enum raster_load_mode {
+	LOAD_DATA = 1,
+	LOAD_PALETTE,
+};
+
+struct display_panel {
+	enum panel_type panel_type; /* QVGA */
+	int max_bpp;
+	int min_bpp;
+	enum panel_shade panel_shade;
+};
+
+struct da8xx_lcdc_platform_data {
+	const char manu_name[10];
+	void *controller_data;
+	const char type[25];
+};
+
+struct lcd_ctrl_config {
+	const struct display_panel *p_disp_panel;
+
+	/* AC Bias Pin Frequency */
+	int ac_bias;
+
+	/* AC Bias Pin Transitions per Interrupt */
+	int ac_bias_intrpt;
+
+	/* DMA burst size */
+	int dma_burst_sz;
+
+	/* Bits per pixel */
+	int bpp;
+
+	/* FIFO DMA Request Delay */
+	int fdd;
+
+	/* TFT Alternative Signal Mapping (Only for active) */
+	unsigned char tft_alt_mode;
+
+	/* 12 Bit Per Pixel (5-6-5) Mode (Only for passive) */
+	unsigned char stn_565_mode;
+
+	/* Mono 8-bit Mode: 1=D0-D7 or 0=D0-D3 */
+	unsigned char mono_8bit_mode;
+
+	/* Invert pixel clock */
+	unsigned char invert_pxl_clock;
+
+	/* Invert line clock */
+	unsigned char invert_line_clock;
+
+	/* Invert frame clock  */
+	unsigned char invert_frm_clock;
+
+	/* Horizontal and Vertical Sync Edge: 0=rising 1=falling */
+	unsigned char sync_edge;
+
+	/* Horizontal and Vertical Sync: Control: 0=ignore */
+	unsigned char sync_ctrl;
+
+	/* Raster Data Order Select: 1=Most-to-least 0=Least-to-most */
+	unsigned char raster_order;
+};
+
+struct lcd_sync_arg {
+	int back_porch;
+	int front_porch;
+	int pulse_width;
+};
+
+/* ioctls */
+#define FBIOGET_CONTRAST	_IOR('F', 1, int)
+#define FBIOPUT_CONTRAST	_IOW('F', 2, int)
+#define FBIGET_BRIGHTNESS	_IOR('F', 3, int)
+#define FBIPUT_BRIGHTNESS	_IOW('F', 3, int)
+#define FBIGET_COLOR		_IOR('F', 5, int)
+#define FBIPUT_COLOR		_IOW('F', 6, int)
+#define FBIPUT_HSYNC		_IOW('F', 9, int)
+#define FBIPUT_VSYNC		_IOW('F', 10, int)
+
+#endif  /* ifndef DA8XX_FB_H */
+
-- 
1.5.6

Re: [Linux-fbdev-devel] [linux-fbdev-devel][PATCH]fb_pan_display:add x/yoffset check

[Kai J. <b1...@fr...>]

Florian Tobias Schandinat wrote:
> Ville Syrjälä schrieb:
>>> So here we have to check the whether the x/yoffset is smaller than 
>>> zero. If the offset is smaller than zero, in the driver, we should 
>>> not move the virtual screen any more.
>>
>> Checking for overflow will catch you buggy application's negative
>> values too.
>
> That's true, but the problem lies in the current implementation first 
> adding the resolution, which results in small negative [0 to 
> -resolution] values (=large positives) being accepted as they overflow 
> during add and become small positive values.
> I'd recommend changing
>
> var->yoffset + yres > info->var.yres_virtual ||
> var->xoffset + info->var.xres > info->var.xres_virtual
>
> to
>
> var->yoffset > info->var.yres_virtual - yres ||
> var->xoffset > info->var.xres_virtual - info->var.xres
>
I am not sure why do we have these change. Could you give a detail 
description or an example?
Thanks!

Best Regards,

Kai Jiang

Re: [Linux-fbdev-devel] [linux-fbdev-devel][PATCH]fb_pan_display:add x/yoffset check

[Kai J. <b1...@fr...>]

We can't suppose that all the user operating this x/yoffset will check 
it. If the user application transfer a negative x/yoffset into the fb 
driver, I suppose fb driver should do operation correctly. So here, I 
think checking x/yoffset to insure the virtual space not moving outside 
real screen is necessary.
> On Tue, Jun 30, 2009 at 11:25:52AM +0800, Kai Jiang wrote:
>   
>> xres,yres,xres_virtual,yres_virtual will be set in the display driver, they have actual value which match the screen(will not very huge).
>>
>> And here, these lines are not checking the overflowing, but checking whether the virtual space display is beyond the real screen.
>>
>> Take x boundary for example:(the screen x and virtual x relationship should be:)
>> xres+xoffset<xres_vritual && xoffset>0
>> This insure that, in the real screen, there are virtual picture display in the screen. When we move the virtual picture to the left, the xoffset will be smaller and smaller
>> to indicate the virtual picture is moving to the left. Finally, the xoffset will be zero when the screen left boundary and virtual picture left boundary overlap. When virtual display is still moving to the left, the xoffset will be negative. And what should be displayed in the gap between screen left boundary and virtual space left boundary?
>>     
>
> If you're storing negative values into xoffset/yoffset your application
> is buggy. Just fix it.
>
>   
>> So here we have to check the whether the x/yoffset is smaller than zero. If the offset is smaller than zero, in the driver, we should not move the virtual screen any more.
>>     
>
> Checking for overflow will catch you buggy application's negative
> values too.
>
>   

[Linux-fbdev-devel] [PATCH 2/3] drivers/video/imxfb.c: Fix resource size off by 1 error

[Julia L. <ju...@di...>]

From: Julia Lawall <ju...@di...>

In the first case, the change is not semantics-preserving, but
resource_size is used at the corresponding call to request_mem_region in
the same function.

In the second case, the change is semantics-preserving.

The problem was found using the following semantic patch:
(http://www.emn.fr/x-info/coccinelle/)

// <smpl>
@@
struct resource *res;
@@

- (res->end - res->start) + 1
+ resource_size(res)

@@
struct resource *res;
@@

- res->end - res->start
+ BAD(resource_size(res))
// </smpl>

Signed-off-by: Julia Lawall <ju...@di...>

---
 drivers/video/imxfb.c |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff -u -p a/drivers/video/imxfb.c b/drivers/video/imxfb.c
--- a/drivers/video/imxfb.c 2009-04-13 16:04:25.000000000 +0200
+++ b/drivers/video/imxfb.c 2009-07-04 21:37:48.000000000 +0200
@@ -754,7 +754,7 @@ failed_map:
 failed_getclock:
 	iounmap(fbi->regs);
 failed_ioremap:
-	release_mem_region(res->start, res->end - res->start);
+	release_mem_region(res->start, resource_size(res));
 failed_req:
 	kfree(info->pseudo_palette);
 failed_init:
@@ -785,7 +785,7 @@ static int __devexit imxfb_remove(struct
 	framebuffer_release(info);
 
 	iounmap(fbi->regs);
-	release_mem_region(res->start, res->end - res->start + 1);
+	release_mem_region(res->start, resource_size(res));
 	clk_disable(fbi->clk);
 	clk_put(fbi->clk);
 

[Linux-fbdev-devel] [PATCH] fb/intelfb: conflict with DRM_I915 and hide by default

[Jesse B. <jb...@vi...>]

Users get confused by this driver.  It's really a special purpose
embedded driver, and causes a lot of problems if enabled.  So hide it
under EMBEDDED by default, and make sure it doesn't get enabled with
the i915 DRM driver.

Dave, I'm hoping you can feed this to Linus through your tree.  It's
appropriate for 2.6.31 I think.

Signed-off-by: Jesse Barnes <jb...@vi...>

diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index d6d65ef..ec12f7a 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -1117,12 +1117,13 @@ config FB_CARILLO_RANCH
 
 config FB_INTEL
 	tristate "Intel 830M/845G/852GM/855GM/865G/915G/945G/945GM/965G/965GM support (EXPERIMENTAL)"
-	depends on EXPERIMENTAL && FB && PCI && X86 && AGP_INTEL
+	depends on EXPERIMENTAL && FB && PCI && X86 && AGP_INTEL && EMBEDDED
 	select FB_MODE_HELPERS
 	select FB_CFB_FILLRECT
 	select FB_CFB_COPYAREA
 	select FB_CFB_IMAGEBLIT
 	select FB_BOOT_VESA_SUPPORT if FB_INTEL = y
+	depends on !DRM_I915
 	help
 	  This driver supports the on-board graphics built in to the Intel
           830M/845G/852GM/855GM/865G/915G/915GM/945G/945GM/965G/965GM chipsets.

Re: [Linux-fbdev-devel] [linux-fbdev-devel][PATCH]fb_pan_display:add x/yoffset check

[Florian T. S. <Flo...@gm...>]

Ville Syrjälä schrieb:
>> So here we have to check the whether the x/yoffset is smaller than zero. If the offset is smaller than zero, in the driver, we should not move the virtual screen any more.
> 
> Checking for overflow will catch you buggy application's negative
> values too.

That's true, but the problem lies in the current implementation first 
adding the resolution, which results in small negative [0 to 
-resolution] values (=large positives) being accepted as they overflow 
during add and become small positive values.
I'd recommend changing

var->yoffset + yres > info->var.yres_virtual ||
var->xoffset + info->var.xres > info->var.xres_virtual

to

var->yoffset > info->var.yres_virtual - yres ||
var->xoffset > info->var.xres_virtual - info->var.xres


Greetings,

Florian Tobias Schandinat

Re: [Linux-fbdev-devel] [linux-fbdev-devel][PATCH]fb_pan_display:add x/yoffset check

[Ville S. <sy...@sc...>]

On Tue, Jun 30, 2009 at 11:25:52AM +0800, Kai Jiang wrote:
> 
> xres,yres,xres_virtual,yres_virtual will be set in the display driver, they have actual value which match the screen(will not very huge).
> 
> And here, these lines are not checking the overflowing, but checking whether the virtual space display is beyond the real screen.
> 
> Take x boundary for example:(the screen x and virtual x relationship should be:)
> xres+xoffset<xres_vritual && xoffset>0
> This insure that, in the real screen, there are virtual picture display in the screen. When we move the virtual picture to the left, the xoffset will be smaller and smaller
> to indicate the virtual picture is moving to the left. Finally, the xoffset will be zero when the screen left boundary and virtual picture left boundary overlap. When virtual display is still moving to the left, the xoffset will be negative. And what should be displayed in the gap between screen left boundary and virtual space left boundary?

If you're storing negative values into xoffset/yoffset your application
is buggy. Just fix it.

> So here we have to check the whether the x/yoffset is smaller than zero. If the offset is smaller than zero, in the driver, we should not move the virtual screen any more.

Checking for overflow will catch you buggy application's negative
values too.

-- 
Ville Syrjälä
sy...@sc...
http://www.sci.fi/~syrjala/

[Linux-fbdev-devel] [PATCH] media/omap: adding __init/__exit macros to lcd_drivers

[Peter H. <Pet...@gm...>]

From: Peter Huewe <pet...@gm...>

Trivial patch which adds the __init and __exit macros to the module_init /
module_exit functions to several files in drivers/video/omap/

linux version 2.6.31-rc1 - linus git tree

Signed-off-by: Peter Huewe <pet...@gm...>
---
diff --git a/drivers/video/omap/lcd_h3.c b/drivers/video/omap/lcd_h3.c
index 2486237..417ae5e 100644
--- a/drivers/video/omap/lcd_h3.c
+++ b/drivers/video/omap/lcd_h3.c
@@ -124,12 +124,12 @@ struct platform_driver h3_panel_driver = {
 	},
 };
 
-static int h3_panel_drv_init(void)
+static int __init h3_panel_drv_init(void)
 {
 	return platform_driver_register(&h3_panel_driver);
 }
 
-static void h3_panel_drv_cleanup(void)
+static void __exit h3_panel_drv_cleanup(void)
 {
 	platform_driver_unregister(&h3_panel_driver);
 }
diff --git a/drivers/video/omap/lcd_h4.c b/drivers/video/omap/lcd_h4.c
index 6ff5643..0c398bd 100644
--- a/drivers/video/omap/lcd_h4.c
+++ b/drivers/video/omap/lcd_h4.c
@@ -102,12 +102,12 @@ static struct platform_driver h4_panel_driver = {
 	},
 };
 
-static int h4_panel_drv_init(void)
+static int __init h4_panel_drv_init(void)
 {
 	return platform_driver_register(&h4_panel_driver);
 }
 
-static void h4_panel_drv_cleanup(void)
+static void __exit h4_panel_drv_cleanup(void)
 {
 	platform_driver_unregister(&h4_panel_driver);
 }
diff --git a/drivers/video/omap/lcd_inn1510.c b/drivers/video/omap/lcd_inn1510.c
index 6953ed4..cdbd8bb 100644
--- a/drivers/video/omap/lcd_inn1510.c
+++ b/drivers/video/omap/lcd_inn1510.c
@@ -109,12 +109,12 @@ struct platform_driver innovator1510_panel_driver = {
 	},
 };
 
-static int innovator1510_panel_drv_init(void)
+static int __init innovator1510_panel_drv_init(void)
 {
 	return platform_driver_register(&innovator1510_panel_driver);
 }
 
-static void innovator1510_panel_drv_cleanup(void)
+static void __exit innovator1510_panel_drv_cleanup(void)
 {
 	platform_driver_unregister(&innovator1510_panel_driver);
 }
diff --git a/drivers/video/omap/lcd_inn1610.c b/drivers/video/omap/lcd_inn1610.c
index 4c4f7ee..268f7f8 100644
--- a/drivers/video/omap/lcd_inn1610.c
+++ b/drivers/video/omap/lcd_inn1610.c
@@ -133,12 +133,12 @@ struct platform_driver innovator1610_panel_driver = {
 	},
 };
 
-static int innovator1610_panel_drv_init(void)
+static int __init innovator1610_panel_drv_init(void)
 {
 	return platform_driver_register(&innovator1610_panel_driver);
 }
 
-static void innovator1610_panel_drv_cleanup(void)
+static void __exit innovator1610_panel_drv_cleanup(void)
 {
 	platform_driver_unregister(&innovator1610_panel_driver);
 }
diff --git a/drivers/video/omap/lcd_osk.c b/drivers/video/omap/lcd_osk.c
index 379c96d..b3fa88b 100644
--- a/drivers/video/omap/lcd_osk.c
+++ b/drivers/video/omap/lcd_osk.c
@@ -127,12 +127,12 @@ struct platform_driver osk_panel_driver = {
 	},
 };
 
-static int osk_panel_drv_init(void)
+static int __init osk_panel_drv_init(void)
 {
 	return platform_driver_register(&osk_panel_driver);
 }
 
-static void osk_panel_drv_cleanup(void)
+static void __exit osk_panel_drv_cleanup(void)
 {
 	platform_driver_unregister(&osk_panel_driver);
 }
diff --git a/drivers/video/omap/lcd_palmte.c b/drivers/video/omap/lcd_palmte.c
index 2183173..4bf3c79 100644
--- a/drivers/video/omap/lcd_palmte.c
+++ b/drivers/video/omap/lcd_palmte.c
@@ -108,12 +108,12 @@ struct platform_driver palmte_panel_driver = {
 	},
 };
 
-static int palmte_panel_drv_init(void)
+static int __init palmte_panel_drv_init(void)
 {
 	return platform_driver_register(&palmte_panel_driver);
 }
 
-static void palmte_panel_drv_cleanup(void)
+static void __exit palmte_panel_drv_cleanup(void)
 {
 	platform_driver_unregister(&palmte_panel_driver);
 }
diff --git a/drivers/video/omap/lcd_palmtt.c b/drivers/video/omap/lcd_palmtt.c
index 57b0f6c..48ea1f9 100644
--- a/drivers/video/omap/lcd_palmtt.c
+++ b/drivers/video/omap/lcd_palmtt.c
@@ -113,12 +113,12 @@ struct platform_driver palmtt_panel_driver = {
 	},
 };
 
-static int palmtt_panel_drv_init(void)
+static int __init palmtt_panel_drv_init(void)
 {
 	return platform_driver_register(&palmtt_panel_driver);
 }
 
-static void palmtt_panel_drv_cleanup(void)
+static void __exit palmtt_panel_drv_cleanup(void)
 {
 	platform_driver_unregister(&palmtt_panel_driver);
 }
diff --git a/drivers/video/omap/lcd_palmz71.c b/drivers/video/omap/lcd_palmz71.c
index d33d78b..0697d29 100644
--- a/drivers/video/omap/lcd_palmz71.c
+++ b/drivers/video/omap/lcd_palmz71.c
@@ -109,12 +109,12 @@ struct platform_driver palmz71_panel_driver = {
 	},
 };
 
-static int palmz71_panel_drv_init(void)
+static int __init palmz71_panel_drv_init(void)
 {
 	return platform_driver_register(&palmz71_panel_driver);
 }
 
-static void palmz71_panel_drv_cleanup(void)
+static void __exit palmz71_panel_drv_cleanup(void)
 {
 	platform_driver_unregister(&palmz71_panel_driver);
 }

[Linux-fbdev-devel] [PATCH] [drivers] [fb] S3C-fb: fix off-by-one bug in loop indexes

[Marek S. <m.s...@sa...>]

From: Pawel Osciak <p.o...@sa...>

Fixed off-by-one bug in loop indexes - some elements beyond windows' array were
accessed, which might result in memory access violations when removing/suspending
the device.

Signed-off-by: Pawel Osciak <p.o...@sa...>
Reviewed-by: Kyungmin Park <kyu...@sa...>
Signed-off-by: Marek Szyprowski <m.s...@sa...>


--- 

diff --git a/drivers/video/s3c-fb.c b/drivers/video/s3c-fb.c
index 094bfeb..92f2a59 100644
--- a/drivers/video/s3c-fb.c
+++ b/drivers/video/s3c-fb.c
@@ -970,7 +970,7 @@ static int __devexit s3c_fb_remove(struct platform_device *pdev)
 	struct s3c_fb *sfb = platform_get_drvdata(pdev);
 	int win;
 
-	for (win = 0; win <= S3C_FB_MAX_WIN; win++)
+	for (win = 0; win < S3C_FB_MAX_WIN; win++)
 		if (sfb->windows[win])
 			s3c_fb_release_win(sfb, sfb->windows[win]);
 
@@ -994,7 +994,7 @@ static int s3c_fb_suspend(struct platform_device *pdev, pm_message_t state)
 	struct s3c_fb_win *win;
 	int win_no;
 
-	for (win_no = S3C_FB_MAX_WIN; win_no >= 0; win_no--) {
+	for (win_no = S3C_FB_MAX_WIN - 1; win_no >= 0; win_no--) {
 		win = sfb->windows[win_no];
 		if (!win)
 			continue;

Re: [Linux-fbdev-devel] [PATCH v4] Frame Buffer driver for TI DA8xx/OMAP-L1xx

[Krzysztof H. <krz...@po...>]

On Tue, 30 Jun 2009 01:50:13 -0400
"Rajashekhara, Sudhakar" <sud...@ti...> wrote:

> Adds LCD controller (LCDC) driver for TI's DA8xx/OMAP-L1xx architecture.
> LCDC specifications can be found at http://www.ti.com/litv/pdf/sprufm0a.
> 
> LCDC on DA8xx consists of two independent controllers, the Raster Controller
> and the LCD Interface Display Driver (LIDD) controller. LIDD further supports
> character and graphic displays.
> 
> This patch adds support for the graphic display (Sharp LQ035Q3DG01) found on
> the DA830 based EVM. The EVM details can be found at:
> http://support.spectrumdigital.com/boards/dskda830/revc/.
> 
> Signed-off-by: Sudhakar Rajashekhara <sud...@ti...>
> Signed-off-by: Pavel Kiryukhin <pki...@ru...>
> Signed-off-by: Steve Chen <sc...@mv...>
> ---
>  Since the previous version, fb_setcolreg function has been modified for
>  8 and 16 bit modes.
> 
>  drivers/video/Kconfig    |   11 +
>  drivers/video/Makefile   |    1 +
>  drivers/video/da8xx-fb.c |  897 ++++++++++++++++++++++++++++++++++++++++++++++
>  include/video/da8xx-fb.h |  106 ++++++
>  4 files changed, 1015 insertions(+), 0 deletions(-)
>  create mode 100644 drivers/video/da8xx-fb.c
>  create mode 100644 include/video/da8xx-fb.h
> 

> diff --git a/drivers/video/da8xx-fb.c b/drivers/video/da8xx-fb.c
> new file mode 100644
> index 0000000..3135234
> --- /dev/null
> +++ b/drivers/video/da8xx-fb.c
> @@ -0,0 +1,897 @@

(...)

> +
> +static int fb_setcolreg(unsigned regno, unsigned red, unsigned green,
> +			      unsigned blue, unsigned transp,
> +			      struct fb_info *info)
> +{
> +	struct da8xx_fb_par *par = info->par;
> +	unsigned short *palette = (unsigned short *)par->v_palette_base;
> +	u_short pal;
> +
> +	if (regno > 255)
> +		return 1;
> +
> +	if (info->fix.visual == FB_VISUAL_DIRECTCOLOR)
> +		return 1;
> +
> +	if (info->var.bits_per_pixel == 8) {
> +		red >>= 4;
> +		green >>= 4;
> +		blue >>= 4;
> +
> +		pal = (red & 0x0f00);
> +		pal |= (green & 0x00f0);
> +		pal |= (blue & 0x000f);
> +
> +		palette[regno] = pal;
> +

I am losing my patience. The shift value for the red component is right (probably as I do 
not know the format of this palette registers). It is however almost surely wrong for other
componets. Just put this simple example value to get almost white color:
red = 0xf000;
green = 0xf000;
blue = 0xf000;

The resulting palette value would be 0xf00. Is it close to white on your controller?

Another example: blue
red = 0;
green = 0;
blue = 0xff00;

The result : 0x0. It does not differ from the value for black colour (rgb = 0/0/0).

> +	} else if ((info->var.bits_per_pixel == 16) && regno < 16) {
> +		red >>= (16 - info->var.red.length);
> +		red <<= info->var.red.offset;
> +
> +		green >>= (16 - info->var.green.length);
> +		green <<= info->var.green.offset;
> +
> +		blue >>= (16 - info->var.blue.length);
> +		blue <<= info->var.blue.offset;
> +
> +		par->pseudo_palette[regno] = red | green | blue;
> +
> +		palette[0] = 0x4000;
> +	}

This one is OK.

Regards,
Krzysztof

----------------------------------------------------------------------
Wybierz najlepsze ubezpieczenie komunikacyjne w Ergo Hestia
http://link.interia.pl/f222a

[Linux-fbdev-devel] [PATCH] fixed clock setting for Samsung SoC Framebuffer.

[InKi D. <da...@gm...>]

This patch corrects CLKVAL_F field value of VIDEO MAIN CONTROLLER 0 REGITSTER.

Frame Rate is 1 / [ { (VSPW+1) + (VBPD+1) + (LIINEVAL + 1) + (VFPD+1)
} x {(HSPW+1) + (HBPD +1)
+ (HFPD+1) + (HOZVAL + 1) } x { ( CLKVAL+1 ) / ( Frequency of Clock
source ) } ] and VCLK = Video Clock Source / (CLKVAL +1).

therefore CLKVAL_F should be "CLKVAL_F = Frequency of Clock source /
pixel clock * refresh".

for this, I added refresh value in platform data like below.
static struct s3c_fb_pd_win xxx_fb_win0 = {
	/* this is to ensure we use win0 */
	.win_mode = {
		.refresh	= 60,
		.pixclock	= (66+4+2+480)*(15+5+3+800),
		.left_margin	= 66,
		.right_margin	= 2,
		.upper_margin	= 15,
		.lower_margin	= 3,
		.hsync_len	= 4,
		.vsync_len	= 5,
		.xres		= 480,
		.yres		= 800,
	},
	.max_bpp	= 32,
	.default_bpp	= 24,
};

static struct s3c_fb_platdata xxx_lcd_pdata __initdata = {
	.win[0]		= &xxx_fb_win0,
	.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
	.vidcon1	= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC
			| VIDCON1_INV_VCLK | VIDCON1_INV_VDEN,
	.setup_gpio	= s5pc1xx_fb_gpio_setup_24bpp,
};

xxx_machine_init()
{
                   .
                   .
                   .
               s3c_fb_set_platdata(&xxx_lcd_pdata);
}

platform data defined in machine code should be setting using
s3c_fb_set_platdata().

I have tested this patch on boards based on s3c6410 and s5pc100 and worked fine.
I attached the patch for s3c-fb.c file.

thanks.

signed-by-off : InKi Dae. <ink...@sa...>

Re: [Linux-fbdev-devel] [Bugme-new] [Bug 13285] New: INTELFB: Colors display incorrectly

[Michal S. <hra...@ce...>]

Hello

2009/6/2 Andrew Morton <ak...@li...>:
> On Sat, 30 May 2009 13:58:33 +0200
> Krzysztof Helt <krz...@po...> wrote:
>
>> The intelfb driver sets color map depending on currently active pipe. However, if an LVDS
>> display is attached (like in laptop) the active pipe variable is never set. The default value is
>> PIPE_A and can be wrong.
>> Set up the pipe variable during driver initialization after hardware state was read.
>>
>> Also, the detection of the active display (and hence the pipe) is wrong. The pipes are assigned
>> to so called planes. Both pipes are always enabled on my laptop but only one plane is enabled
>> (the plane A for the CRT or the plane B for the LVDS). Change active pipe detection code
>> to take into account a status of the plane assigned to each pipe.
>>
>> The problem is visible in the 8 bpp mode if colors above 15 are used. The first 16 color
>> entries are displayed correctly.
>>
>> The graphics chip description is here (G45 vol. 3):
>> http://intellinuxgraphics.org/documentation.html
>>
>> Signed-off-by: Krzysztof Helt <krz...@wp...>
>>
>> ---
>> The second version of the fix to this problem. Now, it is much more sophisticated
>> based on the knowledge gained from documentation available at http://intellinuxgraphics.org/.
>>
>> It does not change a default behaviour (assumed pipe A) for all cases except the case that only
>> the plane assigned to the pipe B is active. It is enough to fix the issue for me.
>
> I queued this.
>
>> Please test it.
>
> But it would great be Dean and/or Michal were to be able to test it, please.
>

Sorry about the late reply.

In the end I could not test the patch on my system. Not only does the
patch not apply but intelfb fails to produce any screen output at all.
the command line is like this:

video=intelfb:mode=1280x1024 fbcon=rotate:1

Here is a boot with both intelfb and efifb. For some reason the efifb
is shown in this case but breaks so I thought I was looking at intelfb
because the output was different. Both geometry and colours are
broken. Part of the console (top, physical right) is invisible, part
(right, physical bottom) is not drawn (shows black initially and
garbage after switching to X and back).


Jun 29 12:50:30 uvt316-2 kernel: [    0.366168] efifb: dmi detected
Macmini1,1 - framebuffer at 80000000
(1024x768, stride 8192)
Jun 29 12:50:30 uvt316-2 kernel: [    0.366273] efifb: probing for efifb
Jun 29 12:50:30 uvt316-2 kernel: [    0.366486] efifb: framebuffer at
0x80000000, mapped to 0xf8100000, u
sing 6144k, total 6144k
Jun 29 12:50:30 uvt316-2 kernel: [    0.366496] efifb: mode is
1024x768x32, linelength=8192, pages=1
Jun 29 12:50:30 uvt316-2 kernel: [    0.366501] efifb: scrolling: redraw
Jun 29 12:50:30 uvt316-2 kernel: [    0.366508] efifb: Truecolor:
size=8:8:8:8, shift=24:16:8:0
Jun 29 12:50:30 uvt316-2 kernel: [    0.395938] Console: switching to
colour frame buffer device 96x64
Jun 29 12:50:30 uvt316-2 kernel: [    0.423483] fb0: EFI VGA frame buffer device
Jun 29 12:50:30 uvt316-2 kernel: [    0.427641] Linux agpgart interface v0.103
Jun 29 12:50:30 uvt316-2 kernel: [    0.427886] agpgart-intel
0000:00:00.0: Intel 945GM Chipset
Jun 29 12:50:30 uvt316-2 kernel: [    0.429006] agpgart-intel
0000:00:00.0: detected 16124K stolen memory
Jun 29 12:50:30 uvt316-2 kernel: [    0.432312] agpgart-intel
0000:00:00.0: AGP aperture is 256M @ 0x8000
0000
Jun 29 12:50:30 uvt316-2 kernel: [    0.432750] intelfb: Framebuffer
driver for Intel(R)
830M/845G/852GM/855GM/865G/915G/915GM/945G/945GM/945GME/965G/965GM
chipsets
Jun 29 12:50:30 uvt316-2 kernel: [    0.433387] intelfb: Version 0.9.6
Jun 29 12:50:30 uvt316-2 kernel: [    0.433626] intelfb 0000:00:02.0:
PCI INT A -> GSI 16 (level, low) -> IRQ 16
Jun 29 12:50:30 uvt316-2 kernel: [    0.434067] intelfb: Cannot
reserve FB region.


Intelfb only. No console output.

Jun 29 14:16:18 uvt316-2 kernel: [    0.370014] Linux agpgart interface v0.103
Jun 29 14:16:18 uvt316-2 kernel: [    0.370037] agpgart-intel
0000:00:00.0: Intel 945GM Chipset
Jun 29 14:16:18 uvt316-2 kernel: [    0.370786] agpgart-intel
0000:00:00.0: detected 16124K stolen memory
Jun 29 14:16:18 uvt316-2 kernel: [    0.373808] agpgart-intel
0000:00:00.0: AGP aperture is 256M @ 0x8000
0000
Jun 29 14:16:18 uvt316-2 kernel: [    0.373876] intelfb: Framebuffer
driver for Intel(R)
830M/845G/852GM/855GM/865G/915G/915GM/945G/945GM/945GME/965G/965GM
chipsets
Jun 29 14:16:18 uvt316-2 kernel: [    0.373886] intelfb: Version 0.9.6
Jun 29 14:16:18 uvt316-2 kernel: [    0.373937] intelfb 0000:00:02.0:
PCI INT A -> GSI 16 (level, low) -> IRQ 16
Jun 29 14:16:18 uvt316-2 kernel: [    0.373960] intelfb: 00:02.0:
Intel(R) 945GM, aperture size 256MB, stolen memory 16124kB
Jun 29 14:16:18 uvt316-2 kernel: [    0.377376] intelfb: Non-CRT
device is enabled ( DVO port B ).  Disabling mode switching.
Jun 29 14:16:18 uvt316-2 kernel: [    0.377392] intelfb: Video mode
must be programmed at boot time.



Efifb only with video=efifb fbcon=rotate:1
Produces correct geometry but broken colours.

Jun 29 15:26:59 uvt316-2 kernel: [    0.364224] efifb: dmi detected
Macmini1,1 - framebuffer at 80000000
(1024x768, stride 8192)
Jun 29 15:26:59 uvt316-2 kernel: [    0.364328] efifb: probing for efifb
Jun 29 15:26:59 uvt316-2 kernel: [    0.364609] efifb: framebuffer at
0x80000000, mapped to 0xf8100000, u
sing 8192k, total 8192k
Jun 29 15:26:59 uvt316-2 kernel: [    0.364619] efifb: mode is
1280x1024x16, linelength=8192, pages=1
Jun 29 15:26:59 uvt316-2 kernel: [    0.364624] efifb: scrolling: redraw
Jun 29 15:26:59 uvt316-2 kernel: [    0.364631] efifb: Truecolor:
size=8:8:8:8, shift=24:16:8:0
Jun 29 15:26:59 uvt316-2 kernel: [    0.389698] Console: switching to
colour frame buffer device 128x80
Jun 29 15:26:59 uvt316-2 kernel: [    0.413244] fb0: EFI VGA frame buffer device

[Linux-fbdev-devel] [PATCH v4] Frame Buffer driver for TI DA8xx/OMAP-L1xx

[Rajashekhara, S. <sud...@ti...>]

Adds LCD controller (LCDC) driver for TI's DA8xx/OMAP-L1xx architecture.
LCDC specifications can be found at http://www.ti.com/litv/pdf/sprufm0a.

LCDC on DA8xx consists of two independent controllers, the Raster Controller
and the LCD Interface Display Driver (LIDD) controller. LIDD further supports
character and graphic displays.

This patch adds support for the graphic display (Sharp LQ035Q3DG01) found on
the DA830 based EVM. The EVM details can be found at:
http://support.spectrumdigital.com/boards/dskda830/revc/.

Signed-off-by: Sudhakar Rajashekhara <sud...@ti...>
Signed-off-by: Pavel Kiryukhin <pki...@ru...>
Signed-off-by: Steve Chen <sc...@mv...>
---
 Since the previous version, fb_setcolreg function has been modified for
 8 and 16 bit modes.

 drivers/video/Kconfig    |   11 +
 drivers/video/Makefile   |    1 +
 drivers/video/da8xx-fb.c |  897 ++++++++++++++++++++++++++++++++++++++++++++++
 include/video/da8xx-fb.h |  106 ++++++
 4 files changed, 1015 insertions(+), 0 deletions(-)
 create mode 100644 drivers/video/da8xx-fb.c
 create mode 100644 include/video/da8xx-fb.h

diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 693fb4e..fc0c191 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -1984,6 +1984,17 @@ config FB_DAVINCI
 	  hardware found on the TI DaVinci EVM.	 If
 	  unsure, say N.
 
+config FB_DA8XX
+        tristate "DA8xx/OMAP-L1xx Framebuffer support"
+        depends on FB && ARCH_DAVINCI_DA830
+	select FB_CFB_FILLRECT
+	select FB_CFB_COPYAREA
+	select FB_CFB_IMAGEBLIT
+	---help---
+          This is the frame buffer device driver for the TI LCD controller
+	  found on DA8xx/OMAP-L1xx SoCs.
+          If unsure, say N.
+
 config FB_VIRTUAL
 	tristate "Virtual Frame Buffer support (ONLY FOR TESTING!)"
 	depends on FB
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 902d199..e7a3e7d 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -136,6 +136,7 @@ obj-$(CONFIG_FB_BF54X_LQ043)	  += bf54x-lq043fb.o
 obj-$(CONFIG_FB_BFIN_T350MCQB)	  += bfin-t350mcqb-fb.o
 obj-$(CONFIG_FB_MX3)		  += mx3fb.o
 obj-$(CONFIG_FB_DAVINCI)	  += davincifb.o
+obj-$(CONFIG_FB_DA8XX)		  += da8xx-fb.o
 
 # the test framebuffer is last
 obj-$(CONFIG_FB_VIRTUAL)          += vfb.o
diff --git a/drivers/video/da8xx-fb.c b/drivers/video/da8xx-fb.c
new file mode 100644
index 0000000..3135234
--- /dev/null
+++ b/drivers/video/da8xx-fb.c
@@ -0,0 +1,897 @@
+/*
+ * Copyright (C) 2008-2009 MontaVista Software Inc.
+ * Copyright (C) 2008-2009 Texas Instruments Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option)any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/fb.h>
+#include <linux/dma-mapping.h>
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <linux/uaccess.h>
+#include <linux/device.h>
+#include <linux/interrupt.h>
+#include <linux/clk.h>
+#include <video/da8xx-fb.h>
+
+#define DRIVER_NAME "da8xx_lcdc"
+
+/* LCD Status Register */
+#define LCD_END_OF_FRAME0		BIT(8)
+#define LCD_FIFO_UNDERFLOW		BIT(5)
+#define LCD_SYNC_LOST			BIT(2)
+
+/* LCD DMA Control Register */
+#define LCD_DMA_BURST_SIZE(x)		((x) << 4)
+#define LCD_DMA_BURST_1			0x0
+#define LCD_DMA_BURST_2			0x1
+#define LCD_DMA_BURST_4			0x2
+#define LCD_DMA_BURST_8			0x3
+#define LCD_DMA_BURST_16		0x4
+#define LCD_END_OF_FRAME_INT_ENA	BIT(2)
+#define LCD_DUAL_FRAME_BUFFER_ENABLE	BIT(0)
+
+/* LCD Control Register */
+#define LCD_CLK_DIVISOR(x)		((x) << 8)
+#define LCD_RASTER_MODE			0x01
+
+/* LCD Raster Control Register */
+#define LCD_PALETTE_LOAD_MODE(x)	((x) << 20)
+#define PALETTE_AND_DATA		0x00
+#define PALETTE_ONLY			0x01
+
+#define LCD_MONO_8BIT_MODE		BIT(9)
+#define LCD_RASTER_ORDER		BIT(8)
+#define LCD_TFT_MODE			BIT(7)
+#define LCD_UNDERFLOW_INT_ENA		BIT(6)
+#define LCD_MONOCHROME_MODE		BIT(1)
+#define LCD_RASTER_ENABLE		BIT(0)
+#define LCD_TFT_ALT_ENABLE		BIT(23)
+#define LCD_STN_565_ENABLE		BIT(24)
+
+/* LCD Raster Timing 2 Register */
+#define LCD_AC_BIAS_TRANSITIONS_PER_INT(x)	((x) << 16)
+#define LCD_AC_BIAS_FREQUENCY(x)		((x) << 8)
+#define LCD_SYNC_CTRL				BIT(25)
+#define LCD_SYNC_EDGE				BIT(24)
+#define LCD_INVERT_PIXEL_CLOCK			BIT(22)
+#define LCD_INVERT_LINE_CLOCK			BIT(21)
+#define LCD_INVERT_FRAME_CLOCK			BIT(20)
+
+/* LCD Block */
+#define  LCD_CTRL_REG				0x4
+#define  LCD_STAT_REG				0x8
+#define  LCD_RASTER_CTRL_REG			0x28
+#define  LCD_RASTER_TIMING_0_REG		0x2C
+#define  LCD_RASTER_TIMING_1_REG		0x30
+#define  LCD_RASTER_TIMING_2_REG		0x34
+#define  LCD_DMA_CTRL_REG			0x40
+#define  LCD_DMA_FRM_BUF_BASE_ADDR_0_REG	0x44
+#define  LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG	0x48
+
+#define WSI_TIMEOUT	50
+#define PALETTE_SIZE	256
+#define LEFT_MARGIN	64
+#define RIGHT_MARGIN	64
+#define UPPER_MARGIN	32
+#define LOWER_MARGIN	32
+
+static resource_size_t da8xx_fb_reg_base;
+
+static inline unsigned int lcdc_read(unsigned int addr)
+{
+	return (unsigned int)__raw_readl(da8xx_fb_reg_base + (addr));
+}
+
+static inline void lcdc_write(unsigned int val, unsigned int addr)
+{
+	__raw_writel(val, da8xx_fb_reg_base + (addr));
+}
+
+struct da8xx_fb_par {
+	wait_queue_head_t da8xx_wq;
+	resource_size_t p_palette_base;
+	unsigned char *v_palette_base;
+	struct clk *lcdc_clk;
+	unsigned int irq;
+	unsigned short pseudo_palette[16];
+	unsigned int databuf_sz;
+	unsigned int palette_sz;
+};
+
+/* Variable Screen Information */
+static struct fb_var_screeninfo da8xx_fb_var __devinitdata = {
+	.xoffset = 0,
+	.yoffset = 0,
+	.transp = {0, 0, 0},
+	.nonstd = 0,
+	.activate = 0,
+	.height = -1,
+	.width = -1,
+	.pixclock = 46666,	/* 46us - AUO display */
+	.accel_flags = 0,
+	.left_margin = LEFT_MARGIN,
+	.right_margin = RIGHT_MARGIN,
+	.upper_margin = UPPER_MARGIN,
+	.lower_margin = LOWER_MARGIN,
+	.sync = 0,
+	.vmode = FB_VMODE_NONINTERLACED
+};
+
+static struct fb_fix_screeninfo da8xx_fb_fix __devinitdata = {
+	.id = "DA8xx FB Drv",
+	.type = FB_TYPE_PACKED_PIXELS,
+	.type_aux = 0,
+	.visual = FB_VISUAL_PSEUDOCOLOR,
+	.xpanstep = 1,
+	.ypanstep = 1,
+	.ywrapstep = 1,
+	.accel = FB_ACCEL_NONE
+};
+
+struct da8xx_panel {
+	const char	name[25];	/* Full name <vendor>_<model> */
+	unsigned short	width;
+	unsigned short	height;
+	int		hfp;		/* Horizontal front porch */
+	int		hbp;		/* Horizontal back porch */
+	int		hsw;		/* Horizontal Sync Pulse Width */
+	int		vfp;		/* Vertical front porch */
+	int		vbp;		/* Vertical back porch */
+	int		vsw;		/* Vertical Sync Pulse Width */
+	int		pxl_clk;	/* Pixel clock */
+};
+
+static struct da8xx_panel known_lcd_panels[] = {
+	/* Sharp LCD035Q3DG01 */
+	[0] = {
+		.name = "Sharp_LCD035Q3DG01",
+		.width = 320,
+		.height = 240,
+		.hfp = 8,
+		.hbp = 6,
+		.hsw = 0,
+		.vfp = 2,
+		.vbp = 2,
+		.vsw = 0,
+		.pxl_clk = 0x10,
+	},
+	/* Sharp LK043T1DG01 */
+	[1] = {
+		.name = "Sharp_LK043T1DG01",
+		.width = 480,
+		.height = 272,
+		.hfp = 2,
+		.hbp = 2,
+		.hsw = 41,
+		.vfp = 2,
+		.vbp = 2,
+		.vsw = 10,
+		.pxl_clk = 0x12,
+	},
+};
+
+/* Disable the Raster Engine of the LCD Controller */
+static int lcd_disable_raster(struct da8xx_fb_par *par)
+{
+	int ret = 0;
+	u32 reg;
+
+	reg = lcdc_read(LCD_RASTER_CTRL_REG);
+	if (reg & LCD_RASTER_ENABLE) {
+		lcdc_write(reg & ~LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG);
+		ret = wait_event_interruptible_timeout(par->da8xx_wq,
+						!lcdc_read(LCD_STAT_REG) &
+						LCD_END_OF_FRAME0, WSI_TIMEOUT);
+	}
+
+	if (ret < 0)
+		return ret;
+	if (ret == 0)
+		return -ETIMEDOUT;
+
+	return 0;
+}
+
+static void lcd_blit(int load_mode, struct da8xx_fb_par *par)
+{
+	u32 tmp = par->p_palette_base + par->databuf_sz - 4;
+	u32 reg;
+
+	/* Update the databuf in the hw. */
+	lcdc_write(par->p_palette_base, LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
+	lcdc_write(tmp, LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
+
+	/* Start the DMA. */
+	reg = lcdc_read(LCD_RASTER_CTRL_REG);
+	reg &= ~(3 << 20);
+	if (load_mode == LOAD_DATA)
+		reg |= LCD_PALETTE_LOAD_MODE(PALETTE_AND_DATA);
+	else if (load_mode == LOAD_PALETTE)
+		reg |= LCD_PALETTE_LOAD_MODE(PALETTE_ONLY);
+
+	lcdc_write(reg, LCD_RASTER_CTRL_REG);
+}
+
+/* Configure the Burst Size of DMA */
+static int lcd_cfg_dma(int burst_size)
+{
+	u32 reg;
+
+	reg = lcdc_read(LCD_DMA_CTRL_REG) & 0x00000001;
+	switch (burst_size) {
+	case 1:
+		reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_1);
+		break;
+	case 2:
+		reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_2);
+		break;
+	case 4:
+		reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_4);
+		break;
+	case 8:
+		reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_8);
+		break;
+	case 16:
+		reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_16);
+		break;
+	default:
+		return -EINVAL;
+	}
+	lcdc_write(reg | LCD_END_OF_FRAME_INT_ENA, LCD_DMA_CTRL_REG);
+
+	return 0;
+}
+
+static void lcd_cfg_ac_bias(int period, int transitions_per_int)
+{
+	u32 reg;
+
+	/* Set the AC Bias Period and Number of Transisitons per Interrupt */
+	reg = lcdc_read(LCD_RASTER_TIMING_2_REG) & 0xFFF00000;
+	reg |= LCD_AC_BIAS_FREQUENCY(period) |
+		LCD_AC_BIAS_TRANSITIONS_PER_INT(transitions_per_int);
+	lcdc_write(reg, LCD_RASTER_TIMING_2_REG);
+}
+
+static void lcd_cfg_horizontal_sync(int back_porch, int pulse_width,
+		int front_porch)
+{
+	u32 reg;
+
+	reg = lcdc_read(LCD_RASTER_TIMING_0_REG) & 0xf;
+	reg |= ((back_porch & 0xff) << 24)
+	    | ((front_porch & 0xff) << 16)
+	    | ((pulse_width & 0x3f) << 10);
+	lcdc_write(reg, LCD_RASTER_TIMING_0_REG);
+}
+
+static void lcd_cfg_vertical_sync(int back_porch, int pulse_width,
+		int front_porch)
+{
+	u32 reg;
+
+	reg = lcdc_read(LCD_RASTER_TIMING_1_REG) & 0x3ff;
+	reg |= ((back_porch & 0xff) << 24)
+	    | ((front_porch & 0xff) << 16)
+	    | ((pulse_width & 0x3f) << 10);
+	lcdc_write(reg, LCD_RASTER_TIMING_1_REG);
+}
+
+static int lcd_cfg_display(const struct lcd_ctrl_config *cfg)
+{
+	u32 reg;
+
+	reg = lcdc_read(LCD_RASTER_CTRL_REG) & ~(LCD_TFT_MODE |
+						LCD_MONO_8BIT_MODE |
+						LCD_MONOCHROME_MODE);
+
+	switch (cfg->p_disp_panel->panel_shade) {
+	case MONOCHROME:
+		reg |= LCD_MONOCHROME_MODE;
+		if (cfg->mono_8bit_mode)
+			reg |= LCD_MONO_8BIT_MODE;
+		break;
+	case COLOR_ACTIVE:
+		reg |= LCD_TFT_MODE;
+		if (cfg->tft_alt_mode)
+			reg |= LCD_TFT_ALT_ENABLE;
+		break;
+
+	case COLOR_PASSIVE:
+		if (cfg->stn_565_mode)
+			reg |= LCD_STN_565_ENABLE;
+		break;
+
+	default:
+		return -EINVAL;
+	}
+
+	/* enable additional interrupts here */
+	reg |= LCD_UNDERFLOW_INT_ENA;
+
+	lcdc_write(reg, LCD_RASTER_CTRL_REG);
+
+	reg = lcdc_read(LCD_RASTER_TIMING_2_REG);
+
+	if (cfg->sync_ctrl)
+		reg |= LCD_SYNC_CTRL;
+	else
+		reg &= ~LCD_SYNC_CTRL;
+
+	if (cfg->sync_edge)
+		reg |= LCD_SYNC_EDGE;
+	else
+		reg &= ~LCD_SYNC_EDGE;
+
+	if (cfg->invert_pxl_clock)
+		reg |= LCD_INVERT_PIXEL_CLOCK;
+	else
+		reg &= ~LCD_INVERT_PIXEL_CLOCK;
+
+	if (cfg->invert_line_clock)
+		reg |= LCD_INVERT_LINE_CLOCK;
+	else
+		reg &= ~LCD_INVERT_LINE_CLOCK;
+
+	if (cfg->invert_frm_clock)
+		reg |= LCD_INVERT_FRAME_CLOCK;
+	else
+		reg &= ~LCD_INVERT_FRAME_CLOCK;
+
+	lcdc_write(reg, LCD_RASTER_TIMING_2_REG);
+
+	return 0;
+}
+
+static int lcd_cfg_frame_buffer(struct da8xx_fb_par *par, u32 width, u32 height,
+		u32 bpp, u32 raster_order)
+{
+	u32 bpl, reg;
+
+	/* Disable Dual Frame Buffer. */
+	reg = lcdc_read(LCD_DMA_CTRL_REG);
+	lcdc_write(reg & ~LCD_DUAL_FRAME_BUFFER_ENABLE,
+						LCD_DMA_CTRL_REG);
+	/* Set the Panel Width */
+	/* Pixels per line = (PPL + 1)*16 */
+	/*0x3F in bits 4..9 gives max horisontal resolution = 1024 pixels*/
+	width &= 0x3f0;
+	reg = lcdc_read(LCD_RASTER_TIMING_0_REG);
+	reg &= 0xfffffc00;
+	reg |= ((width >> 4) - 1) << 4;
+	lcdc_write(reg, LCD_RASTER_TIMING_0_REG);
+
+	/* Set the Panel Height */
+	reg = lcdc_read(LCD_RASTER_TIMING_1_REG);
+	reg = ((height - 1) & 0x3ff) | (reg & 0xfffffc00);
+	lcdc_write(reg, LCD_RASTER_TIMING_1_REG);
+
+	/* Set the Raster Order of the Frame Buffer */
+	reg = lcdc_read(LCD_RASTER_CTRL_REG) & ~(1 << 8);
+	if (raster_order)
+		reg |= LCD_RASTER_ORDER;
+	lcdc_write(reg, LCD_RASTER_CTRL_REG);
+
+	switch (bpp) {
+	case 1:
+	case 2:
+	case 4:
+	case 16:
+		par->palette_sz = 16 * 2;
+		break;
+
+	case 8:
+		par->palette_sz = 256 * 2;
+		break;
+
+	default:
+		return -EINVAL;
+	}
+
+	bpl = width * bpp / 8;
+	par->databuf_sz = height * bpl + par->palette_sz;
+
+	return 0;
+}
+
+static int fb_setcolreg(unsigned regno, unsigned red, unsigned green,
+			      unsigned blue, unsigned transp,
+			      struct fb_info *info)
+{
+	struct da8xx_fb_par *par = info->par;
+	unsigned short *palette = (unsigned short *)par->v_palette_base;
+	u_short pal;
+
+	if (regno > 255)
+		return 1;
+
+	if (info->fix.visual == FB_VISUAL_DIRECTCOLOR)
+		return 1;
+
+	if (info->var.bits_per_pixel == 8) {
+		red >>= 4;
+		green >>= 4;
+		blue >>= 4;
+
+		pal = (red & 0x0f00);
+		pal |= (green & 0x00f0);
+		pal |= (blue & 0x000f);
+
+		palette[regno] = pal;
+
+	} else if ((info->var.bits_per_pixel == 16) && regno < 16) {
+		red >>= (16 - info->var.red.length);
+		red <<= info->var.red.offset;
+
+		green >>= (16 - info->var.green.length);
+		green <<= info->var.green.offset;
+
+		blue >>= (16 - info->var.blue.length);
+		blue <<= info->var.blue.offset;
+
+		par->pseudo_palette[regno] = red | green | blue;
+
+		palette[0] = 0x4000;
+	}
+
+	return 0;
+}
+
+static int lcd_reset(struct da8xx_fb_par *par)
+{
+	int ret = 0;
+
+	/* Disable the Raster if previously Enabled */
+	if (lcdc_read(LCD_RASTER_CTRL_REG) & LCD_RASTER_ENABLE)
+		ret = lcd_disable_raster(par);
+
+	/* DMA has to be disabled */
+	lcdc_write(0, LCD_DMA_CTRL_REG);
+	lcdc_write(0, LCD_RASTER_CTRL_REG);
+
+	return ret;
+}
+
+static int lcd_init(struct da8xx_fb_par *par, const struct lcd_ctrl_config *cfg,
+		struct da8xx_panel *panel)
+{
+	u32 bpp, ret = 0;
+
+	ret = lcd_reset(par);
+	if (ret != 0)
+		return ret;
+
+	/* Configure the LCD clock divisor. */
+	lcdc_write(LCD_CLK_DIVISOR(panel->pxl_clk) |
+			(LCD_RASTER_MODE & 0x1), LCD_CTRL_REG);
+
+	/* Configure the DMA burst size. */
+	ret = lcd_cfg_dma(cfg->dma_burst_sz);
+	if (ret < 0)
+		return ret;
+
+	/* Configure the AC bias properties. */
+	lcd_cfg_ac_bias(cfg->ac_bias, cfg->ac_bias_intrpt);
+
+	/* Configure the vertical and horizontal sync properties. */
+	lcd_cfg_vertical_sync(panel->vbp, panel->vsw, panel->vfp);
+	lcd_cfg_horizontal_sync(panel->hbp, panel->hsw, panel->hfp);
+
+	/* Configure for disply */
+	ret = lcd_cfg_display(cfg);
+	if (ret < 0)
+		return ret;
+
+	if (QVGA != cfg->p_disp_panel->panel_type)
+		return -EINVAL;
+
+	if (cfg->bpp <= cfg->p_disp_panel->max_bpp &&
+	    cfg->bpp >= cfg->p_disp_panel->min_bpp)
+		bpp = cfg->bpp;
+	else
+		bpp = cfg->p_disp_panel->max_bpp;
+	if (bpp == 12)
+		bpp = 16;
+	ret = lcd_cfg_frame_buffer(par, (unsigned int)panel->width,
+				(unsigned int)panel->height, bpp,
+				cfg->raster_order);
+	if (ret < 0)
+		return ret;
+
+	/* Configure FDD */
+	lcdc_write((lcdc_read(LCD_RASTER_CTRL_REG) & 0xfff00fff) |
+		       (cfg->fdd << 12), LCD_RASTER_CTRL_REG);
+
+	return 0;
+}
+
+static irqreturn_t lcdc_irq_handler(int irq, void *arg)
+{
+	u32 stat = lcdc_read(LCD_STAT_REG);
+	struct da8xx_fb_par *par = arg;
+	u32 reg;
+
+	if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) {
+		reg = lcdc_read(LCD_RASTER_CTRL_REG);
+		lcdc_write(reg & ~LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG);
+		lcdc_write(stat, LCD_STAT_REG);
+		lcdc_write(reg | LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG);
+	} else
+		lcdc_write(stat, LCD_STAT_REG);
+
+	wake_up_interruptible(&par->da8xx_wq);
+	return IRQ_HANDLED;
+}
+
+static int fb_check_var(struct fb_var_screeninfo *var,
+			struct fb_info *info)
+{
+	int err = 0;
+
+	switch (var->bits_per_pixel) {
+	case 1:
+	case 8:
+		var->red.offset = 0;
+		var->red.length = 8;
+		var->green.offset = 0;
+		var->green.length = 8;
+		var->blue.offset = 0;
+		var->blue.length = 8;
+		var->transp.offset = 0;
+		var->transp.length = 0;
+		break;
+	case 4:
+		var->red.offset = 0;
+		var->red.length = 4;
+		var->green.offset = 0;
+		var->green.length = 4;
+		var->blue.offset = 0;
+		var->blue.length = 4;
+		var->transp.offset = 0;
+		var->transp.length = 0;
+		break;
+	case 16:		/* RGB 565 */
+		var->red.offset = 0;
+		var->red.length = 5;
+		var->green.offset = 5;
+		var->green.length = 6;
+		var->blue.offset = 11;
+		var->blue.length = 5;
+		var->transp.offset = 0;
+		var->transp.length = 0;
+		break;
+	default:
+		err = -EINVAL;
+	}
+
+	var->red.msb_right = 0;
+	var->green.msb_right = 0;
+	var->blue.msb_right = 0;
+	var->transp.msb_right = 0;
+	return err;
+}
+
+static int __devexit fb_remove(struct platform_device *dev)
+{
+	struct fb_info *info = dev_get_drvdata(&dev->dev);
+	int ret = 0;
+
+	if (info) {
+		struct da8xx_fb_par *par = info->par;
+
+		if (lcdc_read(LCD_RASTER_CTRL_REG) & LCD_RASTER_ENABLE)
+			ret = lcd_disable_raster(par);
+		lcdc_write(0, LCD_RASTER_CTRL_REG);
+
+		/* disable DMA  */
+		lcdc_write(0, LCD_DMA_CTRL_REG);
+
+		unregister_framebuffer(info);
+		fb_dealloc_cmap(&info->cmap);
+		dma_free_coherent(NULL, par->databuf_sz + PAGE_SIZE,
+					info->screen_base,
+					info->fix.smem_start);
+		free_irq(par->irq, NULL);
+		clk_disable(par->lcdc_clk);
+		clk_put(par->lcdc_clk);
+		framebuffer_release(info);
+
+	}
+	return ret;
+}
+
+static int fb_ioctl(struct fb_info *info, unsigned int cmd,
+			  unsigned long arg)
+{
+	struct lcd_sync_arg sync_arg;
+
+	switch (cmd) {
+	case FBIOGET_CONTRAST:
+	case FBIOPUT_CONTRAST:
+	case FBIGET_BRIGHTNESS:
+	case FBIPUT_BRIGHTNESS:
+	case FBIGET_COLOR:
+	case FBIPUT_COLOR:
+		return -EINVAL;
+	case FBIPUT_HSYNC:
+		if (copy_from_user(&sync_arg, (char *)arg,
+				sizeof(struct lcd_sync_arg)))
+			return -EINVAL;
+		lcd_cfg_horizontal_sync(sync_arg.back_porch,
+					sync_arg.pulse_width,
+					sync_arg.front_porch);
+		break;
+	case FBIPUT_VSYNC:
+		if (copy_from_user(&sync_arg, (char *)arg,
+				sizeof(struct lcd_sync_arg)))
+			return -EINVAL;
+		lcd_cfg_vertical_sync(sync_arg.back_porch,
+					sync_arg.pulse_width,
+					sync_arg.front_porch);
+		break;
+	default:
+		return -EINVAL;
+	}
+	return 0;
+}
+
+static struct fb_ops da8xx_fb_ops = {
+	.owner = THIS_MODULE,
+	.fb_check_var = fb_check_var,
+	.fb_setcolreg = fb_setcolreg,
+	.fb_ioctl = fb_ioctl,
+	.fb_fillrect = cfb_fillrect,
+	.fb_copyarea = cfb_copyarea,
+	.fb_imageblit = cfb_imageblit,
+};
+
+static int __init fb_probe(struct platform_device *device)
+{
+	struct da8xx_lcdc_platform_data *fb_pdata =
+						device->dev.platform_data;
+	struct lcd_ctrl_config *lcd_cfg;
+	struct da8xx_panel *lcdc_info;
+	struct fb_info *da8xx_fb_info;
+	struct resource *lcdc_regs;
+	struct clk *fb_clk = NULL;
+	struct da8xx_fb_par *par;
+	resource_size_t len;
+	int ret, i;
+
+	if (fb_pdata == NULL) {
+		dev_err(&device->dev, "Can not get platform data\n");
+		return -ENOENT;
+	}
+
+	lcdc_regs = platform_get_resource(device, IORESOURCE_MEM, 0);
+	if (!lcdc_regs) {
+		dev_err(&device->dev,
+			"Can not get memory resource for LCD controller\n");
+		return -ENOENT;
+	}
+
+	len = lcdc_regs->end - lcdc_regs->start + 1;
+
+	lcdc_regs = request_mem_region(lcdc_regs->start, len, lcdc_regs->name);
+	if (!lcdc_regs)
+		return -EBUSY;
+
+	da8xx_fb_reg_base = (resource_size_t)ioremap(lcdc_regs->start, len);
+
+	fb_clk = clk_get(&device->dev, NULL);
+	if (IS_ERR(fb_clk)) {
+		dev_err(&device->dev, "Can not get device clock\n");
+		ret = -ENODEV;
+		goto err_request_mem;
+	}
+	ret = clk_enable(fb_clk);
+	if (ret)
+		goto err_clk_put;
+
+	for (i = 0, lcdc_info = known_lcd_panels;
+		i < ARRAY_SIZE(known_lcd_panels);
+		i++, lcdc_info++) {
+		if (strcmp(fb_pdata->type, lcdc_info->name) == 0)
+			break;
+	}
+
+	if (i == ARRAY_SIZE(known_lcd_panels)) {
+		dev_err(&device->dev, "GLCD: No valid panel found\n");
+		ret = ENODEV;
+		goto err_clk_disable;
+	} else
+		dev_info(&device->dev, "GLCD: Found %s panel\n",
+					fb_pdata->type);
+
+	lcd_cfg = (struct lcd_ctrl_config *)fb_pdata->controller_data;
+
+	da8xx_fb_info = framebuffer_alloc(sizeof(struct da8xx_fb_par),
+					&device->dev);
+	if (!da8xx_fb_info) {
+		dev_dbg(&device->dev, "Memory allocation failed for fb_info\n");
+		ret = -ENOMEM;
+		goto err_clk_disable;
+	}
+
+	par = da8xx_fb_info->par;
+
+	if (lcd_init(par, lcd_cfg, lcdc_info) < 0) {
+		dev_err(&device->dev, "lcd_init failed\n");
+		ret = -EFAULT;
+		goto err_release_fb;
+	}
+
+	/* allocate frame buffer */
+	da8xx_fb_info->screen_base = dma_alloc_coherent(NULL,
+					par->databuf_sz + PAGE_SIZE,
+					(resource_size_t *)
+					&da8xx_fb_info->fix.smem_start,
+					GFP_KERNEL | GFP_DMA);
+
+	if (!da8xx_fb_info->screen_base) {
+		dev_err(&device->dev,
+			"GLCD: kmalloc for frame buffer failed\n");
+		ret = -EINVAL;
+		goto err_release_fb;
+	}
+
+	/* move palette base pointer by (PAGE_SIZE - palette_sz) bytes */
+	par->v_palette_base = da8xx_fb_info->screen_base +
+				(PAGE_SIZE - par->palette_sz);
+	par->p_palette_base = da8xx_fb_info->fix.smem_start +
+				(PAGE_SIZE - par->palette_sz);
+
+	/* the rest of the frame buffer is pixel data */
+	da8xx_fb_info->screen_base = par->v_palette_base + par->palette_sz;
+	da8xx_fb_fix.smem_start = par->p_palette_base + par->palette_sz;
+	da8xx_fb_fix.smem_len = par->databuf_sz - par->palette_sz;
+	da8xx_fb_fix.line_length = (lcdc_info->width * lcd_cfg->bpp) / 8;
+
+	par->lcdc_clk = fb_clk;
+
+	init_waitqueue_head(&par->da8xx_wq);
+
+	par->irq = platform_get_irq(device, 0);
+	if (par->irq < 0) {
+		ret = -ENOENT;
+		goto err_release_fb_mem;
+	}
+
+	ret = request_irq(par->irq, lcdc_irq_handler, 0, DRIVER_NAME, par);
+	if (ret)
+		goto err_release_fb_mem;
+
+	/* Initialize par */
+	da8xx_fb_info->var.bits_per_pixel = lcd_cfg->bpp;
+
+	da8xx_fb_var.xres = lcdc_info->width;
+	da8xx_fb_var.xres_virtual = lcdc_info->width;
+
+	da8xx_fb_var.yres = lcdc_info->height;
+	da8xx_fb_var.yres_virtual = lcdc_info->height;
+
+	da8xx_fb_var.grayscale =
+	    lcd_cfg->p_disp_panel->panel_shade == MONOCHROME ? 1 : 0;
+	da8xx_fb_var.bits_per_pixel = lcd_cfg->bpp;
+
+	da8xx_fb_var.hsync_len = lcdc_info->hsw;
+	da8xx_fb_var.vsync_len = lcdc_info->vsw;
+
+	/* Initialize fbinfo */
+	da8xx_fb_info->flags = FBINFO_FLAG_DEFAULT;
+	da8xx_fb_info->fix = da8xx_fb_fix;
+	da8xx_fb_info->var = da8xx_fb_var;
+	da8xx_fb_info->fbops = &da8xx_fb_ops;
+	da8xx_fb_info->pseudo_palette = par->pseudo_palette;
+
+	ret = fb_alloc_cmap(&da8xx_fb_info->cmap, PALETTE_SIZE, 0);
+	if (ret)
+		goto err_free_irq;
+
+	/* First palette_sz byte of the frame buffer is the palette */
+	da8xx_fb_info->cmap.len = par->palette_sz;
+
+	/* Flush the buffer to the screen. */
+	lcd_blit(LOAD_DATA, par);
+
+	/* initialize var_screeninfo */
+	da8xx_fb_var.activate = FB_ACTIVATE_FORCE;
+	fb_set_var(da8xx_fb_info, &da8xx_fb_var);
+
+	dev_set_drvdata(&device->dev, da8xx_fb_info);
+	/* Register the Frame Buffer  */
+	if (register_framebuffer(da8xx_fb_info) < 0) {
+		dev_err(&device->dev,
+			"GLCD: Frame Buffer Registration Failed!\n");
+		ret = -EINVAL;
+		goto err_dealloc_cmap;
+	}
+
+	/* enable raster engine */
+	lcdc_write(lcdc_read(LCD_RASTER_CTRL_REG) |
+			LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG);
+
+	return 0;
+
+err_dealloc_cmap:
+	fb_dealloc_cmap(&da8xx_fb_info->cmap);
+
+err_free_irq:
+	free_irq(par->irq, NULL);
+
+err_release_fb_mem:
+	dma_free_coherent(NULL, par->databuf_sz + PAGE_SIZE,
+				da8xx_fb_info->screen_base,
+				da8xx_fb_info->fix.smem_start);
+
+err_release_fb:
+	framebuffer_release(da8xx_fb_info);
+
+err_clk_disable:
+	clk_disable(fb_clk);
+
+err_clk_put:
+	clk_put(fb_clk);
+
+err_request_mem:
+	release_mem_region(lcdc_regs->start, len);;
+
+	return ret;
+}
+
+#ifdef CONFIG_PM
+static int fb_suspend(struct platform_device *dev, pm_message_t state)
+{
+	 return -EBUSY;
+}
+static int fb_resume(struct platform_device *dev)
+{
+	 return -EBUSY;
+}
+#else
+#define fb_suspend NULL
+#define fb_resume NULL
+#endif
+
+static struct platform_driver da8xx_fb_driver = {
+	.probe = fb_probe,
+	.remove = fb_remove,
+	.suspend = fb_suspend,
+	.resume = fb_resume,
+	.driver = {
+		   .name = DRIVER_NAME,
+		   .owner = THIS_MODULE,
+		   },
+};
+
+static int __init da8xx_fb_init(void)
+{
+	return platform_driver_register(&da8xx_fb_driver);
+}
+
+static void __exit da8xx_fb_cleanup(void)
+{
+	platform_driver_unregister(&da8xx_fb_driver);
+}
+
+module_init(da8xx_fb_init);
+module_exit(da8xx_fb_cleanup);
+
+MODULE_DESCRIPTION("Framebuffer driver for TI da8xx/omap-l1xx");
+MODULE_AUTHOR("Texas Instruments");
+MODULE_LICENSE("GPL");
diff --git a/include/video/da8xx-fb.h b/include/video/da8xx-fb.h
new file mode 100644
index 0000000..5f77675
--- /dev/null
+++ b/include/video/da8xx-fb.h
@@ -0,0 +1,106 @@
+/*
+ * Header file for TI DA8XX LCD controller platform data.
+ *
+ * Copyright (C) 2008-2009 MontaVista Software Inc.
+ * Copyright (C) 2008-2009 Texas Instruments Inc
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#ifndef DA8XX_FB_H
+#define DA8XX_FB_H
+
+enum panel_type {
+	QVGA = 0
+};
+
+enum panel_shade {
+	MONOCHROME = 0,
+	COLOR_ACTIVE,
+	COLOR_PASSIVE,
+};
+
+enum raster_load_mode {
+	LOAD_DATA = 1,
+	LOAD_PALETTE,
+};
+
+struct display_panel {
+	enum panel_type panel_type; /* QVGA */
+	int max_bpp;
+	int min_bpp;
+	enum panel_shade panel_shade;
+};
+
+struct da8xx_lcdc_platform_data {
+	const char manu_name[10];
+	void *controller_data;
+	const char type[25];
+};
+
+struct lcd_ctrl_config {
+	const struct display_panel *p_disp_panel;
+
+	/* AC Bias Pin Frequency */
+	int ac_bias;
+
+	/* AC Bias Pin Transitions per Interrupt */
+	int ac_bias_intrpt;
+
+	/* DMA burst size */
+	int dma_burst_sz;
+
+	/* Bits per pixel */
+	int bpp;
+
+	/* FIFO DMA Request Delay */
+	int fdd;
+
+	/* TFT Alternative Signal Mapping (Only for active) */
+	unsigned char tft_alt_mode;
+
+	/* 12 Bit Per Pixel (5-6-5) Mode (Only for passive) */
+	unsigned char stn_565_mode;
+
+	/* Mono 8-bit Mode: 1=D0-D7 or 0=D0-D3 */
+	unsigned char mono_8bit_mode;
+
+	/* Invert pixel clock */
+	unsigned char invert_pxl_clock;
+
+	/* Invert line clock */
+	unsigned char invert_line_clock;
+
+	/* Invert frame clock  */
+	unsigned char invert_frm_clock;
+
+	/* Horizontal and Vertical Sync Edge: 0=rising 1=falling */
+	unsigned char sync_edge;
+
+	/* Horizontal and Vertical Sync: Control: 0=ignore */
+	unsigned char sync_ctrl;
+
+	/* Raster Data Order Select: 1=Most-to-least 0=Least-to-most */
+	unsigned char raster_order;
+};
+
+struct lcd_sync_arg {
+	int back_porch;
+	int front_porch;
+	int pulse_width;
+};
+
+/* ioctls */
+#define FBIOGET_CONTRAST	_IOR('F', 1, int)
+#define FBIOPUT_CONTRAST	_IOW('F', 2, int)
+#define FBIGET_BRIGHTNESS	_IOR('F', 3, int)
+#define FBIPUT_BRIGHTNESS	_IOW('F', 3, int)
+#define FBIGET_COLOR		_IOR('F', 5, int)
+#define FBIPUT_COLOR		_IOW('F', 6, int)
+#define FBIPUT_HSYNC		_IOW('F', 9, int)
+#define FBIPUT_VSYNC		_IOW('F', 10, int)
+
+#endif  /* ifndef DA8XX_FB_H */
+
-- 
1.5.6

Re: [Linux-fbdev-devel] [PATCH v3] Frame Buffer driver for TI DA8xx/OMAP-L1xx

[Rajashekhara, S. <sud...@ti...>]

Hi,

On Fri, Jun 26, 2009 at 10:48:55, Krzysztof Helt wrote:
> On Wed, 24 Jun 2009 06:58:21 -0400
> "Rajashekhara, Sudhakar" <sud...@ti...> wrote:
> 
> > Adds LCD controller (LCDC) driver for TI's DA8xx/OMAP-L1xx architecture.
> > LCDC specifications can be found at http://www.ti.com/litv/pdf/sprufm0a.
> > 
> > LCDC on DA8xx consists of two independent controllers, the Raster Controller
> > and the LCD Interface Display Driver (LIDD) controller. LIDD further supports
> > character and graphic displays.
> > 
> > This patch adds support for the graphic display (Sharp LQ035Q3DG01) found on
> > the DA830 based EVM. The EVM details can be found at:
> > http://support.spectrumdigital.com/boards/dskda830/revc/.
> > 
> > Signed-off-by: Sudhakar Rajashekhara <sud...@ti...>
> > Signed-off-by: Pavel Kiryukhin <pki...@ru...>
> > Signed-off-by: Steve Chen <sc...@mv...>
> > ---

[...]

> 
> The true color modes do not use the palette entry. I assume
> that the value below forces controller to use true color mode.
> 
> > +		palette[0] = 0x4000;
> > +	}
> > +

You are right. The above line enables the true color mode.

I tested the driver with the changes suggested by you. I'll
be submitting the v4 version of the patch soon.

Regards,
Sudhakar

Re: [Linux-fbdev-devel] [linux-fbdev-devel][PATCH]fb_pan_display:add x/yoffset check

[Kai J. <b1...@fr...>]

xres,yres,xres_virtual,yres_virtual will be set in the display driver, they have actual value which match the screen(will not very huge).

And here, these lines are not checking the overflowing, but checking whether the virtual space display is beyond the real screen.

Take x boundary for example:(the screen x and virtual x relationship should be:)
xres+xoffset<xres_vritual && xoffset>0
This insure that, in the real screen, there are virtual picture display in the screen. When we move the virtual picture to the left, the xoffset will be smaller and smaller
to indicate the virtual picture is moving to the left. Finally, the xoffset will be zero when the screen left boundary and virtual picture left boundary overlap. When virtual display is still moving to the left, the xoffset will be negative. And what should be displayed in the gap between screen left boundary and virtual space left boundary?

So here we have to check the whether the x/yoffset is smaller than zero. If the offset is smaller than zero, in the driver, we should not move the virtual screen any more.


Best Regards,

Kai Jiang
 
 


> On Mon, Jun 29, 2009 at 11:49:31AM +0800, Kai Jiang wrote:
>   
>
>   
>> >From a01ede69772634b30a83b44eada5a8db66f8463a Mon Sep 17 00:00:00 2001
>> From: Kai Jiang <Kai...@fr...>
>> Date: Mon, 29 Jun 2009 11:25:58 +0800
>> Subject: [PATCH] When moving virtual space straight to one side in the screen(ex.
>>  straight to the left),finally the virtual space will move outside
>>  of the real screen. Then the xoffset or yoffset will be nagative
>>  value(transfered from user application) to indicate that the virtual
>>  space is beyond the screen boundary. In the function fb_pan_disaplay,
>>  xoffset and yoffset should be checked to ensure that, when they are
>>  negative, the virtual space will not move any more,and the function
>>  will return an error. However, xoffset and yoffset in the structure
>>  fb_var_screeninfo are "__u32" type, here need to transfer them to
>>  "int" type for comparing.
>>
>> Signed-off-by: Kai Jiang <Kai...@fr...>
>> ---
>>  drivers/video/fbmem.c |    5 ++++-
>>  1 files changed, 4 insertions(+), 1 deletions(-)
>>
>> diff --git a/drivers/video/fbmem.c b/drivers/video/fbmem.c
>> index d412a1d..27628de 100644
>> --- a/drivers/video/fbmem.c
>> +++ b/drivers/video/fbmem.c
>> @@ -855,6 +855,8 @@ fb_pan_display(struct fb_info *info, struct fb_var_screeninfo *var)
>>  {
>>  	struct fb_fix_screeninfo *fix = &info->fix;
>>  	unsigned int yres = info->var.yres;
>> +	int xoffset = var->xoffset;
>> +	int yoffset = var->yoffset;
>>  	int err = 0;
>>  
>>  	if (var->yoffset > 0) {
>> @@ -873,7 +875,8 @@ fb_pan_display(struct fb_info *info, struct fb_var_screeninfo *var)
>>  
>>  	if (err || !info->fbops->fb_pan_display ||
>>  	    var->yoffset + yres > info->var.yres_virtual ||
>> -	    var->xoffset + info->var.xres > info->var.xres_virtual)
>> +	    var->xoffset + info->var.xres > info->var.xres_virtual ||
>> +	    xoffset < 0 || yoffset < 0)
>>     
>
> Well negative xoffset/yoffset don't really exist so what you're
> essentially checking is whether offset+res overflows. Your check will
> not catch all overflows though. xres/yres would have to be huge
> (> 2^31) to cause such overflows though so your check should catch all
> cases that can happen in practice. However I think it would be better
> to make the overflow check clearer (eg. 'offset + res < res').
>
>   

Re: [Linux-fbdev-devel] [Bugme-new] [Bug 13566] New: nvidiafb doesn't get my oooold monitor working

[eric m. <eri...@gm...>]

Tnx!

2009/6/29 Andrew Morton <ak...@li...>

>
> (switched to email.  Please respond via emailed reply-to-all, not via the
> bugzilla web interface).
>
> On Thu, 18 Jun 2009 13:04:12 GMT
> bug...@bu... wrote:
>
> > http://bugzilla.kernel.org/show_bug.cgi?id=13566
> >
> >            Summary: nvidiafb doesn't get my oooold monitor working
> >            Product: Drivers
> >            Version: 2.5
> >     Kernel Version: 2.6.30
> >           Platform: All
> >         OS/Version: Linux
> >               Tree: Mainline
> >             Status: NEW
> >           Severity: normal
> >           Priority: P1
> >          Component: Video(Other)
> >         AssignedTo: dri...@ke...
> >         ReportedBy: eri...@gm...
> >         Regression: No
>
> There's more info at the above link
>
> >
> > Nvidiafb doesn't get my ooooooold black & white 7" CRT VGA monitor
> working. I
> > have an GeForce 6200 one:
> >
> > root@slackade:~# lspci  | grep -i vga
> > 01:00.0 VGA compatible controller: nVidia Corporation NV44 [GeForce 6200
> > TurboCache(TM)] (rev a1)
> >
> >
> > This is the dmesg output with this old monitor ( or without any ) plugged
> to
> > the VGA output:
> >
> > root@slackade:~# dmesg | grep nvidia
> > nvidiafb 0000:01:00.0: PCI INT A -> GSI 18 (level, low) -> IRQ 18
> > nvidiafb: Device ID: 10de0161
> > nvidiafb: CRTC0 analog not found
> > nvidiafb: CRTC1 analog not found
> > nvidiafb: CRTC 1 is currently programmed for TV
> > nvidiafb: Using TV on CRTC 1
> > nvidiafb: Panel is TMDS
> > nvidiafb: MTRR set to ON
> > nvidiafb: Flat panel dithering disabled
> > nvidiafb: PCI nVidia NV16 framebuffer (64MB @ 0xD0000000)
> > root@slackade:~#
> >
> > After that, even if I switch to a brand new 1080p lcd the screen just
> blinks
> > with weird vertical stripes.
> >
> > If I reboot with a newer monitor plugged to VGA output all works fine:
> >
> > root@slackade:~# dmesg | grep nvidia
> > nvidiafb 0000:01:00.0: PCI INT A -> GSI 18 (level, low) -> IRQ 18
> > nvidiafb: Device ID: 10de0161
> > nvidiafb: CRTC0 analog found
> > nvidiafb: CRTC1 analog not found
> > nvidiafb: CRTC 0 appears to have a CRT attached
> > nvidiafb: Using CRT on CRTC 0
> > nvidiafb: MTRR set to ON
> > nvidiafb: PCI nVidia NV16 framebuffer (64MB @ 0xD0000000)
> > root@slackade:~#
> >
> > Tnx in advance!
> >
>
> hm.  drivers/video/nvidia/ isn't exactly a hive of development activity
> but let's switch this over to the mailing list and see if there's any
> help.
>
>

Re: [Linux-fbdev-devel] Framebuffer support for HTC Dream

[Dima Z. <di...@an...>]

Pavel,

Thanks for doing the clean up pass, it was long overdue.

>> > So you didn't wrote the code?
>> >
>> >> This adds support for framebuffer on HTC Dream smartphone (aka
>> >> T-Mobile G1, aka ADP1).
>> >>
>> >> Signed-off-by: Pavel Machek <pa...@uc...>
>> >> Cc: Brian Swetland <swe...@go...>
>> >
>> > Someone did.  Are the signoffs and attributions correct and
>> > appropriate?  Should we at least mention the driver's history in the
>> > changelog?

The patch (though it was probably several patches) in our msm tree had
the proper author attribution (Rebecca Schultz Zavin
<re...@an...>), so I think it would make the most sense to
keep that information.

>> > Will it have a maintainer?
>>
>> I did the original quick and dirty version for bringup.  Rebecca took
>> over and (re)wrote the bulk of the driver, getting things stable for
>> production ship of Dream and Sapphire, and Dima is currently adding
>> support for later Qualcomm chipsets (QSD8x50, etc).  Looping them into
>> this discussion.
>
> I can maintain it if noone else steps up. Of course, someone who
> actually knows the hw/has the docs would be preferable.

As Brian mentioned, I'm the last one to touch it here, so I now own
it. I've done a bunch refactoring to add support for the qsd8x50
devices. I'll post those up onto our experimental git tree (hopefully
sometime today), and once this patch goes in, I'll make sure that we
apply cleanly against it. Alternatively, if you like, I can
incorporate your comments into the refactoring work I'm doing, and can
push out the combined patch. In the future though, I'll try to be a
lot more aggressive at sending these out for review earlier so you
don't have to clean up our mess.

Please feel free to CC Rebecca and myself on all the msm_fb related
changes/discussions.

>> It would probably be worth referring to drivers like this as "for
>> Qualcomm MSM/QSD SoCs" or the like, since they do work with a lot of
>> hardware beyond just Dream.
>
> Well, the Dream is why I'm doing it, hence patch title. Of course,
> Kconfig should say 'Qualcomm MSM/QSD SoCs', too.

I second the request that the patches for qualcomm msm7k/qsd8k generic
support would have descriptions that refer to them as such, since the
htc dream specific code is only in the board files in
arch/arm/mach-msm. Note that the HTC Magic (aka the Ion, myTouch 3G,
etc.) uses the exact same fb code (i.e. it's also using the msm7201a
chipset). Mentioning in the body of the patch message that this is the
chipset used in the HTC Dream definitely makes sense, but the main
description should really refer to these as adding generic msm7k
support.

Thanks again for pushing this stuff up. Your help is much appreciated.

--Dima

> Sorry for world record in checkpatch warnings. I checked .c files, but
> somehow forgot about .h files.
>                                                                        Pavel
>
> ---
>
> Fix checkpatch warnings in HTC Dream display driver.
>
> Signed-off-by: Pavel Machek <pa...@uc...>
>
> diff --git a/drivers/video/msm/mddi_hw.h b/drivers/video/msm/mddi_hw.h
> index 0cb55eb..45cc01f 100644
> --- a/drivers/video/msm/mddi_hw.h
> +++ b/drivers/video/msm/mddi_hw.h
> @@ -199,39 +199,39 @@ struct __attribute__((packed)) mddi_video_stream {
>        uint16_t client_id; /* 0 */
>
>        uint16_t video_data_format_descriptor;
> -       /* format of each pixel in the Pixel Data in the present stream in the
> -        * present packet.
> -        * If bits [15:13] = 000 monochrome
> -        * If bits [15:13] = 001 color pixels (palette).
> -        * If bits [15:13] = 010 color pixels in raw RGB
> -        * If bits [15:13] = 011 data in 4:2:2 Y Cb Cr format
> -        * If bits [15:13] = 100 Bayer pixels
> -        */
> +/* format of each pixel in the Pixel Data in the present stream in the
> + * present packet.
> + * If bits [15:13] = 000 monochrome
> + * If bits [15:13] = 001 color pixels (palette).
> + * If bits [15:13] = 010 color pixels in raw RGB
> + * If bits [15:13] = 011 data in 4:2:2 Y Cb Cr format
> + * If bits [15:13] = 100 Bayer pixels
> + */
>
>        uint16_t pixel_data_attributes;
> -       /* interpreted as follows:
> -        * Bits [1:0] = 11  pixel data is displayed to both eyes
> -        * Bits [1:0] = 10  pixel data is routed to the left eye only.
> -        * Bits [1:0] = 01  pixel data is routed to the right eye only.
> -        * Bits [1:0] = 00  pixel data is routed to the alternate display.
> -        * Bit 2 is 0  Pixel Data is in the standard progressive format.
> -        * Bit 2 is 1  Pixel Data is in interlace format.
> -        * Bit 3 is 0  Pixel Data is in the standard progressive format.
> -        * Bit 3 is 1  Pixel Data is in alternate pixel format.
> -        * Bit 4 is 0  Pixel Data is to or from the display frame buffer.
> -        * Bit 4 is 1  Pixel Data is to or from the camera.
> -        * Bit 5 is 0  pixel data contains the next consecutive row of pixels.
> -        * Bit 5 is 1  X Left Edge, Y Top Edge, X Right Edge, Y Bottom Edge,
> -        *             X Start, and Y Start parameters are not defined and
> -        *             shall be ignored by the client.
> -        * Bits [7:6] = 01  Pixel data is written to the offline image buffer.
> -        * Bits [7:6] = 00  Pixel data is written to the buffer to refresh display.
> -        * Bits [7:6] = 11  Pixel data is written to all image buffers.
> -        * Bits [7:6] = 10  Invalid. Reserved for future use.
> -        * Bits 8 through 11 alternate display number.
> -        * Bits 12 through 14 are reserved for future use and shall be set to zero.
> -        * Bit 15 is 1 the row of pixels is the last row of pixels in a frame.
> -        */
> +/* interpreted as follows:
> + * Bits [1:0] = 11  pixel data is displayed to both eyes
> + * Bits [1:0] = 10  pixel data is routed to the left eye only.
> + * Bits [1:0] = 01  pixel data is routed to the right eye only.
> + * Bits [1:0] = 00  pixel data is routed to the alternate display.
> + * Bit 2 is 0  Pixel Data is in the standard progressive format.
> + * Bit 2 is 1  Pixel Data is in interlace format.
> + * Bit 3 is 0  Pixel Data is in the standard progressive format.
> + * Bit 3 is 1  Pixel Data is in alternate pixel format.
> + * Bit 4 is 0  Pixel Data is to or from the display frame buffer.
> + * Bit 4 is 1  Pixel Data is to or from the camera.
> + * Bit 5 is 0  pixel data contains the next consecutive row of pixels.
> + * Bit 5 is 1  X Left Edge, Y Top Edge, X Right Edge, Y Bottom Edge,
> + *             X Start, and Y Start parameters are not defined and
> + *             shall be ignored by the client.
> + * Bits [7:6] = 01  Pixel data is written to the offline image buffer.
> + * Bits [7:6] = 00  Pixel data is written to the buffer to refresh display.
> + * Bits [7:6] = 11  Pixel data is written to all image buffers.
> + * Bits [7:6] = 10  Invalid. Reserved for future use.
> + * Bits 8 through 11 alternate display number.
> + * Bits 12 through 14 are reserved for future use and shall be set to zero.
> + * Bit 15 is 1 the row of pixels is the last row of pixels in a frame.
> + */
>
>        uint16_t x_left_edge;
>        uint16_t y_top_edge;
> @@ -239,17 +239,19 @@ struct __attribute__((packed)) mddi_video_stream {
>
>        uint16_t x_right_edge;
>        uint16_t y_bottom_edge;
> -       /*  X,Y coordinate of the bottom right edge of the window being updated. */
> +       /* X,Y coordinate of the bottom right edge of the window being
> +        * updated. */
>
>        uint16_t x_start;
>        uint16_t y_start;
> -       /*  (X Start, Y Start) is the first pixel in the Pixel Data field below. */
> +       /* (X Start, Y Start) is the first pixel in the Pixel Data field
> +        * below. */
>
>        uint16_t pixel_count;
> -       /*  number of pixels in the Pixel Data field below. */
> +       /* number of pixels in the Pixel Data field below. */
>
>        uint16_t parameter_CRC;
> -       /*  16-bit CRC of all bytes from the Packet Length to the Pixel Count. */
> +       /* 16-bit CRC of all bytes from the Packet Length to the Pixel Count. */
>
>        uint16_t reserved;
>        /* 16-bit variable to make structure align on 4 byte boundary */
> diff --git a/drivers/video/msm/mdp_hw.h b/drivers/video/msm/mdp_hw.h
> index d78dafa..4e3deb4 100644
> --- a/drivers/video/msm/mdp_hw.h
> +++ b/drivers/video/msm/mdp_hw.h
> @@ -20,7 +20,7 @@
>
>  struct mdp_info {
>        struct mdp_device mdp_dev;
> -       char* __iomem base;
> +       char * __iomem base;
>        int irq;
>  };
>  struct mdp_blit_req;
> @@ -32,149 +32,149 @@ int mdp_ppp_blit(const struct mdp_info *mdp, struct mdp_blit_req *req,
>  #define mdp_writel(mdp, value, offset) writel(value, mdp->base + offset)
>  #define mdp_readl(mdp, offset) readl(mdp->base + offset)
>
> -#define MDP_SYNC_CONFIG_0                ( 0x00000)
> -#define MDP_SYNC_CONFIG_1                ( 0x00004)
> -#define MDP_SYNC_CONFIG_2                ( 0x00008)
> -#define MDP_SYNC_STATUS_0                ( 0x0000c)
> -#define MDP_SYNC_STATUS_1                ( 0x00010)
> -#define MDP_SYNC_STATUS_2                ( 0x00014)
> -#define MDP_SYNC_THRESH_0                ( 0x00018)
> -#define MDP_SYNC_THRESH_1                ( 0x0001c)
> -#define MDP_INTR_ENABLE                  ( 0x00020)
> -#define MDP_INTR_STATUS                  ( 0x00024)
> -#define MDP_INTR_CLEAR                   ( 0x00028)
> -#define MDP_DISPLAY0_START               ( 0x00030)
> -#define MDP_DISPLAY1_START               ( 0x00034)
> -#define MDP_DISPLAY_STATUS               ( 0x00038)
> -#define MDP_EBI2_LCD0                    ( 0x0003c)
> -#define MDP_EBI2_LCD1                    ( 0x00040)
> -#define MDP_DISPLAY0_ADDR                ( 0x00054)
> -#define MDP_DISPLAY1_ADDR                ( 0x00058)
> -#define MDP_EBI2_PORTMAP_MODE            ( 0x0005c)
> -#define MDP_MODE                         ( 0x00060)
> -#define MDP_TV_OUT_STATUS                ( 0x00064)
> -#define MDP_HW_VERSION                   ( 0x00070)
> -#define MDP_SW_RESET                     ( 0x00074)
> -#define MDP_AXI_ERROR_MASTER_STOP        ( 0x00078)
> -#define MDP_SEL_CLK_OR_HCLK_TEST_BUS     ( 0x0007c)
> -#define MDP_PRIMARY_VSYNC_OUT_CTRL       ( 0x00080)
> -#define MDP_SECONDARY_VSYNC_OUT_CTRL     ( 0x00084)
> -#define MDP_EXTERNAL_VSYNC_OUT_CTRL      ( 0x00088)
> -#define MDP_VSYNC_CTRL                   ( 0x0008c)
> -#define MDP_CGC_EN                       ( 0x00100)
> -#define MDP_CMD_STATUS                   ( 0x10008)
> -#define MDP_PROFILE_EN                   ( 0x10010)
> -#define MDP_PROFILE_COUNT                ( 0x10014)
> -#define MDP_DMA_START                    ( 0x10044)
> -#define MDP_FULL_BYPASS_WORD0            ( 0x10100)
> -#define MDP_FULL_BYPASS_WORD1            ( 0x10104)
> -#define MDP_COMMAND_CONFIG               ( 0x10104)
> -#define MDP_FULL_BYPASS_WORD2            ( 0x10108)
> -#define MDP_FULL_BYPASS_WORD3            ( 0x1010c)
> -#define MDP_FULL_BYPASS_WORD4            ( 0x10110)
> -#define MDP_FULL_BYPASS_WORD6            ( 0x10118)
> -#define MDP_FULL_BYPASS_WORD7            ( 0x1011c)
> -#define MDP_FULL_BYPASS_WORD8            ( 0x10120)
> -#define MDP_FULL_BYPASS_WORD9            ( 0x10124)
> -#define MDP_PPP_SOURCE_CONFIG            ( 0x10124)
> -#define MDP_FULL_BYPASS_WORD10           ( 0x10128)
> -#define MDP_FULL_BYPASS_WORD11           ( 0x1012c)
> -#define MDP_FULL_BYPASS_WORD12           ( 0x10130)
> -#define MDP_FULL_BYPASS_WORD13           ( 0x10134)
> -#define MDP_FULL_BYPASS_WORD14           ( 0x10138)
> -#define MDP_PPP_OPERATION_CONFIG         ( 0x10138)
> -#define MDP_FULL_BYPASS_WORD15           ( 0x1013c)
> -#define MDP_FULL_BYPASS_WORD16           ( 0x10140)
> -#define MDP_FULL_BYPASS_WORD17           ( 0x10144)
> -#define MDP_FULL_BYPASS_WORD18           ( 0x10148)
> -#define MDP_FULL_BYPASS_WORD19           ( 0x1014c)
> -#define MDP_FULL_BYPASS_WORD20           ( 0x10150)
> -#define MDP_PPP_DESTINATION_CONFIG       ( 0x10150)
> -#define MDP_FULL_BYPASS_WORD21           ( 0x10154)
> -#define MDP_FULL_BYPASS_WORD22           ( 0x10158)
> -#define MDP_FULL_BYPASS_WORD23           ( 0x1015c)
> -#define MDP_FULL_BYPASS_WORD24           ( 0x10160)
> -#define MDP_FULL_BYPASS_WORD25           ( 0x10164)
> -#define MDP_FULL_BYPASS_WORD26           ( 0x10168)
> -#define MDP_FULL_BYPASS_WORD27           ( 0x1016c)
> -#define MDP_FULL_BYPASS_WORD29           ( 0x10174)
> -#define MDP_FULL_BYPASS_WORD30           ( 0x10178)
> -#define MDP_FULL_BYPASS_WORD31           ( 0x1017c)
> -#define MDP_FULL_BYPASS_WORD32           ( 0x10180)
> -#define MDP_DMA_CONFIG                   ( 0x10180)
> -#define MDP_FULL_BYPASS_WORD33           ( 0x10184)
> -#define MDP_FULL_BYPASS_WORD34           ( 0x10188)
> -#define MDP_FULL_BYPASS_WORD35           ( 0x1018c)
> -#define MDP_FULL_BYPASS_WORD37           ( 0x10194)
> -#define MDP_FULL_BYPASS_WORD39           ( 0x1019c)
> -#define MDP_FULL_BYPASS_WORD40           ( 0x101a0)
> -#define MDP_FULL_BYPASS_WORD41           ( 0x101a4)
> -#define MDP_FULL_BYPASS_WORD43           ( 0x101ac)
> -#define MDP_FULL_BYPASS_WORD46           ( 0x101b8)
> -#define MDP_FULL_BYPASS_WORD47           ( 0x101bc)
> -#define MDP_FULL_BYPASS_WORD48           ( 0x101c0)
> -#define MDP_FULL_BYPASS_WORD49           ( 0x101c4)
> -#define MDP_FULL_BYPASS_WORD50           ( 0x101c8)
> -#define MDP_FULL_BYPASS_WORD51           ( 0x101cc)
> -#define MDP_FULL_BYPASS_WORD52           ( 0x101d0)
> -#define MDP_FULL_BYPASS_WORD53           ( 0x101d4)
> -#define MDP_FULL_BYPASS_WORD54           ( 0x101d8)
> -#define MDP_FULL_BYPASS_WORD55           ( 0x101dc)
> -#define MDP_FULL_BYPASS_WORD56           ( 0x101e0)
> -#define MDP_FULL_BYPASS_WORD57           ( 0x101e4)
> -#define MDP_FULL_BYPASS_WORD58           ( 0x101e8)
> -#define MDP_FULL_BYPASS_WORD59           ( 0x101ec)
> -#define MDP_FULL_BYPASS_WORD60           ( 0x101f0)
> -#define MDP_VSYNC_THRESHOLD              ( 0x101f0)
> -#define MDP_FULL_BYPASS_WORD61           ( 0x101f4)
> -#define MDP_FULL_BYPASS_WORD62           ( 0x101f8)
> -#define MDP_FULL_BYPASS_WORD63           ( 0x101fc)
> -#define MDP_TFETCH_TEST_MODE             ( 0x20004)
> -#define MDP_TFETCH_STATUS                ( 0x20008)
> -#define MDP_TFETCH_TILE_COUNT            ( 0x20010)
> -#define MDP_TFETCH_FETCH_COUNT           ( 0x20014)
> -#define MDP_TFETCH_CONSTANT_COLOR        ( 0x20040)
> -#define MDP_CSC_BYPASS                   ( 0x40004)
> -#define MDP_SCALE_COEFF_LSB              ( 0x5fffc)
> -#define MDP_TV_OUT_CTL                   ( 0xc0000)
> -#define MDP_TV_OUT_FIR_COEFF             ( 0xc0004)
> -#define MDP_TV_OUT_BUF_ADDR              ( 0xc0008)
> -#define MDP_TV_OUT_CC_DATA               ( 0xc000c)
> -#define MDP_TV_OUT_SOBEL                 ( 0xc0010)
> -#define MDP_TV_OUT_Y_CLAMP               ( 0xc0018)
> -#define MDP_TV_OUT_CB_CLAMP              ( 0xc001c)
> -#define MDP_TV_OUT_CR_CLAMP              ( 0xc0020)
> -#define MDP_TEST_MODE_CLK                ( 0xd0000)
> -#define MDP_TEST_MISR_RESET_CLK          ( 0xd0004)
> -#define MDP_TEST_EXPORT_MISR_CLK         ( 0xd0008)
> -#define MDP_TEST_MISR_CURR_VAL_CLK       ( 0xd000c)
> -#define MDP_TEST_MODE_HCLK               ( 0xd0100)
> -#define MDP_TEST_MISR_RESET_HCLK         ( 0xd0104)
> -#define MDP_TEST_EXPORT_MISR_HCLK        ( 0xd0108)
> -#define MDP_TEST_MISR_CURR_VAL_HCLK      ( 0xd010c)
> -#define MDP_TEST_MODE_DCLK               ( 0xd0200)
> -#define MDP_TEST_MISR_RESET_DCLK         ( 0xd0204)
> -#define MDP_TEST_EXPORT_MISR_DCLK        ( 0xd0208)
> -#define MDP_TEST_MISR_CURR_VAL_DCLK      ( 0xd020c)
> -#define MDP_TEST_CAPTURED_DCLK           ( 0xd0210)
> -#define MDP_TEST_MISR_CAPT_VAL_DCLK      ( 0xd0214)
> -#define MDP_LCDC_CTL                     ( 0xe0000)
> -#define MDP_LCDC_HSYNC_CTL               ( 0xe0004)
> -#define MDP_LCDC_VSYNC_CTL               ( 0xe0008)
> -#define MDP_LCDC_ACTIVE_HCTL             ( 0xe000c)
> -#define MDP_LCDC_ACTIVE_VCTL             ( 0xe0010)
> -#define MDP_LCDC_BORDER_CLR              ( 0xe0014)
> -#define MDP_LCDC_H_BLANK                 ( 0xe0018)
> -#define MDP_LCDC_V_BLANK                 ( 0xe001c)
> -#define MDP_LCDC_UNDERFLOW_CLR           ( 0xe0020)
> -#define MDP_LCDC_HSYNC_SKEW              ( 0xe0024)
> -#define MDP_LCDC_TEST_CTL                ( 0xe0028)
> -#define MDP_LCDC_LINE_IRQ                ( 0xe002c)
> -#define MDP_LCDC_CTL_POLARITY            ( 0xe0030)
> -#define MDP_LCDC_DMA_CONFIG              ( 0xe1000)
> -#define MDP_LCDC_DMA_SIZE                ( 0xe1004)
> -#define MDP_LCDC_DMA_IBUF_ADDR           ( 0xe1008)
> -#define MDP_LCDC_DMA_IBUF_Y_STRIDE       ( 0xe100c)
> +#define MDP_SYNC_CONFIG_0                (0x00000)
> +#define MDP_SYNC_CONFIG_1                (0x00004)
> +#define MDP_SYNC_CONFIG_2                (0x00008)
> +#define MDP_SYNC_STATUS_0                (0x0000c)
> +#define MDP_SYNC_STATUS_1                (0x00010)
> +#define MDP_SYNC_STATUS_2                (0x00014)
> +#define MDP_SYNC_THRESH_0                (0x00018)
> +#define MDP_SYNC_THRESH_1                (0x0001c)
> +#define MDP_INTR_ENABLE                  (0x00020)
> +#define MDP_INTR_STATUS                  (0x00024)
> +#define MDP_INTR_CLEAR                   (0x00028)
> +#define MDP_DISPLAY0_START               (0x00030)
> +#define MDP_DISPLAY1_START               (0x00034)
> +#define MDP_DISPLAY_STATUS               (0x00038)
> +#define MDP_EBI2_LCD0                    (0x0003c)
> +#define MDP_EBI2_LCD1                    (0x00040)
> +#define MDP_DISPLAY0_ADDR                (0x00054)
> +#define MDP_DISPLAY1_ADDR                (0x00058)
> +#define MDP_EBI2_PORTMAP_MODE            (0x0005c)
> +#define MDP_MODE                         (0x00060)
> +#define MDP_TV_OUT_STATUS                (0x00064)
> +#define MDP_HW_VERSION                   (0x00070)
> +#define MDP_SW_RESET                     (0x00074)
> +#define MDP_AXI_ERROR_MASTER_STOP        (0x00078)
> +#define MDP_SEL_CLK_OR_HCLK_TEST_BUS     (0x0007c)
> +#define MDP_PRIMARY_VSYNC_OUT_CTRL       (0x00080)
> +#define MDP_SECONDARY_VSYNC_OUT_CTRL     (0x00084)
> +#define MDP_EXTERNAL_VSYNC_OUT_CTRL      (0x00088)
> +#define MDP_VSYNC_CTRL                   (0x0008c)
> +#define MDP_CGC_EN                       (0x00100)
> +#define MDP_CMD_STATUS                   (0x10008)
> +#define MDP_PROFILE_EN                   (0x10010)
> +#define MDP_PROFILE_COUNT                (0x10014)
> +#define MDP_DMA_START                    (0x10044)
> +#define MDP_FULL_BYPASS_WORD0            (0x10100)
> +#define MDP_FULL_BYPASS_WORD1            (0x10104)
> +#define MDP_COMMAND_CONFIG               (0x10104)
> +#define MDP_FULL_BYPASS_WORD2            (0x10108)
> +#define MDP_FULL_BYPASS_WORD3            (0x1010c)
> +#define MDP_FULL_BYPASS_WORD4            (0x10110)
> +#define MDP_FULL_BYPASS_WORD6            (0x10118)
> +#define MDP_FULL_BYPASS_WORD7            (0x1011c)
> +#define MDP_FULL_BYPASS_WORD8            (0x10120)
> +#define MDP_FULL_BYPASS_WORD9            (0x10124)
> +#define MDP_PPP_SOURCE_CONFIG            (0x10124)
> +#define MDP_FULL_BYPASS_WORD10           (0x10128)
> +#define MDP_FULL_BYPASS_WORD11           (0x1012c)
> +#define MDP_FULL_BYPASS_WORD12           (0x10130)
> +#define MDP_FULL_BYPASS_WORD13           (0x10134)
> +#define MDP_FULL_BYPASS_WORD14           (0x10138)
> +#define MDP_PPP_OPERATION_CONFIG         (0x10138)
> +#define MDP_FULL_BYPASS_WORD15           (0x1013c)
> +#define MDP_FULL_BYPASS_WORD16           (0x10140)
> +#define MDP_FULL_BYPASS_WORD17           (0x10144)
> +#define MDP_FULL_BYPASS_WORD18           (0x10148)
> +#define MDP_FULL_BYPASS_WORD19           (0x1014c)
> +#define MDP_FULL_BYPASS_WORD20           (0x10150)
> +#define MDP_PPP_DESTINATION_CONFIG       (0x10150)
> +#define MDP_FULL_BYPASS_WORD21           (0x10154)
> +#define MDP_FULL_BYPASS_WORD22           (0x10158)
> +#define MDP_FULL_BYPASS_WORD23           (0x1015c)
> +#define MDP_FULL_BYPASS_WORD24           (0x10160)
> +#define MDP_FULL_BYPASS_WORD25           (0x10164)
> +#define MDP_FULL_BYPASS_WORD26           (0x10168)
> +#define MDP_FULL_BYPASS_WORD27           (0x1016c)
> +#define MDP_FULL_BYPASS_WORD29           (0x10174)
> +#define MDP_FULL_BYPASS_WORD30           (0x10178)
> +#define MDP_FULL_BYPASS_WORD31           (0x1017c)
> +#define MDP_FULL_BYPASS_WORD32           (0x10180)
> +#define MDP_DMA_CONFIG                   (0x10180)
> +#define MDP_FULL_BYPASS_WORD33           (0x10184)
> +#define MDP_FULL_BYPASS_WORD34           (0x10188)
> +#define MDP_FULL_BYPASS_WORD35           (0x1018c)
> +#define MDP_FULL_BYPASS_WORD37           (0x10194)
> +#define MDP_FULL_BYPASS_WORD39           (0x1019c)
> +#define MDP_FULL_BYPASS_WORD40           (0x101a0)
> +#define MDP_FULL_BYPASS_WORD41           (0x101a4)
> +#define MDP_FULL_BYPASS_WORD43           (0x101ac)
> +#define MDP_FULL_BYPASS_WORD46           (0x101b8)
> +#define MDP_FULL_BYPASS_WORD47           (0x101bc)
> +#define MDP_FULL_BYPASS_WORD48           (0x101c0)
> +#define MDP_FULL_BYPASS_WORD49           (0x101c4)
> +#define MDP_FULL_BYPASS_WORD50           (0x101c8)
> +#define MDP_FULL_BYPASS_WORD51           (0x101cc)
> +#define MDP_FULL_BYPASS_WORD52           (0x101d0)
> +#define MDP_FULL_BYPASS_WORD53           (0x101d4)
> +#define MDP_FULL_BYPASS_WORD54           (0x101d8)
> +#define MDP_FULL_BYPASS_WORD55           (0x101dc)
> +#define MDP_FULL_BYPASS_WORD56           (0x101e0)
> +#define MDP_FULL_BYPASS_WORD57           (0x101e4)
> +#define MDP_FULL_BYPASS_WORD58           (0x101e8)
> +#define MDP_FULL_BYPASS_WORD59           (0x101ec)
> +#define MDP_FULL_BYPASS_WORD60           (0x101f0)
> +#define MDP_VSYNC_THRESHOLD              (0x101f0)
> +#define MDP_FULL_BYPASS_WORD61           (0x101f4)
> +#define MDP_FULL_BYPASS_WORD62           (0x101f8)
> +#define MDP_FULL_BYPASS_WORD63           (0x101fc)
> +#define MDP_TFETCH_TEST_MODE             (0x20004)
> +#define MDP_TFETCH_STATUS                (0x20008)
> +#define MDP_TFETCH_TILE_COUNT            (0x20010)
> +#define MDP_TFETCH_FETCH_COUNT           (0x20014)
> +#define MDP_TFETCH_CONSTANT_COLOR        (0x20040)
> +#define MDP_CSC_BYPASS                   (0x40004)
> +#define MDP_SCALE_COEFF_LSB              (0x5fffc)
> +#define MDP_TV_OUT_CTL                   (0xc0000)
> +#define MDP_TV_OUT_FIR_COEFF             (0xc0004)
> +#define MDP_TV_OUT_BUF_ADDR              (0xc0008)
> +#define MDP_TV_OUT_CC_DATA               (0xc000c)
> +#define MDP_TV_OUT_SOBEL                 (0xc0010)
> +#define MDP_TV_OUT_Y_CLAMP               (0xc0018)
> +#define MDP_TV_OUT_CB_CLAMP              (0xc001c)
> +#define MDP_TV_OUT_CR_CLAMP              (0xc0020)
> +#define MDP_TEST_MODE_CLK                (0xd0000)
> +#define MDP_TEST_MISR_RESET_CLK          (0xd0004)
> +#define MDP_TEST_EXPORT_MISR_CLK         (0xd0008)
> +#define MDP_TEST_MISR_CURR_VAL_CLK       (0xd000c)
> +#define MDP_TEST_MODE_HCLK               (0xd0100)
> +#define MDP_TEST_MISR_RESET_HCLK         (0xd0104)
> +#define MDP_TEST_EXPORT_MISR_HCLK        (0xd0108)
> +#define MDP_TEST_MISR_CURR_VAL_HCLK      (0xd010c)
> +#define MDP_TEST_MODE_DCLK               (0xd0200)
> +#define MDP_TEST_MISR_RESET_DCLK         (0xd0204)
> +#define MDP_TEST_EXPORT_MISR_DCLK        (0xd0208)
> +#define MDP_TEST_MISR_CURR_VAL_DCLK      (0xd020c)
> +#define MDP_TEST_CAPTURED_DCLK           (0xd0210)
> +#define MDP_TEST_MISR_CAPT_VAL_DCLK      (0xd0214)
> +#define MDP_LCDC_CTL                     (0xe0000)
> +#define MDP_LCDC_HSYNC_CTL               (0xe0004)
> +#define MDP_LCDC_VSYNC_CTL               (0xe0008)
> +#define MDP_LCDC_ACTIVE_HCTL             (0xe000c)
> +#define MDP_LCDC_ACTIVE_VCTL             (0xe0010)
> +#define MDP_LCDC_BORDER_CLR              (0xe0014)
> +#define MDP_LCDC_H_BLANK                 (0xe0018)
> +#define MDP_LCDC_V_BLANK                 (0xe001c)
> +#define MDP_LCDC_UNDERFLOW_CLR           (0xe0020)
> +#define MDP_LCDC_HSYNC_SKEW              (0xe0024)
> +#define MDP_LCDC_TEST_CTL                (0xe0028)
> +#define MDP_LCDC_LINE_IRQ                (0xe002c)
> +#define MDP_LCDC_CTL_POLARITY            (0xe0030)
> +#define MDP_LCDC_DMA_CONFIG              (0xe1000)
> +#define MDP_LCDC_DMA_SIZE                (0xe1004)
> +#define MDP_LCDC_DMA_IBUF_ADDR           (0xe1008)
> +#define MDP_LCDC_DMA_IBUF_Y_STRIDE       (0xe100c)
>
>
>  #define MDP_DMA2_TERM 0x1
> @@ -246,11 +246,11 @@ int mdp_ppp_blit(const struct mdp_info *mdp, struct mdp_blit_req *req,
>  /* MDP_VSYNC_CTRL */
>  #define DISP0_VSYNC_MAP_VSYNC0 0
>  #define DISP0_VSYNC_MAP_VSYNC1 (1<<0)
> -#define DISP0_VSYNC_MAP_VSYNC2 (1<<0)|(1<<1)
> +#define DISP0_VSYNC_MAP_VSYNC2 ((1<<0)|(1<<1))
>
>  #define DISP1_VSYNC_MAP_VSYNC0 0
>  #define DISP1_VSYNC_MAP_VSYNC1 (1<<2)
> -#define DISP1_VSYNC_MAP_VSYNC2 (1<<2)|(1<<3)
> +#define DISP1_VSYNC_MAP_VSYNC2 ((1<<2)|(1<<3))
>
>  #define PRIMARY_LCD_SYNC_EN (1<<4)
>  #define PRIMARY_LCD_SYNC_DISABLE 0
> @@ -368,7 +368,7 @@ int mdp_ppp_blit(const struct mdp_info *mdp, struct mdp_blit_req *req,
>  #define PPP_OP_BG_CHROMA_RGB 0
>  #define PPP_OP_BG_CHROMA_H2V1 (1<<25)
>  #define PPP_OP_BG_CHROMA_H1V2 (1<<26)
> -#define PPP_OP_BG_CHROMA_420 (1<<25)|(1<<26)
> +#define PPP_OP_BG_CHROMA_420 ((1<<25)|(1<<26))
>  #define PPP_OP_BG_CHROMA_SITE_COSITE 0
>  #define PPP_OP_BG_CHROMA_SITE_OFFSITE (1<<27)
>
> @@ -417,25 +417,25 @@ int mdp_ppp_blit(const struct mdp_info *mdp, struct mdp_blit_req *req,
>  #define PPP_DST_MDDI_EXTERNAL (1<<22)
>
>  /* image configurations by image type */
> -#define PPP_CFG_MDP_RGB_565(dir)       PPP_##dir##_C2R_5BIT | \
> +#define PPP_CFG_MDP_RGB_565(dir)       (PPP_##dir##_C2R_5BIT | \
>                                        PPP_##dir##_C0G_6BIT | \
>                                        PPP_##dir##_C1B_5BIT | \
>                                        PPP_##dir##_BPP_2BYTES | \
>                                        PPP_##dir##_INTERLVD_3COMPONENTS | \
>                                        PPP_##dir##_PACK_TIGHT | \
>                                        PPP_##dir##_PACK_ALIGN_LSB | \
> -                                       PPP_##dir##_PLANE_INTERLVD
> +                                       PPP_##dir##_PLANE_INTERLVD)
>
> -#define PPP_CFG_MDP_RGB_888(dir)       PPP_##dir##_C2R_8BIT | \
> +#define PPP_CFG_MDP_RGB_888(dir)       (PPP_##dir##_C2R_8BIT | \
>                                        PPP_##dir##_C0G_8BIT | \
>                                        PPP_##dir##_C1B_8BIT | \
>                                        PPP_##dir##_BPP_3BYTES | \
>                                        PPP_##dir##_INTERLVD_3COMPONENTS | \
>                                        PPP_##dir##_PACK_TIGHT | \
>                                        PPP_##dir##_PACK_ALIGN_LSB | \
> -                                       PPP_##dir##_PLANE_INTERLVD
> +                                       PPP_##dir##_PLANE_INTERLVD)
>
> -#define PPP_CFG_MDP_ARGB_8888(dir)     PPP_##dir##_C2R_8BIT | \
> +#define PPP_CFG_MDP_ARGB_8888(dir)     (PPP_##dir##_C2R_8BIT | \
>                                        PPP_##dir##_C0G_8BIT | \
>                                        PPP_##dir##_C1B_8BIT | \
>                                        PPP_##dir##_C3A_8BIT | \
> @@ -444,13 +444,13 @@ int mdp_ppp_blit(const struct mdp_info *mdp, struct mdp_blit_req *req,
>                                        PPP_##dir##_INTERLVD_4COMPONENTS | \
>                                        PPP_##dir##_PACK_TIGHT | \
>                                        PPP_##dir##_PACK_ALIGN_LSB | \
> -                                       PPP_##dir##_PLANE_INTERLVD
> +                                       PPP_##dir##_PLANE_INTERLVD)
>
>  #define PPP_CFG_MDP_XRGB_8888(dir) PPP_CFG_MDP_ARGB_8888(dir)
>  #define PPP_CFG_MDP_RGBA_8888(dir) PPP_CFG_MDP_ARGB_8888(dir)
>  #define PPP_CFG_MDP_BGRA_8888(dir) PPP_CFG_MDP_ARGB_8888(dir)
>
> -#define PPP_CFG_MDP_Y_CBCR_H2V2(dir)   PPP_##dir##_C2R_8BIT | \
> +#define PPP_CFG_MDP_Y_CBCR_H2V2(dir)   (PPP_##dir##_C2R_8BIT | \
>                                        PPP_##dir##_C0G_8BIT | \
>                                        PPP_##dir##_C1B_8BIT | \
>                                        PPP_##dir##_C3A_8BIT | \
> @@ -458,11 +458,11 @@ int mdp_ppp_blit(const struct mdp_info *mdp, struct mdp_blit_req *req,
>                                        PPP_##dir##_INTERLVD_2COMPONENTS | \
>                                        PPP_##dir##_PACK_TIGHT | \
>                                        PPP_##dir##_PACK_ALIGN_LSB | \
> -                                       PPP_##dir##_PLANE_PSEUDOPLNR
> +                                       PPP_##dir##_PLANE_PSEUDOPLNR)
>
>  #define PPP_CFG_MDP_Y_CRCB_H2V2(dir)   PPP_CFG_MDP_Y_CBCR_H2V2(dir)
>
> -#define PPP_CFG_MDP_YCRYCB_H2V1(dir)   PPP_##dir##_C2R_8BIT | \
> +#define PPP_CFG_MDP_YCRYCB_H2V1(dir)   (PPP_##dir##_C2R_8BIT | \
>                                        PPP_##dir##_C0G_8BIT | \
>                                        PPP_##dir##_C1B_8BIT | \
>                                        PPP_##dir##_C3A_8BIT | \
> @@ -470,9 +470,9 @@ int mdp_ppp_blit(const struct mdp_info *mdp, struct mdp_blit_req *req,
>                                        PPP_##dir##_INTERLVD_4COMPONENTS | \
>                                        PPP_##dir##_PACK_TIGHT | \
>                                        PPP_##dir##_PACK_ALIGN_LSB |\
> -                                       PPP_##dir##_PLANE_INTERLVD
> +                                       PPP_##dir##_PLANE_INTERLVD)
>
> -#define PPP_CFG_MDP_Y_CBCR_H2V1(dir)   PPP_##dir##_C2R_8BIT | \
> +#define PPP_CFG_MDP_Y_CBCR_H2V1(dir)   (PPP_##dir##_C2R_8BIT | \
>                                        PPP_##dir##_C0G_8BIT | \
>                                        PPP_##dir##_C1B_8BIT | \
>                                        PPP_##dir##_C3A_8BIT | \
> @@ -480,7 +480,7 @@ int mdp_ppp_blit(const struct mdp_info *mdp, struct mdp_blit_req *req,
>                                        PPP_##dir##_INTERLVD_2COMPONENTS |  \
>                                        PPP_##dir##_PACK_TIGHT | \
>                                        PPP_##dir##_PACK_ALIGN_LSB | \
> -                                       PPP_##dir##_PLANE_PSEUDOPLNR
> +                                       PPP_##dir##_PLANE_PSEUDOPLNR)
>
>  #define PPP_CFG_MDP_Y_CRCB_H2V1(dir)   PPP_CFG_MDP_Y_CBCR_H2V1(dir)
>
> @@ -549,7 +549,7 @@ int mdp_ppp_blit(const struct mdp_info *mdp, struct mdp_blit_req *req,
>                     (img == MDP_ARGB_8888) | (img == MDP_RGBA_8888) | \
>                     (img == MDP_XRGB_8888) | (img == MDP_BGRA_8888))
>  #define HAS_ALPHA(img) ((img == MDP_ARGB_8888) | (img == MDP_RGBA_8888) | \
> -                       (img == MDP_BGRA_8888))
> +                       (img == MDP_BGRA_8888))
>
>  #define IS_PSEUDOPLNR(img) ((img == MDP_Y_CRCB_H2V2) | \
>                            (img == MDP_Y_CBCR_H2V2) | \
> diff --git a/drivers/video/msm/mdp_scale_tables.h b/drivers/video/msm/mdp_scale_tables.h
> index 4e19a25..34077b1 100644
> --- a/drivers/video/msm/mdp_scale_tables.h
> +++ b/drivers/video/msm/mdp_scale_tables.h
> @@ -31,8 +31,8 @@ enum {
>        MDP_DOWNSCALE_MAX,
>  };
>
> -extern struct mdp_table_entry* mdp_downscale_x_table[MDP_DOWNSCALE_MAX];
> -extern struct mdp_table_entry* mdp_downscale_y_table[MDP_DOWNSCALE_MAX];
> +extern struct mdp_table_entry *mdp_downscale_x_table[MDP_DOWNSCALE_MAX];
> +extern struct mdp_table_entry *mdp_downscale_y_table[MDP_DOWNSCALE_MAX];
>  extern struct mdp_table_entry mdp_gaussian_blur_table[];
>
> -#endif  //_MDP_SCALE_TABLES_H_
> +#endif
>
>
>
>
> --
> (english) http://www.livejournal.com/~pavelmachek
> (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
> --
> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
> the body of a message to maj...@vg...
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> Please read the FAQ at  http://www.tux.org/lkml/
>

Re: [Linux-fbdev-devel] [Bugme-new] [Bug 13566] New: nvidiafb doesn't get my oooold monitor working

[Andrew M. <ak...@li...>]

(switched to email.  Please respond via emailed reply-to-all, not via the
bugzilla web interface).

On Thu, 18 Jun 2009 13:04:12 GMT
bug...@bu... wrote:

> http://bugzilla.kernel.org/show_bug.cgi?id=13566
> 
>            Summary: nvidiafb doesn't get my oooold monitor working
>            Product: Drivers
>            Version: 2.5
>     Kernel Version: 2.6.30
>           Platform: All
>         OS/Version: Linux
>               Tree: Mainline
>             Status: NEW
>           Severity: normal
>           Priority: P1
>          Component: Video(Other)
>         AssignedTo: dri...@ke...
>         ReportedBy: eri...@gm...
>         Regression: No

There's more info at the above link

> 
> Nvidiafb doesn't get my ooooooold black & white 7" CRT VGA monitor working. I
> have an GeForce 6200 one:
> 
> root@slackade:~# lspci  | grep -i vga
> 01:00.0 VGA compatible controller: nVidia Corporation NV44 [GeForce 6200
> TurboCache(TM)] (rev a1)
> 
> 
> This is the dmesg output with this old monitor ( or without any ) plugged to
> the VGA output:
> 
> root@slackade:~# dmesg | grep nvidia
> nvidiafb 0000:01:00.0: PCI INT A -> GSI 18 (level, low) -> IRQ 18
> nvidiafb: Device ID: 10de0161 
> nvidiafb: CRTC0 analog not found
> nvidiafb: CRTC1 analog not found
> nvidiafb: CRTC 1 is currently programmed for TV
> nvidiafb: Using TV on CRTC 1
> nvidiafb: Panel is TMDS
> nvidiafb: MTRR set to ON
> nvidiafb: Flat panel dithering disabled
> nvidiafb: PCI nVidia NV16 framebuffer (64MB @ 0xD0000000)
> root@slackade:~# 
> 
> After that, even if I switch to a brand new 1080p lcd the screen just blinks
> with weird vertical stripes.
> 
> If I reboot with a newer monitor plugged to VGA output all works fine:
> 
> root@slackade:~# dmesg | grep nvidia
> nvidiafb 0000:01:00.0: PCI INT A -> GSI 18 (level, low) -> IRQ 18
> nvidiafb: Device ID: 10de0161 
> nvidiafb: CRTC0 analog found
> nvidiafb: CRTC1 analog not found
> nvidiafb: CRTC 0 appears to have a CRT attached
> nvidiafb: Using CRT on CRTC 0
> nvidiafb: MTRR set to ON
> nvidiafb: PCI nVidia NV16 framebuffer (64MB @ 0xD0000000)
> root@slackade:~# 
> 
> Tnx in advance!
> 

hm.  drivers/video/nvidia/ isn't exactly a hive of development activity
but let's switch this over to the mailing list and see if there's any
help.

Re: [Linux-fbdev-devel] Framebuffer support for HTC Dream

[Pavel M. <pa...@uc...>]

On Mon 2009-06-29 13:00:33, Brian Swetland wrote:
> On Mon, Jun 29, 2009 at 12:38 PM, Andrew
> Morton<ak...@li...> wrote:
> > On Mon, 29 Jun 2009 13:10:30 +0200
> > Pavel Machek <pa...@uc...> wrote:
> >> I cleaned up dead code, a lot of debugging infastructure and horrific
> >> logo code. I had to remove earlysuspend support, because neccessary
> >> headers are not in mainline. The driver still works :-).
> >
> > So you didn't wrote the code?
> >
> >> This adds support for framebuffer on HTC Dream smartphone (aka
> >> T-Mobile G1, aka ADP1).
> >>
> >> Signed-off-by: Pavel Machek <pa...@uc...>
> >> Cc: Brian Swetland <swe...@go...>
> >
> > Someone did.  Are the signoffs and attributions correct and
> > appropriate?  Should we at least mention the driver's history in the
> > changelog?

> > Will it have a maintainer?
> 
> I did the original quick and dirty version for bringup.  Rebecca took
> over and (re)wrote the bulk of the driver, getting things stable for
> production ship of Dream and Sapphire, and Dima is currently adding
> support for later Qualcomm chipsets (QSD8x50, etc).  Looping them into
> this discussion.

I can maintain it if noone else steps up. Of course, someone who
actually knows the hw/has the docs would be preferable.

> It would probably be worth referring to drivers like this as "for
> Qualcomm MSM/QSD SoCs" or the like, since they do work with a lot of
> hardware beyond just Dream.

Well, the Dream is why I'm doing it, hence patch title. Of course,
Kconfig should say 'Qualcomm MSM/QSD SoCs', too.

Sorry for world record in checkpatch warnings. I checked .c files, but
somehow forgot about .h files.
									Pavel

---

Fix checkpatch warnings in HTC Dream display driver.

Signed-off-by: Pavel Machek <pa...@uc...>

diff --git a/drivers/video/msm/mddi_hw.h b/drivers/video/msm/mddi_hw.h
index 0cb55eb..45cc01f 100644
--- a/drivers/video/msm/mddi_hw.h
+++ b/drivers/video/msm/mddi_hw.h
@@ -199,39 +199,39 @@ struct __attribute__((packed)) mddi_video_stream {
 	uint16_t client_id; /* 0 */
 
 	uint16_t video_data_format_descriptor;
-	/* format of each pixel in the Pixel Data in the present stream in the
-	 * present packet.
-	 * If bits [15:13] = 000 monochrome
-	 * If bits [15:13] = 001 color pixels (palette).
-	 * If bits [15:13] = 010 color pixels in raw RGB
-	 * If bits [15:13] = 011 data in 4:2:2 Y Cb Cr format
-	 * If bits [15:13] = 100 Bayer pixels
-	 */
+/* format of each pixel in the Pixel Data in the present stream in the
+ * present packet.
+ * If bits [15:13] = 000 monochrome
+ * If bits [15:13] = 001 color pixels (palette).
+ * If bits [15:13] = 010 color pixels in raw RGB
+ * If bits [15:13] = 011 data in 4:2:2 Y Cb Cr format
+ * If bits [15:13] = 100 Bayer pixels
+ */
 
 	uint16_t pixel_data_attributes;
-	/* interpreted as follows:
-	 * Bits [1:0] = 11  pixel data is displayed to both eyes
-	 * Bits [1:0] = 10  pixel data is routed to the left eye only.
-	 * Bits [1:0] = 01  pixel data is routed to the right eye only.
-	 * Bits [1:0] = 00  pixel data is routed to the alternate display.
-	 * Bit 2 is 0  Pixel Data is in the standard progressive format.
-	 * Bit 2 is 1  Pixel Data is in interlace format.
-	 * Bit 3 is 0  Pixel Data is in the standard progressive format.
-	 * Bit 3 is 1  Pixel Data is in alternate pixel format.
-	 * Bit 4 is 0  Pixel Data is to or from the display frame buffer.
-	 * Bit 4 is 1  Pixel Data is to or from the camera.
-	 * Bit 5 is 0  pixel data contains the next consecutive row of pixels.
-	 * Bit 5 is 1  X Left Edge, Y Top Edge, X Right Edge, Y Bottom Edge,
-	 *             X Start, and Y Start parameters are not defined and
-	 *             shall be ignored by the client.
-	 * Bits [7:6] = 01  Pixel data is written to the offline image buffer.
-	 * Bits [7:6] = 00  Pixel data is written to the buffer to refresh display.
-	 * Bits [7:6] = 11  Pixel data is written to all image buffers.
-	 * Bits [7:6] = 10  Invalid. Reserved for future use.
-	 * Bits 8 through 11 alternate display number.
-	 * Bits 12 through 14 are reserved for future use and shall be set to zero.
-	 * Bit 15 is 1 the row of pixels is the last row of pixels in a frame.
-	 */
+/* interpreted as follows:
+ * Bits [1:0] = 11  pixel data is displayed to both eyes
+ * Bits [1:0] = 10  pixel data is routed to the left eye only.
+ * Bits [1:0] = 01  pixel data is routed to the right eye only.
+ * Bits [1:0] = 00  pixel data is routed to the alternate display.
+ * Bit 2 is 0  Pixel Data is in the standard progressive format.
+ * Bit 2 is 1  Pixel Data is in interlace format.
+ * Bit 3 is 0  Pixel Data is in the standard progressive format.
+ * Bit 3 is 1  Pixel Data is in alternate pixel format.
+ * Bit 4 is 0  Pixel Data is to or from the display frame buffer.
+ * Bit 4 is 1  Pixel Data is to or from the camera.
+ * Bit 5 is 0  pixel data contains the next consecutive row of pixels.
+ * Bit 5 is 1  X Left Edge, Y Top Edge, X Right Edge, Y Bottom Edge,
+ *             X Start, and Y Start parameters are not defined and
+ *             shall be ignored by the client.
+ * Bits [7:6] = 01  Pixel data is written to the offline image buffer.
+ * Bits [7:6] = 00  Pixel data is written to the buffer to refresh display.
+ * Bits [7:6] = 11  Pixel data is written to all image buffers.
+ * Bits [7:6] = 10  Invalid. Reserved for future use.
+ * Bits 8 through 11 alternate display number.
+ * Bits 12 through 14 are reserved for future use and shall be set to zero.
+ * Bit 15 is 1 the row of pixels is the last row of pixels in a frame.
+ */
 
 	uint16_t x_left_edge;
 	uint16_t y_top_edge;
@@ -239,17 +239,19 @@ struct __attribute__((packed)) mddi_video_stream {
 
 	uint16_t x_right_edge;
 	uint16_t y_bottom_edge;
-	/*  X,Y coordinate of the bottom right edge of the window being updated. */
+	/* X,Y coordinate of the bottom right edge of the window being
+	 * updated. */
 
 	uint16_t x_start;
 	uint16_t y_start;
-	/*  (X Start, Y Start) is the first pixel in the Pixel Data field below. */
+	/* (X Start, Y Start) is the first pixel in the Pixel Data field
+	 * below. */
 
 	uint16_t pixel_count;
-	/*  number of pixels in the Pixel Data field below. */
+	/* number of pixels in the Pixel Data field below. */
 
 	uint16_t parameter_CRC;
-	/*  16-bit CRC of all bytes from the Packet Length to the Pixel Count. */
+	/* 16-bit CRC of all bytes from the Packet Length to the Pixel Count. */
 
 	uint16_t reserved;
 	/* 16-bit variable to make structure align on 4 byte boundary */
diff --git a/drivers/video/msm/mdp_hw.h b/drivers/video/msm/mdp_hw.h
index d78dafa..4e3deb4 100644
--- a/drivers/video/msm/mdp_hw.h
+++ b/drivers/video/msm/mdp_hw.h
@@ -20,7 +20,7 @@
 
 struct mdp_info {
 	struct mdp_device mdp_dev;
-	char* __iomem base;
+	char * __iomem base;
 	int irq;
 };
 struct mdp_blit_req;
@@ -32,149 +32,149 @@ int mdp_ppp_blit(const struct mdp_info *mdp, struct mdp_blit_req *req,
 #define mdp_writel(mdp, value, offset) writel(value, mdp->base + offset)
 #define mdp_readl(mdp, offset) readl(mdp->base + offset)
 
-#define MDP_SYNC_CONFIG_0                ( 0x00000)
-#define MDP_SYNC_CONFIG_1                ( 0x00004)
-#define MDP_SYNC_CONFIG_2                ( 0x00008)
-#define MDP_SYNC_STATUS_0                ( 0x0000c)
-#define MDP_SYNC_STATUS_1                ( 0x00010)
-#define MDP_SYNC_STATUS_2                ( 0x00014)
-#define MDP_SYNC_THRESH_0                ( 0x00018)
-#define MDP_SYNC_THRESH_1                ( 0x0001c)
-#define MDP_INTR_ENABLE                  ( 0x00020)
-#define MDP_INTR_STATUS                  ( 0x00024)
-#define MDP_INTR_CLEAR                   ( 0x00028)
-#define MDP_DISPLAY0_START               ( 0x00030)
-#define MDP_DISPLAY1_START               ( 0x00034)
-#define MDP_DISPLAY_STATUS               ( 0x00038)
-#define MDP_EBI2_LCD0                    ( 0x0003c)
-#define MDP_EBI2_LCD1                    ( 0x00040)
-#define MDP_DISPLAY0_ADDR                ( 0x00054)
-#define MDP_DISPLAY1_ADDR                ( 0x00058)
-#define MDP_EBI2_PORTMAP_MODE            ( 0x0005c)
-#define MDP_MODE                         ( 0x00060)
-#define MDP_TV_OUT_STATUS                ( 0x00064)
-#define MDP_HW_VERSION                   ( 0x00070)
-#define MDP_SW_RESET                     ( 0x00074)
-#define MDP_AXI_ERROR_MASTER_STOP        ( 0x00078)
-#define MDP_SEL_CLK_OR_HCLK_TEST_BUS     ( 0x0007c)
-#define MDP_PRIMARY_VSYNC_OUT_CTRL       ( 0x00080)
-#define MDP_SECONDARY_VSYNC_OUT_CTRL     ( 0x00084)
-#define MDP_EXTERNAL_VSYNC_OUT_CTRL      ( 0x00088)
-#define MDP_VSYNC_CTRL                   ( 0x0008c)
-#define MDP_CGC_EN                       ( 0x00100)
-#define MDP_CMD_STATUS                   ( 0x10008)
-#define MDP_PROFILE_EN                   ( 0x10010)
-#define MDP_PROFILE_COUNT                ( 0x10014)
-#define MDP_DMA_START                    ( 0x10044)
-#define MDP_FULL_BYPASS_WORD0            ( 0x10100)
-#define MDP_FULL_BYPASS_WORD1            ( 0x10104)
-#define MDP_COMMAND_CONFIG               ( 0x10104)
-#define MDP_FULL_BYPASS_WORD2            ( 0x10108)
-#define MDP_FULL_BYPASS_WORD3            ( 0x1010c)
-#define MDP_FULL_BYPASS_WORD4            ( 0x10110)
-#define MDP_FULL_BYPASS_WORD6            ( 0x10118)
-#define MDP_FULL_BYPASS_WORD7            ( 0x1011c)
-#define MDP_FULL_BYPASS_WORD8            ( 0x10120)
-#define MDP_FULL_BYPASS_WORD9            ( 0x10124)
-#define MDP_PPP_SOURCE_CONFIG            ( 0x10124)
-#define MDP_FULL_BYPASS_WORD10           ( 0x10128)
-#define MDP_FULL_BYPASS_WORD11           ( 0x1012c)
-#define MDP_FULL_BYPASS_WORD12           ( 0x10130)
-#define MDP_FULL_BYPASS_WORD13           ( 0x10134)
-#define MDP_FULL_BYPASS_WORD14           ( 0x10138)
-#define MDP_PPP_OPERATION_CONFIG         ( 0x10138)
-#define MDP_FULL_BYPASS_WORD15           ( 0x1013c)
-#define MDP_FULL_BYPASS_WORD16           ( 0x10140)
-#define MDP_FULL_BYPASS_WORD17           ( 0x10144)
-#define MDP_FULL_BYPASS_WORD18           ( 0x10148)
-#define MDP_FULL_BYPASS_WORD19           ( 0x1014c)
-#define MDP_FULL_BYPASS_WORD20           ( 0x10150)
-#define MDP_PPP_DESTINATION_CONFIG       ( 0x10150)
-#define MDP_FULL_BYPASS_WORD21           ( 0x10154)
-#define MDP_FULL_BYPASS_WORD22           ( 0x10158)
-#define MDP_FULL_BYPASS_WORD23           ( 0x1015c)
-#define MDP_FULL_BYPASS_WORD24           ( 0x10160)
-#define MDP_FULL_BYPASS_WORD25           ( 0x10164)
-#define MDP_FULL_BYPASS_WORD26           ( 0x10168)
-#define MDP_FULL_BYPASS_WORD27           ( 0x1016c)
-#define MDP_FULL_BYPASS_WORD29           ( 0x10174)
-#define MDP_FULL_BYPASS_WORD30           ( 0x10178)
-#define MDP_FULL_BYPASS_WORD31           ( 0x1017c)
-#define MDP_FULL_BYPASS_WORD32           ( 0x10180)
-#define MDP_DMA_CONFIG                   ( 0x10180)
-#define MDP_FULL_BYPASS_WORD33           ( 0x10184)
-#define MDP_FULL_BYPASS_WORD34           ( 0x10188)
-#define MDP_FULL_BYPASS_WORD35           ( 0x1018c)
-#define MDP_FULL_BYPASS_WORD37           ( 0x10194)
-#define MDP_FULL_BYPASS_WORD39           ( 0x1019c)
-#define MDP_FULL_BYPASS_WORD40           ( 0x101a0)
-#define MDP_FULL_BYPASS_WORD41           ( 0x101a4)
-#define MDP_FULL_BYPASS_WORD43           ( 0x101ac)
-#define MDP_FULL_BYPASS_WORD46           ( 0x101b8)
-#define MDP_FULL_BYPASS_WORD47           ( 0x101bc)
-#define MDP_FULL_BYPASS_WORD48           ( 0x101c0)
-#define MDP_FULL_BYPASS_WORD49           ( 0x101c4)
-#define MDP_FULL_BYPASS_WORD50           ( 0x101c8)
-#define MDP_FULL_BYPASS_WORD51           ( 0x101cc)
-#define MDP_FULL_BYPASS_WORD52           ( 0x101d0)
-#define MDP_FULL_BYPASS_WORD53           ( 0x101d4)
-#define MDP_FULL_BYPASS_WORD54           ( 0x101d8)
-#define MDP_FULL_BYPASS_WORD55           ( 0x101dc)
-#define MDP_FULL_BYPASS_WORD56           ( 0x101e0)
-#define MDP_FULL_BYPASS_WORD57           ( 0x101e4)
-#define MDP_FULL_BYPASS_WORD58           ( 0x101e8)
-#define MDP_FULL_BYPASS_WORD59           ( 0x101ec)
-#define MDP_FULL_BYPASS_WORD60           ( 0x101f0)
-#define MDP_VSYNC_THRESHOLD              ( 0x101f0)
-#define MDP_FULL_BYPASS_WORD61           ( 0x101f4)
-#define MDP_FULL_BYPASS_WORD62           ( 0x101f8)
-#define MDP_FULL_BYPASS_WORD63           ( 0x101fc)
-#define MDP_TFETCH_TEST_MODE             ( 0x20004)
-#define MDP_TFETCH_STATUS                ( 0x20008)
-#define MDP_TFETCH_TILE_COUNT            ( 0x20010)
-#define MDP_TFETCH_FETCH_COUNT           ( 0x20014)
-#define MDP_TFETCH_CONSTANT_COLOR        ( 0x20040)
-#define MDP_CSC_BYPASS                   ( 0x40004)
-#define MDP_SCALE_COEFF_LSB              ( 0x5fffc)
-#define MDP_TV_OUT_CTL                   ( 0xc0000)
-#define MDP_TV_OUT_FIR_COEFF             ( 0xc0004)
-#define MDP_TV_OUT_BUF_ADDR              ( 0xc0008)
-#define MDP_TV_OUT_CC_DATA               ( 0xc000c)
-#define MDP_TV_OUT_SOBEL                 ( 0xc0010)
-#define MDP_TV_OUT_Y_CLAMP               ( 0xc0018)
-#define MDP_TV_OUT_CB_CLAMP              ( 0xc001c)
-#define MDP_TV_OUT_CR_CLAMP              ( 0xc0020)
-#define MDP_TEST_MODE_CLK                ( 0xd0000)
-#define MDP_TEST_MISR_RESET_CLK          ( 0xd0004)
-#define MDP_TEST_EXPORT_MISR_CLK         ( 0xd0008)
-#define MDP_TEST_MISR_CURR_VAL_CLK       ( 0xd000c)
-#define MDP_TEST_MODE_HCLK               ( 0xd0100)
-#define MDP_TEST_MISR_RESET_HCLK         ( 0xd0104)
-#define MDP_TEST_EXPORT_MISR_HCLK        ( 0xd0108)
-#define MDP_TEST_MISR_CURR_VAL_HCLK      ( 0xd010c)
-#define MDP_TEST_MODE_DCLK               ( 0xd0200)
-#define MDP_TEST_MISR_RESET_DCLK         ( 0xd0204)
-#define MDP_TEST_EXPORT_MISR_DCLK        ( 0xd0208)
-#define MDP_TEST_MISR_CURR_VAL_DCLK      ( 0xd020c)
-#define MDP_TEST_CAPTURED_DCLK           ( 0xd0210)
-#define MDP_TEST_MISR_CAPT_VAL_DCLK      ( 0xd0214)
-#define MDP_LCDC_CTL                     ( 0xe0000)
-#define MDP_LCDC_HSYNC_CTL               ( 0xe0004)
-#define MDP_LCDC_VSYNC_CTL               ( 0xe0008)
-#define MDP_LCDC_ACTIVE_HCTL             ( 0xe000c)
-#define MDP_LCDC_ACTIVE_VCTL             ( 0xe0010)
-#define MDP_LCDC_BORDER_CLR              ( 0xe0014)
-#define MDP_LCDC_H_BLANK                 ( 0xe0018)
-#define MDP_LCDC_V_BLANK                 ( 0xe001c)
-#define MDP_LCDC_UNDERFLOW_CLR           ( 0xe0020)
-#define MDP_LCDC_HSYNC_SKEW              ( 0xe0024)
-#define MDP_LCDC_TEST_CTL                ( 0xe0028)
-#define MDP_LCDC_LINE_IRQ                ( 0xe002c)
-#define MDP_LCDC_CTL_POLARITY            ( 0xe0030)
-#define MDP_LCDC_DMA_CONFIG              ( 0xe1000)
-#define MDP_LCDC_DMA_SIZE                ( 0xe1004)
-#define MDP_LCDC_DMA_IBUF_ADDR           ( 0xe1008)
-#define MDP_LCDC_DMA_IBUF_Y_STRIDE       ( 0xe100c)
+#define MDP_SYNC_CONFIG_0                (0x00000)
+#define MDP_SYNC_CONFIG_1                (0x00004)
+#define MDP_SYNC_CONFIG_2                (0x00008)
+#define MDP_SYNC_STATUS_0                (0x0000c)
+#define MDP_SYNC_STATUS_1                (0x00010)
+#define MDP_SYNC_STATUS_2                (0x00014)
+#define MDP_SYNC_THRESH_0                (0x00018)
+#define MDP_SYNC_THRESH_1                (0x0001c)
+#define MDP_INTR_ENABLE                  (0x00020)
+#define MDP_INTR_STATUS                  (0x00024)
+#define MDP_INTR_CLEAR                   (0x00028)
+#define MDP_DISPLAY0_START               (0x00030)
+#define MDP_DISPLAY1_START               (0x00034)
+#define MDP_DISPLAY_STATUS               (0x00038)
+#define MDP_EBI2_LCD0                    (0x0003c)
+#define MDP_EBI2_LCD1                    (0x00040)
+#define MDP_DISPLAY0_ADDR                (0x00054)
+#define MDP_DISPLAY1_ADDR                (0x00058)
+#define MDP_EBI2_PORTMAP_MODE            (0x0005c)
+#define MDP_MODE                         (0x00060)
+#define MDP_TV_OUT_STATUS                (0x00064)
+#define MDP_HW_VERSION                   (0x00070)
+#define MDP_SW_RESET                     (0x00074)
+#define MDP_AXI_ERROR_MASTER_STOP        (0x00078)
+#define MDP_SEL_CLK_OR_HCLK_TEST_BUS     (0x0007c)
+#define MDP_PRIMARY_VSYNC_OUT_CTRL       (0x00080)
+#define MDP_SECONDARY_VSYNC_OUT_CTRL     (0x00084)
+#define MDP_EXTERNAL_VSYNC_OUT_CTRL      (0x00088)
+#define MDP_VSYNC_CTRL                   (0x0008c)
+#define MDP_CGC_EN                       (0x00100)
+#define MDP_CMD_STATUS                   (0x10008)
+#define MDP_PROFILE_EN                   (0x10010)
+#define MDP_PROFILE_COUNT                (0x10014)
+#define MDP_DMA_START                    (0x10044)
+#define MDP_FULL_BYPASS_WORD0            (0x10100)
+#define MDP_FULL_BYPASS_WORD1            (0x10104)
+#define MDP_COMMAND_CONFIG               (0x10104)
+#define MDP_FULL_BYPASS_WORD2            (0x10108)
+#define MDP_FULL_BYPASS_WORD3            (0x1010c)
+#define MDP_FULL_BYPASS_WORD4            (0x10110)
+#define MDP_FULL_BYPASS_WORD6            (0x10118)
+#define MDP_FULL_BYPASS_WORD7            (0x1011c)
+#define MDP_FULL_BYPASS_WORD8            (0x10120)
+#define MDP_FULL_BYPASS_WORD9            (0x10124)
+#define MDP_PPP_SOURCE_CONFIG            (0x10124)
+#define MDP_FULL_BYPASS_WORD10           (0x10128)
+#define MDP_FULL_BYPASS_WORD11           (0x1012c)
+#define MDP_FULL_BYPASS_WORD12           (0x10130)
+#define MDP_FULL_BYPASS_WORD13           (0x10134)
+#define MDP_FULL_BYPASS_WORD14           (0x10138)
+#define MDP_PPP_OPERATION_CONFIG         (0x10138)
+#define MDP_FULL_BYPASS_WORD15           (0x1013c)
+#define MDP_FULL_BYPASS_WORD16           (0x10140)
+#define MDP_FULL_BYPASS_WORD17           (0x10144)
+#define MDP_FULL_BYPASS_WORD18           (0x10148)
+#define MDP_FULL_BYPASS_WORD19           (0x1014c)
+#define MDP_FULL_BYPASS_WORD20           (0x10150)
+#define MDP_PPP_DESTINATION_CONFIG       (0x10150)
+#define MDP_FULL_BYPASS_WORD21           (0x10154)
+#define MDP_FULL_BYPASS_WORD22           (0x10158)
+#define MDP_FULL_BYPASS_WORD23           (0x1015c)
+#define MDP_FULL_BYPASS_WORD24           (0x10160)
+#define MDP_FULL_BYPASS_WORD25           (0x10164)
+#define MDP_FULL_BYPASS_WORD26           (0x10168)
+#define MDP_FULL_BYPASS_WORD27           (0x1016c)
+#define MDP_FULL_BYPASS_WORD29           (0x10174)
+#define MDP_FULL_BYPASS_WORD30           (0x10178)
+#define MDP_FULL_BYPASS_WORD31           (0x1017c)
+#define MDP_FULL_BYPASS_WORD32           (0x10180)
+#define MDP_DMA_CONFIG                   (0x10180)
+#define MDP_FULL_BYPASS_WORD33           (0x10184)
+#define MDP_FULL_BYPASS_WORD34           (0x10188)
+#define MDP_FULL_BYPASS_WORD35           (0x1018c)
+#define MDP_FULL_BYPASS_WORD37           (0x10194)
+#define MDP_FULL_BYPASS_WORD39           (0x1019c)
+#define MDP_FULL_BYPASS_WORD40           (0x101a0)
+#define MDP_FULL_BYPASS_WORD41           (0x101a4)
+#define MDP_FULL_BYPASS_WORD43           (0x101ac)
+#define MDP_FULL_BYPASS_WORD46           (0x101b8)
+#define MDP_FULL_BYPASS_WORD47           (0x101bc)
+#define MDP_FULL_BYPASS_WORD48           (0x101c0)
+#define MDP_FULL_BYPASS_WORD49           (0x101c4)
+#define MDP_FULL_BYPASS_WORD50           (0x101c8)
+#define MDP_FULL_BYPASS_WORD51           (0x101cc)
+#define MDP_FULL_BYPASS_WORD52           (0x101d0)
+#define MDP_FULL_BYPASS_WORD53           (0x101d4)
+#define MDP_FULL_BYPASS_WORD54           (0x101d8)
+#define MDP_FULL_BYPASS_WORD55           (0x101dc)
+#define MDP_FULL_BYPASS_WORD56           (0x101e0)
+#define MDP_FULL_BYPASS_WORD57           (0x101e4)
+#define MDP_FULL_BYPASS_WORD58           (0x101e8)
+#define MDP_FULL_BYPASS_WORD59           (0x101ec)
+#define MDP_FULL_BYPASS_WORD60           (0x101f0)
+#define MDP_VSYNC_THRESHOLD              (0x101f0)
+#define MDP_FULL_BYPASS_WORD61           (0x101f4)
+#define MDP_FULL_BYPASS_WORD62           (0x101f8)
+#define MDP_FULL_BYPASS_WORD63           (0x101fc)
+#define MDP_TFETCH_TEST_MODE             (0x20004)
+#define MDP_TFETCH_STATUS                (0x20008)
+#define MDP_TFETCH_TILE_COUNT            (0x20010)
+#define MDP_TFETCH_FETCH_COUNT           (0x20014)
+#define MDP_TFETCH_CONSTANT_COLOR        (0x20040)
+#define MDP_CSC_BYPASS                   (0x40004)
+#define MDP_SCALE_COEFF_LSB              (0x5fffc)
+#define MDP_TV_OUT_CTL                   (0xc0000)
+#define MDP_TV_OUT_FIR_COEFF             (0xc0004)
+#define MDP_TV_OUT_BUF_ADDR              (0xc0008)
+#define MDP_TV_OUT_CC_DATA               (0xc000c)
+#define MDP_TV_OUT_SOBEL                 (0xc0010)
+#define MDP_TV_OUT_Y_CLAMP               (0xc0018)
+#define MDP_TV_OUT_CB_CLAMP              (0xc001c)
+#define MDP_TV_OUT_CR_CLAMP              (0xc0020)
+#define MDP_TEST_MODE_CLK                (0xd0000)
+#define MDP_TEST_MISR_RESET_CLK          (0xd0004)
+#define MDP_TEST_EXPORT_MISR_CLK         (0xd0008)
+#define MDP_TEST_MISR_CURR_VAL_CLK       (0xd000c)
+#define MDP_TEST_MODE_HCLK               (0xd0100)
+#define MDP_TEST_MISR_RESET_HCLK         (0xd0104)
+#define MDP_TEST_EXPORT_MISR_HCLK        (0xd0108)
+#define MDP_TEST_MISR_CURR_VAL_HCLK      (0xd010c)
+#define MDP_TEST_MODE_DCLK               (0xd0200)
+#define MDP_TEST_MISR_RESET_DCLK         (0xd0204)
+#define MDP_TEST_EXPORT_MISR_DCLK        (0xd0208)
+#define MDP_TEST_MISR_CURR_VAL_DCLK      (0xd020c)
+#define MDP_TEST_CAPTURED_DCLK           (0xd0210)
+#define MDP_TEST_MISR_CAPT_VAL_DCLK      (0xd0214)
+#define MDP_LCDC_CTL                     (0xe0000)
+#define MDP_LCDC_HSYNC_CTL               (0xe0004)
+#define MDP_LCDC_VSYNC_CTL               (0xe0008)
+#define MDP_LCDC_ACTIVE_HCTL             (0xe000c)
+#define MDP_LCDC_ACTIVE_VCTL             (0xe0010)
+#define MDP_LCDC_BORDER_CLR              (0xe0014)
+#define MDP_LCDC_H_BLANK                 (0xe0018)
+#define MDP_LCDC_V_BLANK                 (0xe001c)
+#define MDP_LCDC_UNDERFLOW_CLR           (0xe0020)
+#define MDP_LCDC_HSYNC_SKEW              (0xe0024)
+#define MDP_LCDC_TEST_CTL                (0xe0028)
+#define MDP_LCDC_LINE_IRQ                (0xe002c)
+#define MDP_LCDC_CTL_POLARITY            (0xe0030)
+#define MDP_LCDC_DMA_CONFIG              (0xe1000)
+#define MDP_LCDC_DMA_SIZE                (0xe1004)
+#define MDP_LCDC_DMA_IBUF_ADDR           (0xe1008)
+#define MDP_LCDC_DMA_IBUF_Y_STRIDE       (0xe100c)
 
 
 #define MDP_DMA2_TERM 0x1
@@ -246,11 +246,11 @@ int mdp_ppp_blit(const struct mdp_info *mdp, struct mdp_blit_req *req,
 /* MDP_VSYNC_CTRL */
 #define DISP0_VSYNC_MAP_VSYNC0 0
 #define DISP0_VSYNC_MAP_VSYNC1 (1<<0)
-#define DISP0_VSYNC_MAP_VSYNC2 (1<<0)|(1<<1)
+#define DISP0_VSYNC_MAP_VSYNC2 ((1<<0)|(1<<1))
 
 #define DISP1_VSYNC_MAP_VSYNC0 0
 #define DISP1_VSYNC_MAP_VSYNC1 (1<<2)
-#define DISP1_VSYNC_MAP_VSYNC2 (1<<2)|(1<<3)
+#define DISP1_VSYNC_MAP_VSYNC2 ((1<<2)|(1<<3))
 
 #define PRIMARY_LCD_SYNC_EN (1<<4)
 #define PRIMARY_LCD_SYNC_DISABLE 0
@@ -368,7 +368,7 @@ int mdp_ppp_blit(const struct mdp_info *mdp, struct mdp_blit_req *req,
 #define PPP_OP_BG_CHROMA_RGB 0
 #define PPP_OP_BG_CHROMA_H2V1 (1<<25)
 #define PPP_OP_BG_CHROMA_H1V2 (1<<26)
-#define PPP_OP_BG_CHROMA_420 (1<<25)|(1<<26)
+#define PPP_OP_BG_CHROMA_420 ((1<<25)|(1<<26))
 #define PPP_OP_BG_CHROMA_SITE_COSITE 0
 #define PPP_OP_BG_CHROMA_SITE_OFFSITE (1<<27)
 
@@ -417,25 +417,25 @@ int mdp_ppp_blit(const struct mdp_info *mdp, struct mdp_blit_req *req,
 #define PPP_DST_MDDI_EXTERNAL (1<<22)
 
 /* image configurations by image type */
-#define PPP_CFG_MDP_RGB_565(dir)	PPP_##dir##_C2R_5BIT | \
+#define PPP_CFG_MDP_RGB_565(dir)       (PPP_##dir##_C2R_5BIT | \
 					PPP_##dir##_C0G_6BIT | \
 					PPP_##dir##_C1B_5BIT | \
 					PPP_##dir##_BPP_2BYTES | \
 					PPP_##dir##_INTERLVD_3COMPONENTS | \
 					PPP_##dir##_PACK_TIGHT | \
 					PPP_##dir##_PACK_ALIGN_LSB | \
-					PPP_##dir##_PLANE_INTERLVD
+					PPP_##dir##_PLANE_INTERLVD)
 
-#define PPP_CFG_MDP_RGB_888(dir)	PPP_##dir##_C2R_8BIT | \
+#define PPP_CFG_MDP_RGB_888(dir)       (PPP_##dir##_C2R_8BIT | \
 					PPP_##dir##_C0G_8BIT | \
 					PPP_##dir##_C1B_8BIT | \
 					PPP_##dir##_BPP_3BYTES | \
 					PPP_##dir##_INTERLVD_3COMPONENTS | \
 					PPP_##dir##_PACK_TIGHT | \
 					PPP_##dir##_PACK_ALIGN_LSB | \
-					PPP_##dir##_PLANE_INTERLVD
+					PPP_##dir##_PLANE_INTERLVD)
 
-#define PPP_CFG_MDP_ARGB_8888(dir)	PPP_##dir##_C2R_8BIT | \
+#define PPP_CFG_MDP_ARGB_8888(dir)     (PPP_##dir##_C2R_8BIT | \
 					PPP_##dir##_C0G_8BIT | \
 					PPP_##dir##_C1B_8BIT | \
 					PPP_##dir##_C3A_8BIT | \
@@ -444,13 +444,13 @@ int mdp_ppp_blit(const struct mdp_info *mdp, struct mdp_blit_req *req,
 					PPP_##dir##_INTERLVD_4COMPONENTS | \
 					PPP_##dir##_PACK_TIGHT | \
 					PPP_##dir##_PACK_ALIGN_LSB | \
-					PPP_##dir##_PLANE_INTERLVD
+					PPP_##dir##_PLANE_INTERLVD)
 
 #define PPP_CFG_MDP_XRGB_8888(dir) PPP_CFG_MDP_ARGB_8888(dir)
 #define PPP_CFG_MDP_RGBA_8888(dir) PPP_CFG_MDP_ARGB_8888(dir)
 #define PPP_CFG_MDP_BGRA_8888(dir) PPP_CFG_MDP_ARGB_8888(dir)
 
-#define PPP_CFG_MDP_Y_CBCR_H2V2(dir)	PPP_##dir##_C2R_8BIT | \
+#define PPP_CFG_MDP_Y_CBCR_H2V2(dir)   (PPP_##dir##_C2R_8BIT | \
 					PPP_##dir##_C0G_8BIT | \
 					PPP_##dir##_C1B_8BIT | \
 					PPP_##dir##_C3A_8BIT | \
@@ -458,11 +458,11 @@ int mdp_ppp_blit(const struct mdp_info *mdp, struct mdp_blit_req *req,
 					PPP_##dir##_INTERLVD_2COMPONENTS | \
 					PPP_##dir##_PACK_TIGHT | \
 					PPP_##dir##_PACK_ALIGN_LSB | \
-					PPP_##dir##_PLANE_PSEUDOPLNR
+					PPP_##dir##_PLANE_PSEUDOPLNR)
 
 #define PPP_CFG_MDP_Y_CRCB_H2V2(dir)	PPP_CFG_MDP_Y_CBCR_H2V2(dir)
 
-#define PPP_CFG_MDP_YCRYCB_H2V1(dir)	PPP_##dir##_C2R_8BIT | \
+#define PPP_CFG_MDP_YCRYCB_H2V1(dir)   (PPP_##dir##_C2R_8BIT | \
 					PPP_##dir##_C0G_8BIT | \
 					PPP_##dir##_C1B_8BIT | \
 					PPP_##dir##_C3A_8BIT | \
@@ -470,9 +470,9 @@ int mdp_ppp_blit(const struct mdp_info *mdp, struct mdp_blit_req *req,
 					PPP_##dir##_INTERLVD_4COMPONENTS | \
 					PPP_##dir##_PACK_TIGHT | \
 					PPP_##dir##_PACK_ALIGN_LSB |\
-					PPP_##dir##_PLANE_INTERLVD
+					PPP_##dir##_PLANE_INTERLVD)
 
-#define PPP_CFG_MDP_Y_CBCR_H2V1(dir)	PPP_##dir##_C2R_8BIT | \
+#define PPP_CFG_MDP_Y_CBCR_H2V1(dir)   (PPP_##dir##_C2R_8BIT | \
 					PPP_##dir##_C0G_8BIT | \
 					PPP_##dir##_C1B_8BIT | \
 					PPP_##dir##_C3A_8BIT | \
@@ -480,7 +480,7 @@ int mdp_ppp_blit(const struct mdp_info *mdp, struct mdp_blit_req *req,
 					PPP_##dir##_INTERLVD_2COMPONENTS |  \
 					PPP_##dir##_PACK_TIGHT | \
 					PPP_##dir##_PACK_ALIGN_LSB | \
-					PPP_##dir##_PLANE_PSEUDOPLNR
+					PPP_##dir##_PLANE_PSEUDOPLNR)
 
 #define PPP_CFG_MDP_Y_CRCB_H2V1(dir)	PPP_CFG_MDP_Y_CBCR_H2V1(dir)
 
@@ -549,7 +549,7 @@ int mdp_ppp_blit(const struct mdp_info *mdp, struct mdp_blit_req *req,
 		     (img == MDP_ARGB_8888) | (img == MDP_RGBA_8888) | \
 		     (img == MDP_XRGB_8888) | (img == MDP_BGRA_8888))
 #define HAS_ALPHA(img) ((img == MDP_ARGB_8888) | (img == MDP_RGBA_8888) | \
-		        (img == MDP_BGRA_8888))
+			(img == MDP_BGRA_8888))
 
 #define IS_PSEUDOPLNR(img) ((img == MDP_Y_CRCB_H2V2) | \
 			    (img == MDP_Y_CBCR_H2V2) | \
diff --git a/drivers/video/msm/mdp_scale_tables.h b/drivers/video/msm/mdp_scale_tables.h
index 4e19a25..34077b1 100644
--- a/drivers/video/msm/mdp_scale_tables.h
+++ b/drivers/video/msm/mdp_scale_tables.h
@@ -31,8 +31,8 @@ enum {
 	MDP_DOWNSCALE_MAX,
 };
 
-extern struct mdp_table_entry* mdp_downscale_x_table[MDP_DOWNSCALE_MAX];
-extern struct mdp_table_entry* mdp_downscale_y_table[MDP_DOWNSCALE_MAX];
+extern struct mdp_table_entry *mdp_downscale_x_table[MDP_DOWNSCALE_MAX];
+extern struct mdp_table_entry *mdp_downscale_y_table[MDP_DOWNSCALE_MAX];
 extern struct mdp_table_entry mdp_gaussian_blur_table[];
 
-#endif  //_MDP_SCALE_TABLES_H_
+#endif




-- 
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html